2 * Copyright © 2013 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
23 typedef volatile uint32_t vuint32_t;
24 typedef volatile uint16_t vuint16_t;
25 typedef volatile uint8_t vuint8_t;
26 typedef volatile void * vvoid_t;
59 vuint32_t pio1_0; /* 0x60 */
69 vuint32_t pio1_8; /* 0x80 */
79 vuint32_t pio1_16; /* 0xa0 */
89 vuint32_t pio1_24; /* 0xc0 */
100 extern struct lpc_ioconf lpc_ioconf;
102 #define LPC_IOCONF_FUNC 0
105 #define LPC_IOCONF_FUNC_RESET 0
106 #define LPC_IOCONF_FUNC_PIO0_0 1
109 #define LPC_IOCONF_FUNC_PIO0_1 0
110 #define LPC_IOCONF_FUNC_CLKOUT 1
111 #define LPC_IOCONF_FUNC_CT32B0_MAT2 2
112 #define LPC_IOCONF_FUNC_USB_FTOGGLE 3
115 #define LPC_IOCONF_FUNC_PIO0_2 0
116 #define LPC_IOCONF_FUNC_SSEL0 1
117 #define LPC_IOCONF_FUNC_CT16B0_CAP0 2
120 #define LPC_IOCONF_FUNC_PIO0_3 0
121 #define LPC_IOCONF_FUNC_USB_VBUS 1
124 #define LPC_IOCONF_FUNC_PIO0_4 0
125 #define LPC_IOCONF_FUNC_I2C_SCL 1
128 #define LPC_IOCONF_FUNC_PIO0_5 0
129 #define LPC_IOCONF_FUNC_I2C_SDA 1
132 #define LPC_IOCONF_FUNC_PIO0_6 0
133 #define LPC_IOCONF_FUNC_USB_CONNECT 1
134 #define LPC_IOCONF_FUNC_SCK0 2
137 #define LPC_IOCONF_FUNC_PIO0_7 0
138 #define LPC_IOCONF_FUNC_CTS 1
141 #define LPC_IOCONF_FUNC_PIO0_8 0
142 #define LPC_IOCONF_FUNC_MISO0 1
143 #define LPC_IOCONF_FUNC_CT16B0_MAT0 2
146 #define LPC_IOCONF_FUNC_PIO0_9 0
147 #define LPC_IOCONF_FUNC_MOSI0 1
148 #define LPC_IOCONF_FUNC_CT16B0_MAT1 2
151 #define LPC_IOCONF_FUNC_SWCLK 0
152 #define LPC_IOCONF_FUNC_PIO0_10 1
153 #define LPC_IOCONF_FUNC_SCK0 2
154 #define LPC_IOCONF_FUNC_CT16B0_MAT2 3
157 #define LPC_IOCONF_FUNC_TDI 0
158 #define LPC_IOCONF_FUNC_PIO0_11 1
159 #define LPC_IOCONF_FUNC_AD0 2
160 #define LPC_IOCONF_FUNC_CT32B0_MAT3 3
163 #define LPC_IOCONF_FUNC_TMS 0
164 #define LPC_IOCONF_FUNC_PIO0_12 1
165 #define LPC_IOCONF_FUNC_AD1 2
166 #define LPC_IOCONF_FUNC_CT32B1_CAP0 3
169 #define LPC_IOCONF_FUNC_TD0 0
170 #define LPC_IOCONF_FUNC_PIO0_13 1
171 #define LPC_IOCONF_FUNC_AD2 2
172 #define LPC_IOCONF_FUNC_CT32B1_MAT0 3
175 #define LPC_IOCONF_FUNC_TRST 0
176 #define LPC_IOCONF_FUNC_PIO0_14 1
177 #define LPC_IOCONF_FUNC_AD3 2
178 #define LPC_IOCONF_FUNC_PIO0_14_CT32B1_MAT1 3
181 #define LPC_IOCONF_FUNC_SWDIO 0
182 #define LPC_IOCONF_FUNC_PIO0_15 1
183 #define LPC_IOCONF_FUNC_AD4 2
184 #define LPC_IOCONF_FUNC_CT32B1_MAT2 3
187 #define LPC_IOCONF_FUNC_PIO0_16 0
188 #define LPC_IOCONF_FUNC_AD5 1
189 #define LPC_IOCONF_FUNC_CT32B1_MAT3 2
192 #define LPC_IOCONF_FUNC_PIO0_17 0
193 #define LPC_IOCONF_FUNC_RTS 1
194 #define LPC_IOCONF_FUNC_CT32B0_CAP0 2
195 #define LPC_IOCONF_FUNC_SCLK 3
198 #define LPC_IOCONF_FUNC_PIO0_18 0
199 #define LPC_IOCONF_FUNC_PIO0_18_RXD 1
200 #define LPC_IOCONF_FUNC_PIO0_18_CT32B0_MAT0 2
203 #define LPC_IOCONF_FUNC_PIO0_19 0
204 #define LPC_IOCONF_FUNC_PIO0_19_TXD 1
205 #define LPC_IOCONF_FUNC_PIO0_19_CT32B0_MAT1 2
208 #define LPC_IOCONF_FUNC_PIO0_20 0
209 #define LPC_IOCONF_FUNC_CT16B1_CAP0 1
212 #define LPC_IOCONF_FUNC_PIO0_21 0
213 #define LPC_IOCONF_FUNC_CT16B1_MAT0 1
214 #define LPC_IOCONF_FUNC_MOSI1 2
217 #define LPC_IOCONF_FUNC_PIO0_22 0
218 #define LPC_IOCONF_FUNC_AD6 1
219 #define LPC_IOCONF_FUNC_CT16B1_MAT1 2
220 #define LPC_IOCONF_FUNC_MISO1 3
223 #define LPC_IOCONF_FUNC_PIO0_23 0
224 #define LPC_IOCONF_FUNC_AD7 1
227 #define LPC_IOCONF_FUNC_PIO1_0 0
228 #define LPC_IOCONF_FUNC_CT32B1_MAT1 1
231 #define LPC_IOCONF_FUNC_PIO1_1 0
232 #define LPC_IOCONF_FUNC_CT32B1_MAT1 1
235 #define LPC_IOCONF_FUNC_PIO1_2 0
236 #define LPC_IOCONF_FUNC_PIO1_2_CT32B1_MAT2 1
239 #define LPC_IOCONF_FUNC_PIO1_3 0
240 #define LPC_IOCONF_FUNC_PIO1_3_CT32B1_MAT3 1
243 #define LPC_IOCONF_FUNC_PIO1_4 0
244 #define LPC_IOCONF_FUNC_PIO1_4_CT32B1_CAP0 1
247 #define LPC_IOCONF_FUNC_PIO1_5 0
248 #define LPC_IOCONF_FUNC_CT32B1_CAP1 1
251 #define LPC_IOCONF_FUNC_PIO1_6 0
254 #define LPC_IOCONF_FUNC_PIO1_7 0
257 #define LPC_IOCONF_FUNC_PIO1_8 0
260 #define LPC_IOCONF_FUNC_PIO1_9 0
263 #define LPC_IOCONF_FUNC_PIO1_10 0
266 #define LPC_IOCONF_FUNC_PIO1_11 0
269 #define LPC_IOCONF_FUNC_PIO1_12 0
272 #define LPC_IOCONF_FUNC_PIO1_13 0
273 #define LPC_IOCONF_FUNC_DTR 1
274 #define LPC_IOCONF_FUNC_CT16B0_MAT0 2
275 #define LPC_IOCONF_FUNC_PIO1_13_TXD 3
278 #define LPC_IOCONF_FUNC_PIO1_14 0
279 #define LPC_IOCONF_FUNC_DSR 1
280 #define LPC_IOCONF_FUNC_CT16B0_MAT1 2
281 #define LPC_IOCONF_FUNC_PIO1_13_RXD 3
284 #define LPC_IOCONF_FUNC_PIO1_15 0
285 #define LPC_IOCONF_FUNC_DCD 1
286 #define LPC_IOCONF_FUNC_PIO1_15_CT16B0_MAT2 2
287 #define LPC_IOCONF_FUNC_SCK1 3
290 #define LPC_IOCONF_FUNC_PIO1_16 0
291 #define LPC_IOCONF_FUNC_RI 1
292 #define LPC_IOCONF_FUNC_CT16B0_CAP0 2
295 #define LPC_IOCONF_FUNC_PIO1_17 0
296 #define LPC_IOCONF_FUNC_CT16B0_CAP1 1
297 #define LPC_IOCONF_FUNC_PIO1_17_RXD 2
300 #define LPC_IOCONF_FUNC_PIO1_18 0
301 #define LPC_IOCONF_FUNC_CT16B1_CAP1 1
302 #define LPC_IOCONF_FUNC_PIO1_18_TXD 2
305 #define LPC_IOCONF_FUNC_PIO1_19 0
306 #define LPC_IOCONF_FUNC_DTR 1
307 #define LPC_IOCONF_FUNC_SSEL1 2
310 #define LPC_IOCONF_FUNC_PIO1_20 0
311 #define LPC_IOCONF_FUNC_DSR 1
312 #define LPC_IOCONF_FUNC_PIO1_20_SCK1 2
315 #define LPC_IOCONF_FUNC_PIO1_21 0
316 #define LPC_IOCONF_FUNC_DCD 1
317 #define LPC_IOCONF_FUNC_PIO1_21_MISO1 2
320 #define LPC_IOCONF_FUNC_PIO1_22 0
321 #define LPC_IOCONF_FUNC_RI 1
322 #define LPC_IOCONF_FUNC_MOSI1 2
325 #define LPC_IOCONF_FUNC_PIO1_23 0
326 #define LPC_IOCONF_FUNC_PIO1_23_CT16B1_MAT1 1
327 #define LPC_IOCONF_FUNC_SSEL1 2
330 #define LPC_IOCONF_FUNC_PIO1_24 0
331 #define LPC_IOCONF_FUNC_PIO1_24_CT32B0_MAT0 1
334 #define LPC_IOCONF_FUNC_PIO1_25 0
335 #define LPC_IOCONF_FUNC_PIO1_25_CT32B0_MAT1 1
338 #define LPC_IOCONF_FUNC_PIO1_26 0
339 #define LPC_IOCONF_FUNC_PIO1_26_CT32B0_MAT2 1
340 #define LPC_IOCONF_FUNC_PIO1_26_RXD 2
343 #define LPC_IOCONF_FUNC_PIO1_27 0
344 #define LPC_IOCONF_FUNC_PIO1_27_CT32B0_MAT3 1
345 #define LPC_IOCONF_FUNC_PIO1_27_TXD 2
348 #define LPC_IOCONF_FUNC_PIO1_28 0
349 #define LPC_IOCONF_FUNC_PIO1_28_CT32B0_CAP0 1
350 #define LPC_IOCONF_FUNC_PIO1_28_SCLK 2
353 #define LPC_IOCONF_FUNC_PIO1_29 0
354 #define LPC_IOCONF_FUNC_PIO1_29_SCK0 1
355 #define LPC_IOCONF_FUNC_PIO1_29_CT32B0_CAP1 2
358 #define LPC_IOCONF_FUNC_PIO1_31 0
360 #define LPC_IOCONF_FUNC_MASK 0x7
362 #define LPC_IOCONF_MODE 3
363 #define LPC_IOCONF_MODE_INACTIVE 0
364 #define LPC_IOCONF_MODE_PULL_DOWN 1
365 #define LPC_IOCONF_MODE_PULL_UP 2
366 #define LPC_IOCONF_MODE_REPEATER 3
367 #define LPC_IOCONF_MODE_MASK 3
369 #define LPC_IOCONF_HYS 5
371 #define LPC_IOCONF_INV 6
372 #define LPC_IOCONF_OD 10
375 vuint32_t sysmemremap; /* 0x00 */
376 vuint32_t presetctrl;
377 vuint32_t syspllctrl;
378 vuint32_t syspllstat;
380 vuint32_t usbpllctrl; /* 0x10 */
381 vuint32_t usbpllstat;
385 vuint32_t sysoscctrl; /* 0x20 */
386 vuint32_t wdtoscctrl;
390 vuint32_t sysrststat; /* 0x30 */
395 vuint32_t syspllclksel; /* 0x40 */
396 vuint32_t syspllclkuen;
397 vuint32_t usbpllclksel;
398 vuint32_t usbplllclkuen;
402 vuint32_t mainclksel; /* 0x70 */
403 vuint32_t mainclkuen;
404 vuint32_t sysahbclkdiv;
407 vuint32_t sysahbclkctrl; /* 0x80 */
410 uint32_t r90; /* 0x90 */
411 vuint32_t ssp0clkdiv;
412 vuint32_t uartclkdiv;
413 vuint32_t ssp1clkdiv;
417 vuint32_t usbclksel; /* 0xc0 */
424 vuint32_t clkoutsel; /* 0xe0 */
429 uint32_t rf0[4]; /* 0xf0 */
431 vuint32_t pioporcap0; /* 0x100 */
432 vuint32_t pioporcap1;
435 uint32_t r110[4]; /* 0x110 */
436 uint32_t r120[4]; /* 0x120 */
437 uint32_t r130[4]; /* 0x130 */
438 uint32_t r140[4]; /* 0x140 */
440 vuint32_t bodctrl; /* 0x150 */
444 uint32_t r160[4]; /* 0x160 */
446 vuint32_t irqlatency; /* 0x170 */
451 vuint32_t pintsel2; /* 0x180 */
456 vuint32_t pintsel6; /* 0x190 */
458 vuint32_t usbclkctrl;
461 uint32_t r1a0[6*4]; /* 0x1a0 */
463 uint32_t r200; /* 0x200 */
467 uint32_t r210; /* 0x210 */
471 uint32_t r220[4]; /* 0x220 */
473 vuint32_t pdsleepcfg; /* 0x230 */
474 vuint32_t pdawakecfg;
478 uint32_t r240[12 * 4]; /* 0x240 */
480 uint32_t r300[15 * 4]; /* 0x300 */
482 uint32_t r3f0; /* 0x3f0 */
486 extern struct lpc_scb lpc_scb;
488 #define LPC_SCB_PRESETCTRL_SSP0_RST_N 0
489 #define LPC_SCB_PRESETCTRL_I2C_RST_N 1
490 #define LPC_SCB_PRESETCTRL_SSP1_RST_N 2
492 #define LPC_SCB_SYSPLLCTRL_MSEL 0
493 #define LPC_SCB_SYSPLLCTRL_PSEL 5
494 #define LPC_SCB_SYSPLLCTRL_PSEL_1 0
495 #define LPC_SCB_SYSPLLCTRL_PSEL_2 1
496 #define LPC_SCB_SYSPLLCTRL_PSEL_4 2
497 #define LPC_SCB_SYSPLLCTRL_PSEL_8 3
498 #define LPC_SCB_SYSPLLCTRL_PSEL_MASK 3
500 #define LPC_SCB_SYSPLLSTAT_LOCK 0
502 #define LPC_SCB_USBPLLCTRL_MSEL 0
503 #define LPC_SCB_USBPLLCTRL_PSEL 5
504 #define LPC_SCB_USBPLLCTRL_PSEL_1 0
505 #define LPC_SCB_USBPLLCTRL_PSEL_2 1
506 #define LPC_SCB_USBPLLCTRL_PSEL_4 2
507 #define LPC_SCB_USBPLLCTRL_PSEL_8 3
508 #define LPC_SCB_USBPLLCTRL_PSEL_MASK 3
510 #define LPC_SCB_USBPLLSTAT_LOCK 0
512 #define LPC_SCB_SYSOSCCTRL_BYPASS 0
513 #define LPC_SCB_SYSOSCCTRL_FREQRANGE 1
514 #define LPC_SCB_SYSOSCCTRL_FREQRANGE_1_20 0
515 #define LPC_SCB_SYSOSCCTRL_FREQRANGE_15_25 1
517 #define LPC_SCB_WDTOSCCTRL_DIVSEL 0
518 #define LPC_SCB_WDTOSCCTRL_DIVSEL_MASK 0x1f
519 #define LPC_SCB_WDTOSCCTRL_FREQSEL 5
520 #define LPC_SCB_WDTOSCCTRL_FREQSEL_0_6 1
521 #define LPC_SCB_WDTOSCCTRL_FREQSEL_1_05 2
522 #define LPC_SCB_WDTOSCCTRL_FREQSEL_1_4 3
523 #define LPC_SCB_WDTOSCCTRL_FREQSEL_1_75 4
524 #define LPC_SCB_WDTOSCCTRL_FREQSEL_2_1 5
525 #define LPC_SCB_WDTOSCCTRL_FREQSEL_2_4 6
526 #define LPC_SCB_WDTOSCCTRL_FREQSEL_2_7 7
527 #define LPC_SCB_WDTOSCCTRL_FREQSEL_3_0 8
528 #define LPC_SCB_WDTOSCCTRL_FREQSEL_3_25 9
529 #define LPC_SCB_WDTOSCCTRL_FREQSEL_3_5 0x0a
530 #define LPC_SCB_WDTOSCCTRL_FREQSEL_3_75 0x0b
531 #define LPC_SCB_WDTOSCCTRL_FREQSEL_4_0 0x0c
532 #define LPC_SCB_WDTOSCCTRL_FREQSEL_4_2 0x0d
533 #define LPC_SCB_WDTOSCCTRL_FREQSEL_4_4 0x0e
534 #define LPC_SCB_WDTOSCCTRL_FREQSEL_4_6 0x0f
535 #define LPC_SCB_WDTOSCCTRL_FREQSEL_MASK 0x0f
537 #define LPC_SCB_SYSRSTSTAT_POR 0
538 #define LPC_SCB_SYSRSTSTAT_EXTRST 1
539 #define LPC_SCB_SYSRSTSTAT_WDT 2
540 #define LPC_SCB_SYSRSTSTAT_BOD 3
541 #define LPC_SCB_SYSRSTSTAT_SYSRST 4
543 #define LPC_SCB_SYSPLLCLKSEL_SEL 0
544 #define LPC_SCB_SYSPLLCLKSEL_SEL_IRC 0
545 #define LPC_SCB_SYSPLLCLKSEL_SEL_SYSOSC 1
546 #define LPC_SCB_SYSPLLCLKSEL_SEL_MASK 3
548 #define LPC_SCB_SYSPLLCLKUEN_ENA 0
550 #define LPC_SCB_USBPLLCLKSEL_SEL 0
551 #define LPC_SCB_USBPLLCLKSEL_SEL_IRC 0
552 #define LPC_SCB_USBPLLCLKSEL_SEL_SYSOSC 1
553 #define LPC_SCB_USBPLLCLKSEL_SEL_MASK 3
555 #define LPC_SCB_USBPLLCLKUEN_ENA 0
557 #define LPC_SCB_MAINCLKSEL_SEL 0
558 #define LPC_SCB_MAINCLKSEL_SEL_IRC 0
559 #define LPC_SCB_MAINCLKSEL_SEL_PLL_INPUT 1
560 #define LPC_SCB_MAINCLKSEL_SEL_WATCHDOG 2
561 #define LPC_SCB_MAINCLKSEL_SEL_PLL_OUTPUT 3
562 #define LPC_SCB_MAINCLKSEL_SEL_MASK 3
564 #define LPC_SCB_MAINCLKUEN_ENA 0
566 #define LPC_SCB_SYSAHBCLKDIV_DIV 0
568 #define LPC_SCB_SYSAHBCLKCTRL_SYS 0
569 #define LPC_SCB_SYSAHBCLKCTRL_ROM 1
570 #define LPC_SCB_SYSAHBCLKCTRL_RAM0 2
571 #define LPC_SCB_SYSAHBCLKCTRL_FLASHREG 3
572 #define LPC_SCB_SYSAHBCLKCTRL_FLASHARRAY 4
573 #define LPC_SCB_SYSAHBCLKCTRL_I2C 5
574 #define LPC_SCB_SYSAHBCLKCTRL_GPIO 6
575 #define LPC_SCB_SYSAHBCLKCTRL_CT16B0 7
576 #define LPC_SCB_SYSAHBCLKCTRL_CT16B1 8
577 #define LPC_SCB_SYSAHBCLKCTRL_CT32B0 9
578 #define LPC_SCB_SYSAHBCLKCTRL_CT32B1 10
579 #define LPC_SCB_SYSAHBCLKCTRL_SSP0 11
580 #define LPC_SCB_SYSAHBCLKCTRL_USART 12
581 #define LPC_SCB_SYSAHBCLKCTRL_ADC 13
582 #define LPC_SCB_SYSAHBCLKCTRL_USB 14
583 #define LPC_SCB_SYSAHBCLKCTRL_WWDT 15
584 #define LPC_SCB_SYSAHBCLKCTRL_IOCON 16
585 #define LPC_SCB_SYSAHBCLKCTRL_SSP1 18
586 #define LPC_SCB_SYSAHBCLKCTRL_PINT 19
587 #define LPC_SCB_SYSAHBCLKCTRL_GROUP0INT 23
588 #define LPC_SCB_SYSAHBCLKCTRL_GROUP1INT 24
589 #define LPC_SCB_SYSAHBCLKCTRL_RAM1 26
590 #define LPC_SCB_SYSAHBCLKCTRL_USBRAM 27
592 #define LPC_SCB_SSP0CLKDIV_
593 #define LPC_SCB_UARTCLKDIV_
594 #define LPC_SCB_SSP1CLKDIV_
596 #define LPC_SCB_USBCLKSEL_SEL 0
597 #define LPC_SCB_USBCLKSEL_SEL_USB_PLL 0
598 #define LPC_SCB_USBCLKSEL_SEL_MAIN_CLOCK 1
600 #define LPC_SCB_USBCLKUEN_ENA 0
601 #define LPC_SCB_USBCLKDIV_DIV 0
603 #define LPC_SCB_CLKOUTSEL_
604 #define LPC_SCB_CLKOUTUEN_
606 #define LPC_SCB_PDRUNCFG_IRCOUT_PD 0
607 #define LPC_SCB_PDRUNCFG_IRC_PD 1
608 #define LPC_SCB_PDRUNCFG_FLASH_PD 2
609 #define LPC_SCB_PDRUNCFG_BOD_PD 3
610 #define LPC_SCB_PDRUNCFG_ADC_PD 4
611 #define LPC_SCB_PDRUNCFG_SYSOSC_PD 5
612 #define LPC_SCB_PDRUNCFG_WDTOSC_PD 6
613 #define LPC_SCB_PDRUNCFG_SYSPLL_PD 7
614 #define LPC_SCB_PDRUNCFG_USBPLL_PD 8
615 #define LPC_SCB_PDRUNCFG_USBPAD_PD 10
618 uint32_t r0[4]; /* 0x0 */
620 vuint32_t flashcfg; /* 0x10 */
623 extern struct lpc_flash lpc_flash;
625 struct lpc_gpio_pin {
628 extern struct lpc_gpio_pin lpc_gpio_pin;
630 struct lpc_gpio_group0 {
633 extern struct lpc_gpio_group0 lpc_gpio_group0;
635 struct lpc_gpio_group1 {
638 extern struct lpc_gpio_group1 lpc_gpio_group1;
641 vuint8_t byte[0x40]; /* 0x0000 */
643 uint8_t r0030[0x1000 - 0x40];
645 vuint32_t word[0x40]; /* 0x1000 */
647 uint8_t r1100[0x2000 - 0x1100];
649 vuint32_t dir[2]; /* 0x2000 */
651 uint8_t r2008[0x2080 - 0x2008];
653 vuint32_t mask[2]; /* 0x2080 */
655 uint8_t r2088[0x2100 - 0x2088];
657 vuint32_t pin[2]; /* 0x2100 */
659 uint8_t r2108[0x2200 - 0x2108];
661 vuint32_t set[2]; /* 0x2200 */
663 uint8_t r2208[0x2280 - 0x2208];
665 vuint32_t clr[2]; /* 0x2280 */
667 uint8_t r2288[0x2300 - 0x2288];
669 vuint32_t not[2]; /* 0x2300 */
672 extern struct lpc_gpio lpc_gpio;
675 uint8_t r0000[0x10]; /* 0x0000 */
677 vuint32_t csr; /* 0x0010 */
683 extern struct lpc_systick lpc_systick;
685 #define LPC_SYSTICK_CSR_ENABLE 0
686 #define LPC_SYSTICK_CSR_TICKINT 1
687 #define LPC_SYSTICK_CSR_CLKSOURCE 2
688 #define LPC_SYSTICK_CSR_CLKSOURCE_CPU_OVER_2 0
689 #define LPC_SYSTICK_CSR_CLKSOURCE_CPU 1
690 #define LPC_SYSTICK_CSR_COUNTFLAG 16
693 vuint32_t rbr_thr; /* 0x0000 */
698 vuint32_t mcr; /* 0x0010 */
703 vuint32_t acr; /* 0x0020 */
708 vuint32_t ter; /* 0x0030 */
711 vuint32_t hden; /* 0x0040 */
716 vuint32_t rs485addrmatch; /* 0x0050 */
721 extern struct lpc_usart lpc_usart;
723 #define LPC_USART_IER_RBRINTEN 0
724 #define LPC_USART_IER_THREINTEN 1
725 #define LPC_USART_IER_RSLINTEN 2
726 #define LPC_USART_IER_MSINTEN 3
727 #define LPC_USART_IER_ABEOINTEN 8
728 #define LPC_USART_IER_ABTOINTEN 9
730 #define LPC_USART_IIR_INTSTATUS 0
731 #define LPC_USART_IIR_INTID 1
732 #define LPC_USART_IIR_INTID_RLS 3
733 #define LPC_USART_IIR_INTID_RDA 2
734 #define LPC_USART_IIR_INTID_CTI 6
735 #define LPC_USART_IIR_INTID_THRE 1
736 #define LPC_USART_IIR_INTID_MS 0
737 #define LPC_USART_IIR_INTID_MASK 7
738 #define LPC_USART_IIR_FIFOEN 6
739 #define LPC_USART_IIR_ABEOINT 8
740 #define LPC_USART_IIR_ABTOINT 9
742 #define LPC_USART_FCR_FIFOEN 0
743 #define LPC_USART_FCR_RXFIFORES 1
744 #define LPC_USART_FCR_TXFIFORES 2
745 #define LPC_USART_FCR_RXTL 6
746 #define LPC_USART_FCR_RXTL_1 0
747 #define LPC_USART_FCR_RXTL_4 1
748 #define LPC_USART_FCR_RXTL_8 2
749 #define LPC_USART_FCR_RXTL_14 3
751 #define LPC_USART_LCR_WLS 0
752 #define LPC_USART_LCR_WLS_5 0
753 #define LPC_USART_LCR_WLS_6 1
754 #define LPC_USART_LCR_WLS_7 2
755 #define LPC_USART_LCR_WLS_8 3
756 #define LPC_USART_LCR_WLS_MASK 3
757 #define LPC_USART_LCR_SBS 2
758 #define LPC_USART_LCR_SBS_1 0
759 #define LPC_USART_LCR_SBS_2 1
760 #define LPC_USART_LCR_SBS_MASK 1
761 #define LPC_USART_LCR_PE 3
762 #define LPC_USART_LCR_PS 4
763 #define LPC_USART_LCR_PS_ODD 0
764 #define LPC_USART_LCR_PS_EVEN 1
765 #define LPC_USART_LCR_PS_ONE 2
766 #define LPC_USART_LCR_PS_ZERO 3
767 #define LPC_USART_LCR_PS_MASK 3
768 #define LPC_USART_LCR_BC 6
769 #define LPC_USART_LCR_DLAB 7
771 #define LPC_USART_MCR_DTRCTRL 0
772 #define LPC_USART_MCR_RTSCTRL 1
773 #define LPC_USART_MCR_LMS 4
774 #define LPC_USART_MCR_RTSEN 6
775 #define LPC_USART_MCR_CTSEN 7
777 #define LPC_USART_LSR_RDR 0
778 #define LPC_USART_LSR_OE 1
779 #define LPC_USART_LSR_PE 2
780 #define LPC_USART_LSR_FE 3
781 #define LPC_USART_LSR_BI 4
782 #define LPC_USART_LSR_THRE 5
783 #define LPC_USART_LSR_TEMT 6
784 #define LPC_USART_LSR_RXFE 7
785 #define LPC_USART_LSR_TXERR 8
787 #define LPC_USART_MSR_DCTS 0
788 #define LPC_USART_MSR_DDSR 1
789 #define LPC_USART_MSR_TERI 2
790 #define LPC_USART_MSR_DDCD 3
791 #define LPC_USART_MSR_CTS 4
792 #define LPC_USART_MSR_DSR 5
793 #define LPC_USART_MSR_RI 6
794 #define LPC_USART_MSR_DCD 7
796 #define LPC_USART_ACR_START 0
797 #define LPC_USART_ACR_MODE 1
798 #define LPC_USART_ACR_AUTORESTART 2
799 #define LPC_USART_ACR_ABEOINTCLR 8
800 #define LPC_USART_ACR_ABTOINTCLR 9
802 #define LPC_USART_FDR_DIVADDVAL 0
803 #define LPC_USART_FDR_MULVAL 4
805 #define LPC_USART_OSR_OSFRAC 1
806 #define LPC_USART_OSR_OSINT 4
807 #define LPC_USART_OSR_FDINT 8
809 #define LPC_USART_TER_TXEN 7
811 #define LPC_USART_HDEN_HDEN 0
813 #define LPC_ISR_PIN_INT0_POS 0
814 #define LPC_ISR_PIN_INT1_POS 1
815 #define LPC_ISR_PIN_INT2_POS 2
816 #define LPC_ISR_PIN_INT3_POS 3
817 #define LPC_ISR_PIN_INT4_POS 4
818 #define LPC_ISR_PIN_INT5_POS 5
819 #define LPC_ISR_PIN_INT6_POS 6
820 #define LPC_ISR_PIN_INT7_POS 7
821 #define LPC_ISR_GINT0_POS 8
822 #define LPC_ISR_GINT1_POS 9
823 #define LPC_ISR_SSP1_POS 14
824 #define LPC_ISR_I2C_POS 15
825 #define LPC_ISR_CT16B0_POS 16
826 #define LPC_ISR_CT16B1_POS 17
827 #define LPC_ISR_CT32B0_POS 18
828 #define LPC_ISR_CT32B1_POS 19
829 #define LPC_ISR_SSP0_POS 20
830 #define LPC_ISR_USART_POS 21
831 #define LPC_ISR_USB_IRQ_POS 22
832 #define LPC_ISR_USB_FIQ_POS 23
833 #define LPC_ISR_ADC_POS 24
834 #define LPC_ISR_WWDT_POS 25
835 #define LPC_ISR_BOD_POS 26
836 #define LPC_ISR_FLASH_POS 27
837 #define LPC_ISR_USB_WAKEUP_POS 30
840 vuint32_t iser; /* 0x000 0xe000e100 Set Enable Register */
842 uint8_t _unused020[0x080 - 0x004];
844 vuint32_t icer; /* 0x080 0xe000e180 Clear Enable Register */
846 uint8_t _unused0a0[0x100 - 0x084];
848 vuint32_t ispr; /* 0x100 0xe000e200 Set Pending Register */
850 uint8_t _unused120[0x180 - 0x104];
852 vuint32_t icpr; /* 0x180 0xe000e280 Clear Pending Register */
854 uint8_t _unused1a0[0x300 - 0x184];
856 vuint32_t ipr[8]; /* 0x300 0xe000e400 Priority Register */
859 extern struct lpc_nvic lpc_nvic;
862 lpc_nvic_set_enable(int irq) {
863 lpc_nvic.iser |= (1 << irq);
867 lpc_nvic_clear_enable(int irq) {
868 lpc_nvic.icer |= (1 << irq);
872 lpc_nvic_enabled(int irq) {
873 return (lpc_nvic.iser >> irq) & 1;
878 lpc_nvic_set_pending(int irq) {
879 lpc_nvic.ispr = (1 << irq);
883 lpc_nvic_clear_pending(int irq) {
884 lpc_nvic.icpr = (1 << irq);
888 lpc_nvic_pending(int irq) {
889 return (lpc_nvic.ispr >> irq) & 1;
892 #define IRQ_PRIO_REG(irq) ((irq) >> 2)
893 #define IRQ_PRIO_BIT(irq) (((irq) & 3) << 3)
894 #define IRQ_PRIO_MASK(irq) (0xff << IRQ_PRIO_BIT(irq))
897 lpc_nvic_set_priority(int irq, uint8_t prio) {
898 int n = IRQ_PRIO_REG(irq);
902 v &= ~IRQ_PRIO_MASK(irq);
903 v |= (prio) << IRQ_PRIO_BIT(irq);
907 static inline uint8_t
908 lpc_nvic_get_priority(int irq) {
909 return (lpc_nvic.ipr[IRQ_PRIO_REG(irq)] >> IRQ_PRIO_BIT(irq)) & IRQ_PRIO_MASK(0);