2 * Copyright © 2013 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
22 #define AO_SYSTICK (AO_LPC_SYSCLK / 2)
24 volatile AO_TICK_TYPE ao_tick_count;
35 AO_TICK_TYPE before, after;
39 before = ao_tick_count;
40 cvr = lpc_systick.cvr;
41 after = ao_tick_count;
42 } while (before != after);
44 return (uint64_t) after * (1000000000ULL / AO_HERTZ) +
45 (uint64_t) cvr * (1000000000ULL / AO_SYSTICK);
49 volatile uint8_t ao_data_interval = 1;
50 volatile uint8_t ao_data_count;
53 void lpc_systick_isr(void)
55 if (lpc_systick.csr & (1 << LPC_SYSTICK_CSR_COUNTFLAG)) {
57 ao_task_check_alarm();
59 if (++ao_data_count == ao_data_interval) {
62 #if (AO_DATA_ALL & ~(AO_DATA_ADC))
63 ao_wakeup((void *) &ao_data_count);
72 ao_timer_set_adc_interval(uint8_t interval)
75 ao_data_interval = interval;
81 #define SYSTICK_RELOAD ((AO_LPC_SYSCLK / 2) / 100 - 1)
83 /* Initialize our 100Hz clock */
87 lpc_systick.rvr = SYSTICK_RELOAD;
89 lpc_systick.csr = ((1 << LPC_SYSTICK_CSR_ENABLE) |
90 (1 << LPC_SYSTICK_CSR_TICKINT) |
91 (LPC_SYSTICK_CSR_CLKSOURCE_CPU_OVER_2 << LPC_SYSTICK_CSR_CLKSOURCE));
94 #define AO_LPC_M ((AO_LPC_CLKOUT / AO_LPC_CLKIN) - 1)
96 #define AO_LPC_FCCO_MIN 156000000
102 for (i = 0; i < 200; i++)
112 /* Turn off all perhipherals except for GPIO configuration */
113 lpc_scb.sysahbclkctrl = ((1 << LPC_SCB_SYSAHBCLKCTRL_SYS) |
114 (1 << LPC_SCB_SYSAHBCLKCTRL_ROM) |
115 (1 << LPC_SCB_SYSAHBCLKCTRL_RAM0) |
116 (1 << LPC_SCB_SYSAHBCLKCTRL_FLASHARRAY) |
117 (1 << LPC_SCB_SYSAHBCLKCTRL_GPIO) |
118 (1 << LPC_SCB_SYSAHBCLKCTRL_IOCON));
120 /* Enable the brown-out detection at the highest voltage to
121 * make sure the flash part remains happy
124 lpc_scb.pdruncfg &= ~(1 << LPC_SCB_PDRUNCFG_BOD_PD);
125 lpc_scb.bodctrl = ((LPC_SCB_BOD_BODRSTLEV_2_63 << LPC_SCB_BOD_BODRSTLEV) |
126 (LPC_SCB_BOD_BODINTVAL_RESERVED << LPC_SCB_BOD_BODINTVAL) |
127 (1 << LPC_SCB_BOD_BODRSTENA));
129 /* Turn the IRC clock back on */
130 lpc_scb.pdruncfg &= ~(1 << LPC_SCB_PDRUNCFG_IRC_PD);
133 /* Switch to the IRC clock */
134 lpc_scb.mainclksel = LPC_SCB_MAINCLKSEL_SEL_IRC << LPC_SCB_MAINCLKSEL_SEL;
135 lpc_scb.mainclkuen = (0 << LPC_SCB_MAINCLKUEN_ENA);
136 lpc_scb.mainclkuen = (1 << LPC_SCB_MAINCLKUEN_ENA);
137 while (!(lpc_scb.mainclkuen & (1 << LPC_SCB_MAINCLKUEN_ENA)))
140 /* Switch USB to the main clock */
141 lpc_scb.usbclksel = (LPC_SCB_USBCLKSEL_SEL_MAIN_CLOCK << LPC_SCB_USBCLKSEL_SEL);
142 lpc_scb.usbclkuen = (0 << LPC_SCB_USBCLKUEN_ENA);
143 lpc_scb.usbclkuen = (1 << LPC_SCB_USBCLKUEN_ENA);
144 while (!(lpc_scb.usbclkuen & (1 << LPC_SCB_USBCLKUEN_ENA)))
147 /* Find a PLL post divider ratio that gets the FCCO in range */
148 for (p = 0; p < 4; p++)
149 if (AO_LPC_CLKOUT << (1 + p) >= AO_LPC_FCCO_MIN)
153 ao_panic(AO_PANIC_CRASH);
155 /* Power down the PLL before touching the registers */
156 lpc_scb.pdruncfg |= (1 << LPC_SCB_PDRUNCFG_SYSPLL_PD);
159 /* Set PLL divider values */
160 lpc_scb.syspllctrl = ((AO_LPC_M << LPC_SCB_SYSPLLCTRL_MSEL) |
161 (p << LPC_SCB_SYSPLLCTRL_PSEL));
163 /* Turn off the external crystal clock */
164 lpc_scb.pdruncfg |= (1 << LPC_SCB_PDRUNCFG_SYSOSC_PD);
167 /* Configure the crystal clock */
168 lpc_scb.sysoscctrl = ((0 << LPC_SCB_SYSOSCCTRL_BYPASS) | /* using a crystal */
169 ((AO_LPC_CLKIN > 15000000) << LPC_SCB_SYSOSCCTRL_FREQRANGE));/* set range */
171 /* Turn on the external crystal clock */
172 lpc_scb.pdruncfg &= ~(1 << LPC_SCB_PDRUNCFG_SYSOSC_PD);
175 /* Select crystal as PLL input */
177 lpc_scb.syspllclksel = (LPC_SCB_SYSPLLCLKSEL_SEL_SYSOSC << LPC_SCB_SYSPLLCLKSEL_SEL);
178 lpc_scb.syspllclkuen = (1 << LPC_SCB_SYSPLLCLKUEN_ENA);
179 lpc_scb.syspllclkuen = (0 << LPC_SCB_SYSPLLCLKUEN_ENA);
180 lpc_scb.syspllclkuen = (1 << LPC_SCB_SYSPLLCLKUEN_ENA);
181 while (!(lpc_scb.syspllclkuen & (1 << LPC_SCB_SYSPLLCLKUEN_ENA)))
184 /* Turn on the PLL */
185 lpc_scb.pdruncfg &= ~(1 << LPC_SCB_PDRUNCFG_SYSPLL_PD);
187 /* Wait for it to lock */
189 for (i = 0; i < 20000; i++)
190 if (lpc_scb.syspllstat & (1 << LPC_SCB_SYSPLLSTAT_LOCK))
193 ao_panic(AO_PANIC_CRASH);
195 /* Switch to the PLL */
196 lpc_scb.mainclksel = LPC_SCB_MAINCLKSEL_SEL_PLL_OUTPUT << LPC_SCB_MAINCLKSEL_SEL;
197 lpc_scb.mainclkuen = (1 << LPC_SCB_MAINCLKUEN_ENA);
198 lpc_scb.mainclkuen = (0 << LPC_SCB_MAINCLKUEN_ENA);
199 lpc_scb.mainclkuen = (1 << LPC_SCB_MAINCLKUEN_ENA);
200 while (!(lpc_scb.mainclkuen & (1 << LPC_SCB_MAINCLKUEN_ENA)))
203 /* Set system clock divider */
204 lpc_scb.sysahbclkdiv = AO_LPC_CLKOUT / AO_LPC_SYSCLK;
206 /* Shut down perhipheral clocks (enabled as needed) */
207 lpc_scb.ssp0clkdiv = 0;
208 lpc_scb.uartclkdiv = 0;
209 lpc_scb.ssp1clkdiv = 0;
210 lpc_scb.usbclkdiv = 0;
211 lpc_scb.clkoutdiv = 0;
213 /* Switch USB PLL source to system osc so we can power down the IRC */
214 lpc_scb.usbpllclksel = (LPC_SCB_USBPLLCLKSEL_SEL_SYSOSC << LPC_SCB_USBPLLCLKSEL_SEL);
215 lpc_scb.usbpllclkuen = (0 << LPC_SCB_USBPLLCLKUEN_ENA);
216 lpc_scb.usbpllclkuen = (1 << LPC_SCB_USBPLLCLKUEN_ENA);
217 while (!(lpc_scb.usbpllclkuen & (1 << LPC_SCB_USBPLLCLKUEN_ENA)))
220 /* Power down everything we don't need */
221 lpc_scb.pdruncfg = ((1 << LPC_SCB_PDRUNCFG_IRCOUT_PD) |
222 (1 << LPC_SCB_PDRUNCFG_IRC_PD) |
223 (0 << LPC_SCB_PDRUNCFG_BOD_PD) |
224 (1 << LPC_SCB_PDRUNCFG_ADC_PD) |
225 (1 << LPC_SCB_PDRUNCFG_WDTOSC_PD) |
226 (1 << LPC_SCB_PDRUNCFG_USBPLL_PD) |
227 (1 << LPC_SCB_PDRUNCFG_USBPAD_PD) |