2 * Copyright © 2013 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
20 volatile __data AO_TICK_TYPE ao_tick_count;
29 volatile __data uint8_t ao_data_interval = 1;
30 volatile __data uint8_t ao_data_count;
33 void lpc_systick_isr(void)
35 if (lpc_systick.csr & (1 << LPC_SYSTICK_CSR_COUNTFLAG)) {
38 if (ao_task_alarm_tick && (int16_t) (ao_tick_count - ao_task_alarm_tick) >= 0)
39 ao_task_check_alarm((uint16_t) ao_tick_count);
42 if (++ao_data_count == ao_data_interval) {
45 #if (AO_DATA_ALL & ~(AO_DATA_ADC))
46 ao_wakeup((void *) &ao_data_count);
55 ao_timer_set_adc_interval(uint8_t interval)
58 ao_data_interval = interval;
64 #define SYSTICK_RELOAD ((AO_LPC_SYSCLK / 2) / 100 - 1)
66 /* Initialize our 100Hz clock */
70 lpc_systick.rvr = SYSTICK_RELOAD;
72 lpc_systick.csr = ((1 << LPC_SYSTICK_CSR_ENABLE) |
73 (1 << LPC_SYSTICK_CSR_TICKINT) |
74 (LPC_SYSTICK_CSR_CLKSOURCE_CPU_OVER_2 << LPC_SYSTICK_CSR_CLKSOURCE));
77 #define AO_LPC_M ((AO_LPC_CLKOUT / AO_LPC_CLKIN) - 1)
79 #define AO_LPC_FCCO_MIN 156000000
85 for (i = 0; i < 200; i++)
95 /* Turn off all perhipherals except for GPIO configuration */
96 lpc_scb.sysahbclkctrl = ((1 << LPC_SCB_SYSAHBCLKCTRL_SYS) |
97 (1 << LPC_SCB_SYSAHBCLKCTRL_ROM) |
98 (1 << LPC_SCB_SYSAHBCLKCTRL_RAM0) |
99 (1 << LPC_SCB_SYSAHBCLKCTRL_FLASHARRAY) |
100 (1 << LPC_SCB_SYSAHBCLKCTRL_GPIO) |
101 (1 << LPC_SCB_SYSAHBCLKCTRL_IOCON));
103 /* Turn the IRC clock back on */
104 lpc_scb.pdruncfg &= ~(1 << LPC_SCB_PDRUNCFG_IRC_PD);
107 /* Switch to the IRC clock */
108 lpc_scb.mainclksel = LPC_SCB_MAINCLKSEL_SEL_IRC << LPC_SCB_MAINCLKSEL_SEL;
109 lpc_scb.mainclkuen = (1 << LPC_SCB_MAINCLKUEN_ENA);
110 lpc_scb.mainclkuen = (0 << LPC_SCB_MAINCLKUEN_ENA);
111 lpc_scb.mainclkuen = (1 << LPC_SCB_MAINCLKUEN_ENA);
112 while (!(lpc_scb.mainclkuen & (1 << LPC_SCB_MAINCLKUEN_ENA)))
115 /* Find a PLL post divider ratio that gets the FCCO in range */
116 for (p = 0; p < 4; p++)
117 if (AO_LPC_CLKOUT << (1 + p) >= AO_LPC_FCCO_MIN)
121 ao_panic(AO_PANIC_CRASH);
123 /* Power down the PLL before touching the registers */
124 lpc_scb.pdruncfg |= (1 << LPC_SCB_PDRUNCFG_SYSPLL_PD);
127 /* Set PLL divider values */
128 lpc_scb.syspllctrl = ((AO_LPC_M << LPC_SCB_SYSPLLCTRL_MSEL) |
129 (p << LPC_SCB_SYSPLLCTRL_PSEL));
131 /* Turn off the external crystal clock */
132 lpc_scb.pdruncfg |= (1 << LPC_SCB_PDRUNCFG_SYSOSC_PD);
135 /* Configure the crystal clock */
136 lpc_scb.sysoscctrl = ((0 << LPC_SCB_SYSOSCCTRL_BYPASS) | /* using a crystal */
137 ((AO_LPC_CLKIN > 15000000) << LPC_SCB_SYSOSCCTRL_FREQRANGE));/* set range */
139 /* Turn on the external crystal clock */
140 lpc_scb.pdruncfg &= ~(1 << LPC_SCB_PDRUNCFG_SYSOSC_PD);
143 /* Select crystal as PLL input */
145 lpc_scb.syspllclksel = (LPC_SCB_SYSPLLCLKSEL_SEL_SYSOSC << LPC_SCB_SYSPLLCLKSEL_SEL);
146 lpc_scb.syspllclkuen = (1 << LPC_SCB_SYSPLLCLKUEN_ENA);
147 lpc_scb.syspllclkuen = (0 << LPC_SCB_SYSPLLCLKUEN_ENA);
148 lpc_scb.syspllclkuen = (1 << LPC_SCB_SYSPLLCLKUEN_ENA);
149 while (!(lpc_scb.syspllclkuen & (1 << LPC_SCB_SYSPLLCLKUEN_ENA)))
152 /* Turn on the PLL */
153 lpc_scb.pdruncfg &= ~(1 << LPC_SCB_PDRUNCFG_SYSPLL_PD);
155 /* Wait for it to lock */
157 for (i = 0; i < 20000; i++)
158 if (lpc_scb.syspllstat & (1 << LPC_SCB_SYSPLLSTAT_LOCK))
161 ao_panic(AO_PANIC_CRASH);
163 /* Switch to the PLL */
164 lpc_scb.mainclksel = LPC_SCB_MAINCLKSEL_SEL_PLL_OUTPUT << LPC_SCB_MAINCLKSEL_SEL;
165 lpc_scb.mainclkuen = (1 << LPC_SCB_MAINCLKUEN_ENA);
166 lpc_scb.mainclkuen = (0 << LPC_SCB_MAINCLKUEN_ENA);
167 lpc_scb.mainclkuen = (1 << LPC_SCB_MAINCLKUEN_ENA);
168 while (!(lpc_scb.mainclkuen & (1 << LPC_SCB_MAINCLKUEN_ENA)))
171 /* Set system clock divider */
172 lpc_scb.sysahbclkdiv = AO_LPC_CLKOUT / AO_LPC_SYSCLK;
174 /* Shut down perhipheral clocks (enabled as needed) */
175 lpc_scb.ssp0clkdiv = 0;
176 lpc_scb.uartclkdiv = 0;
177 lpc_scb.ssp1clkdiv = 0;
178 lpc_scb.usbclkdiv = 0;
179 lpc_scb.clkoutdiv = 0;