2 * Copyright © 2013 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
21 volatile __data AO_TICK_TYPE ao_tick_count;
30 volatile __data uint8_t ao_data_interval = 1;
31 volatile __data uint8_t ao_data_count;
34 void lpc_systick_isr(void)
36 if (lpc_systick.csr & (1 << LPC_SYSTICK_CSR_COUNTFLAG)) {
39 if (ao_task_alarm_tick && (int16_t) (ao_tick_count - ao_task_alarm_tick) >= 0)
40 ao_task_check_alarm((uint16_t) ao_tick_count);
43 if (++ao_data_count == ao_data_interval) {
46 #if (AO_DATA_ALL & ~(AO_DATA_ADC))
47 ao_wakeup((void *) &ao_data_count);
56 ao_timer_set_adc_interval(uint8_t interval)
59 ao_data_interval = interval;
65 #define SYSTICK_RELOAD ((AO_LPC_SYSCLK / 2) / 100 - 1)
67 /* Initialize our 100Hz clock */
71 lpc_systick.rvr = SYSTICK_RELOAD;
73 lpc_systick.csr = ((1 << LPC_SYSTICK_CSR_ENABLE) |
74 (1 << LPC_SYSTICK_CSR_TICKINT) |
75 (LPC_SYSTICK_CSR_CLKSOURCE_CPU_OVER_2 << LPC_SYSTICK_CSR_CLKSOURCE));
78 #define AO_LPC_M ((AO_LPC_CLKOUT / AO_LPC_CLKIN) - 1)
80 #define AO_LPC_FCCO_MIN 156000000
86 for (i = 0; i < 200; i++)
96 /* Turn off all perhipherals except for GPIO configuration */
97 lpc_scb.sysahbclkctrl = ((1 << LPC_SCB_SYSAHBCLKCTRL_SYS) |
98 (1 << LPC_SCB_SYSAHBCLKCTRL_ROM) |
99 (1 << LPC_SCB_SYSAHBCLKCTRL_RAM0) |
100 (1 << LPC_SCB_SYSAHBCLKCTRL_FLASHARRAY) |
101 (1 << LPC_SCB_SYSAHBCLKCTRL_GPIO) |
102 (1 << LPC_SCB_SYSAHBCLKCTRL_IOCON));
104 /* Enable the brown-out detection at the highest voltage to
105 * make sure the flash part remains happy
108 lpc_scb.pdruncfg &= ~(1 << LPC_SCB_PDRUNCFG_BOD_PD);
109 lpc_scb.bodctrl = ((LPC_SCB_BOD_BODRSTLEV_2_63 << LPC_SCB_BOD_BODRSTLEV) |
110 (LPC_SCB_BOD_BODINTVAL_RESERVED << LPC_SCB_BOD_BODINTVAL) |
111 (1 << LPC_SCB_BOD_BODRSTENA));
113 /* Turn the IRC clock back on */
114 lpc_scb.pdruncfg &= ~(1 << LPC_SCB_PDRUNCFG_IRC_PD);
117 /* Switch to the IRC clock */
118 lpc_scb.mainclksel = LPC_SCB_MAINCLKSEL_SEL_IRC << LPC_SCB_MAINCLKSEL_SEL;
119 lpc_scb.mainclkuen = (0 << LPC_SCB_MAINCLKUEN_ENA);
120 lpc_scb.mainclkuen = (1 << LPC_SCB_MAINCLKUEN_ENA);
121 while (!(lpc_scb.mainclkuen & (1 << LPC_SCB_MAINCLKUEN_ENA)))
124 /* Switch USB to the main clock */
125 lpc_scb.usbclksel = (LPC_SCB_USBCLKSEL_SEL_MAIN_CLOCK << LPC_SCB_USBCLKSEL_SEL);
126 lpc_scb.usbclkuen = (0 << LPC_SCB_USBCLKUEN_ENA);
127 lpc_scb.usbclkuen = (1 << LPC_SCB_USBCLKUEN_ENA);
128 while (!(lpc_scb.usbclkuen & (1 << LPC_SCB_USBCLKUEN_ENA)))
131 /* Find a PLL post divider ratio that gets the FCCO in range */
132 for (p = 0; p < 4; p++)
133 if (AO_LPC_CLKOUT << (1 + p) >= AO_LPC_FCCO_MIN)
137 ao_panic(AO_PANIC_CRASH);
139 /* Power down the PLL before touching the registers */
140 lpc_scb.pdruncfg |= (1 << LPC_SCB_PDRUNCFG_SYSPLL_PD);
143 /* Set PLL divider values */
144 lpc_scb.syspllctrl = ((AO_LPC_M << LPC_SCB_SYSPLLCTRL_MSEL) |
145 (p << LPC_SCB_SYSPLLCTRL_PSEL));
147 /* Turn off the external crystal clock */
148 lpc_scb.pdruncfg |= (1 << LPC_SCB_PDRUNCFG_SYSOSC_PD);
151 /* Configure the crystal clock */
152 lpc_scb.sysoscctrl = ((0 << LPC_SCB_SYSOSCCTRL_BYPASS) | /* using a crystal */
153 ((AO_LPC_CLKIN > 15000000) << LPC_SCB_SYSOSCCTRL_FREQRANGE));/* set range */
155 /* Turn on the external crystal clock */
156 lpc_scb.pdruncfg &= ~(1 << LPC_SCB_PDRUNCFG_SYSOSC_PD);
159 /* Select crystal as PLL input */
161 lpc_scb.syspllclksel = (LPC_SCB_SYSPLLCLKSEL_SEL_SYSOSC << LPC_SCB_SYSPLLCLKSEL_SEL);
162 lpc_scb.syspllclkuen = (1 << LPC_SCB_SYSPLLCLKUEN_ENA);
163 lpc_scb.syspllclkuen = (0 << LPC_SCB_SYSPLLCLKUEN_ENA);
164 lpc_scb.syspllclkuen = (1 << LPC_SCB_SYSPLLCLKUEN_ENA);
165 while (!(lpc_scb.syspllclkuen & (1 << LPC_SCB_SYSPLLCLKUEN_ENA)))
168 /* Turn on the PLL */
169 lpc_scb.pdruncfg &= ~(1 << LPC_SCB_PDRUNCFG_SYSPLL_PD);
171 /* Wait for it to lock */
173 for (i = 0; i < 20000; i++)
174 if (lpc_scb.syspllstat & (1 << LPC_SCB_SYSPLLSTAT_LOCK))
177 ao_panic(AO_PANIC_CRASH);
179 /* Switch to the PLL */
180 lpc_scb.mainclksel = LPC_SCB_MAINCLKSEL_SEL_PLL_OUTPUT << LPC_SCB_MAINCLKSEL_SEL;
181 lpc_scb.mainclkuen = (1 << LPC_SCB_MAINCLKUEN_ENA);
182 lpc_scb.mainclkuen = (0 << LPC_SCB_MAINCLKUEN_ENA);
183 lpc_scb.mainclkuen = (1 << LPC_SCB_MAINCLKUEN_ENA);
184 while (!(lpc_scb.mainclkuen & (1 << LPC_SCB_MAINCLKUEN_ENA)))
187 /* Set system clock divider */
188 lpc_scb.sysahbclkdiv = AO_LPC_CLKOUT / AO_LPC_SYSCLK;
190 /* Shut down perhipheral clocks (enabled as needed) */
191 lpc_scb.ssp0clkdiv = 0;
192 lpc_scb.uartclkdiv = 0;
193 lpc_scb.ssp1clkdiv = 0;
194 lpc_scb.usbclkdiv = 0;
195 lpc_scb.clkoutdiv = 0;
197 /* Switch USB PLL source to system osc so we can power down the IRC */
198 lpc_scb.usbpllclksel = (LPC_SCB_USBPLLCLKSEL_SEL_SYSOSC << LPC_SCB_USBPLLCLKSEL_SEL);
199 lpc_scb.usbpllclkuen = (0 << LPC_SCB_USBPLLCLKUEN_ENA);
200 lpc_scb.usbpllclkuen = (1 << LPC_SCB_USBPLLCLKUEN_ENA);
201 while (!(lpc_scb.usbpllclkuen & (1 << LPC_SCB_USBPLLCLKUEN_ENA)))
204 /* Power down everything we don't need */
205 lpc_scb.pdruncfg = ((1 << LPC_SCB_PDRUNCFG_IRCOUT_PD) |
206 (1 << LPC_SCB_PDRUNCFG_IRC_PD) |
207 (0 << LPC_SCB_PDRUNCFG_BOD_PD) |
208 (1 << LPC_SCB_PDRUNCFG_ADC_PD) |
209 (1 << LPC_SCB_PDRUNCFG_WDTOSC_PD) |
210 (1 << LPC_SCB_PDRUNCFG_USBPLL_PD) |
211 (1 << LPC_SCB_PDRUNCFG_USBPAD_PD) |