2 * Copyright © 2013 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
21 #ifndef AO_LPC_CT_BEEP
22 /* XXX need to adjust this for configurable beeper */
23 #define AO_LPC_CT_BEEP lpc_ct32b1
24 #define AO_LPC_CT_BEEP_CLKCTRL LPC_SCB_SYSAHBCLKCTRL_CT32B1
25 #define AO_LPC_CT_BEEP_EMR LPC_CT32B_EMR_EMC1
32 AO_LPC_CT_BEEP.tcr = ((0 << LPC_CT32B_TCR_CEN) |
33 (1 << LPC_CT32B_TCR_CRST));
34 lpc_scb.sysahbclkctrl &= ~(1UL << AO_LPC_CT_BEEP_CLKCTRL);
36 lpc_scb.sysahbclkctrl |= (1UL << AO_LPC_CT_BEEP_CLKCTRL);
38 /* Set prescaler to match cc1111 clocks
40 AO_LPC_CT_BEEP.pr = AO_LPC_SYSCLK / 750000 - 1;
42 /* Write the desired data in the match registers */
44 /* Reset after two time units */
45 AO_LPC_CT_BEEP.mr[0] = beep << 1;
47 /* PWM width is half of that */
48 AO_LPC_CT_BEEP.mr[1] = beep;
50 /* Flip output 1 on PWM match */
51 AO_LPC_CT_BEEP.emr = (LPC_CT32B_EMR_EMC_TOGGLE << AO_LPC_CT_BEEP_EMR);
53 /* Reset on match 0 */
54 AO_LPC_CT_BEEP.mcr = (1 << LPC_CT32B_MCR_MR0R);
57 AO_LPC_CT_BEEP.pwmc = (1 << LPC_CT32B_PWMC_PWMEN1);
60 AO_LPC_CT_BEEP.ctcr = 0;
62 /* And turn the timer on */
63 AO_LPC_CT_BEEP.tcr = ((1 << LPC_CT32B_TCR_CEN) |
64 (0 << LPC_CT32B_TCR_CRST));
69 ao_beep_for(uint8_t beep, AO_TICK_TYPE ticks)
79 /* Our beeper is on c32b1_mat1
80 * which is on pin pio0_14
83 lpc_ioconf.pio0_14 = ((LPC_IOCONF_FUNC_PIO0_14_CT32B1_MAT1 << LPC_IOCONF_FUNC) |
84 (LPC_IOCONF_MODE_INACTIVE << LPC_IOCONF_MODE) |
85 (0 << LPC_IOCONF_HYS) |
86 (0 << LPC_IOCONF_INV) |
87 (1 << LPC_IOCONF_ADMODE) |
88 (0 << LPC_IOCONF_OD));
90 lpc_scb.sysahbclkctrl |= (1 << LPC_SCB_SYSAHBCLKCTRL_CT32B1);
92 /* Disable the counter and reset the value */
93 AO_LPC_CT_BEEP.tcr = ((0 << LPC_CT32B_TCR_CEN) |
94 (1 << LPC_CT32B_TCR_CRST));