2 * Copyright © 2010 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
20 /* Shared mutex to protect SPI bus, must cover the entire
21 * operation, from CS low to CS high. This means that any SPI
22 * user must protect the SPI bus with this mutex
24 __xdata uint8_t ao_spi_mutex;
25 __xdata uint8_t ao_spi_dma_in_done;
26 __xdata uint8_t ao_spi_dma_out_done;
28 uint8_t ao_spi_dma_out_id;
29 uint8_t ao_spi_dma_in_id;
31 static __xdata uint8_t ao_spi_const;
33 /* Send bytes over SPI.
35 * This sets up two DMA engines, one writing the data and another reading
36 * bytes coming back. We use the bytes coming back to tell when the transfer
37 * is complete, as the transmit register is double buffered and hence signals
38 * completion one byte before the transfer is actually complete
41 ao_spi_send_bus(void __xdata *block, uint16_t len) __reentrant
44 ao_dma_set_transfer(ao_spi_dma_in_id,
49 DMA_CFG0_TMODE_SINGLE |
50 DMA_CFG0_TRIGGER_URX0,
53 DMA_CFG1_PRIORITY_NORMAL);
55 ao_dma_set_transfer(ao_spi_dma_out_id,
60 DMA_CFG0_TMODE_SINGLE |
61 DMA_CFG0_TRIGGER_UTX0,
64 DMA_CFG1_PRIORITY_NORMAL);
67 ao_dma_start(ao_spi_dma_in_id);
69 ao_dma_start(ao_spi_dma_out_id);
70 ao_dma_trigger(ao_spi_dma_out_id);
72 __critical while (!ao_spi_dma_out_done)
73 ao_sleep(&ao_spi_dma_out_done);
75 __critical while (!ao_spi_dma_in_done)
76 ao_sleep(&ao_spi_dma_in_done);
80 /* Receive bytes over SPI.
82 * This sets up tow DMA engines, one reading the data and another
83 * writing constant values to the SPI transmitter as that is what
84 * clocks the data coming in.
87 ao_spi_recv_bus(void __xdata *block, uint16_t len) __reentrant
89 ao_dma_set_transfer(ao_spi_dma_in_id,
94 DMA_CFG0_TMODE_SINGLE |
95 DMA_CFG0_TRIGGER_URX0,
98 DMA_CFG1_PRIORITY_NORMAL);
102 ao_dma_set_transfer(ao_spi_dma_out_id,
106 DMA_CFG0_WORDSIZE_8 |
107 DMA_CFG0_TMODE_SINGLE |
108 DMA_CFG0_TRIGGER_UTX0,
111 DMA_CFG1_PRIORITY_NORMAL);
113 ao_dma_start(ao_spi_dma_in_id);
114 ao_dma_start(ao_spi_dma_out_id);
115 ao_dma_trigger(ao_spi_dma_out_id);
116 __critical while (!ao_spi_dma_in_done)
117 ao_sleep(&ao_spi_dma_in_done);
121 * Initialize USART0 for SPI using config alt 2
128 * Chip select is the responsibility of the caller in master mode
133 #define UxCSR_DIRECTION UxCSR_SLAVE
136 #define UxCSR_DIRECTION UxCSR_MASTER
142 /* Set up the USART pin assignment */
143 PERCFG = (PERCFG & ~PERCFG_U0CFG_ALT_MASK) | PERCFG_U0CFG_ALT_2;
145 /* Ensure that USART0 takes precidence over USART1 for pins that
148 P2SEL = (P2SEL & ~P2SEL_PRI3P1_MASK) | P2SEL_PRI3P1_USART0;
150 /* Make the SPI pins be controlled by the USART peripheral */
151 P1SEL |= ((1 << 5) | (1 << 4) | (1 << 3) | CSS);
154 ao_spi_dma_out_id = ao_dma_alloc(&ao_spi_dma_out_done);
157 ao_spi_dma_in_id = ao_dma_alloc(&ao_spi_dma_in_done);
163 U0CSR = (UxCSR_MODE_SPI | UxCSR_RE | UxCSR_DIRECTION);
165 /* Set the baud rate and signal parameters
167 * The cc1111 is limited to a 24/8 MHz SPI clock.
168 * Every peripheral I've ever seen goes faster than that,
169 * so set the clock to 3MHz (BAUD_E 17, BAUD_M 0)
172 U0GCR = (UxGCR_CPOL_NEGATIVE |
173 UxGCR_CPHA_FIRST_EDGE |
175 (17 << UxGCR_BAUD_E_SHIFT));