2 * Copyright © 2010 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
21 /* Default pin usage for existing Altus Metrum devices */
24 #define SPI_CONST 0xff
28 * USART0 SPI config alt 1
35 * USART0 SPI config alt 2
42 * USART1 SPI config alt 1
49 * USART1 SPI config alt 2
57 * Chip select is the responsibility of the caller in master mode
61 #define SPI_BUF_0 &U0DBUFXADDR
62 #define SPI_CSR_0 U0CSR
63 #define SPI_BAUD_0 U0BAUD
64 #define SPI_GCR_0 U0GCR
65 #define SPI_CFG_MASK_0 PERCFG_U0CFG_ALT_MASK
66 #define SPI_DMA_TX_0 DMA_CFG0_TRIGGER_UTX0
67 #define SPI_DMA_RX_0 DMA_CFG0_TRIGGER_URX0
70 #define SPI_CFG_0 PERCFG_U0CFG_ALT_1
71 #define SPI_SEL_0 P0SEL
72 #define SPI_BITS_0 (1 << 3) | (1 << 2) | (1 << 5)
73 #define SPI_CSS_BIT_0 (1 << 4)
77 #define SPI_CFG_0 PERCFG_U0CFG_ALT_2
78 #define SPI_SEL_0 P1SEL
79 #define SPI_PRI_0 P2SEL_PRI3P1_USART0
80 #define SPI_BITS_0 (1 << 5) | (1 << 4) | (1 << 3)
81 #define SPI_CSS_BIT_0 (1 << 2)
87 #define SPI_BUF_1 &U1DBUFXADDR
88 #define SPI_CSR_1 U1CSR
89 #define SPI_BAUD_1 U1BAUD
90 #define SPI_GCR_1 U1GCR
91 #define SPI_CFG_MASK_1 PERCFG_U1CFG_ALT_MASK
92 #define SPI_DMA_TX_1 DMA_CFG0_TRIGGER_UTX1
93 #define SPI_DMA_RX_1 DMA_CFG0_TRIGGER_URX1
96 #define SPI_CFG_1 PERCFG_U1CFG_ALT_1
97 #define SPI_SEL_1 P0SEL
98 #define SPI_BITS_1 (1 << 4) | (1 << 5) | (1 << 3)
99 #define SPI_CSS_BIT_1 (1 << 2)
103 #define SPI_CFG_1 PERCFG_U1CFG_ALT_2
104 #define SPI_SEL_1 P1SEL
105 #define SPI_PRI_1 P2SEL_PRI3P1_USART1
106 #define SPI_BITS_1 (1 << 6) | (1 << 7) | (1 << 5)
107 #define SPI_CSS_BIT_1 (1 << 4)
114 #define SPI_BUF(bus) ((bus) ? SPI_BUF_1 : SPI_BUF_0)
115 #define SPI_CSR(bus) ((bus) ? SPI_CSR_1 : SPI_CSR_0)
116 #define SPI_BAUD(bus) ((bus) ? SPI_BAUD_1 : SPI_BAUD_0)
117 #define SPI_GCR(bus) ((bus) ? SPI_GCR_1 : SPI_GCR_0)
118 #define SPI_CFG_MASK(bus) ((bus) ? SPI_CFG_MASK_1 : SPI_CFG_MASK_0)
119 #define SPI_DMA_TX(bus) ((bus) ? SPI_DMA_TX_1 : SPI_DMA_TX_0)
120 #define SPI_DMA_RX(bus) ((bus) ? SPI_DMA_RX_1 : SPI_DMA_RX_0)
121 #define SPI_CFG(bus) ((bus) ? SPI_CFG_1 : SPI_CFG_0)
122 #define SPI_SEL(bus) ((bus) ? SPI_SEL_1 : SPI_SEL_0)
123 #define SPI_BITS(bus) ((bus) ? SPI_BITS_1 : SPI_BITS_0)
124 #define SPI_CSS_BIT(bus) ((bus) ? SPI_CSS_BIT_1 : SPI_CSS_BIT_0)
129 #define SPI_BUF(bus) SPI_BUF_0
130 #define SPI_CSR(bus) SPI_CSR_0
131 #define SPI_BAUD(bus) SPI_BAUD_0
132 #define SPI_GCR(bus) SPI_GCR_0
133 #define SPI_CFG_MASK(bus) SPI_CFG_MASK_0
134 #define SPI_DMA_TX(bus) SPI_DMA_TX_0
135 #define SPI_DMA_RX(bus) SPI_DMA_RX_0
136 #define SPI_CFG(bus) SPI_CFG_0
137 #define SPI_SEL(bus) SPI_SEL_0
138 #define SPI_BITS(bus) SPI_BITS_0
139 #define SPI_CSS_BIT(bus) SPI_CSS_BIT_0
142 #define SPI_BUF(bus) SPI_BUF_1
143 #define SPI_CSR(bus) SPI_CSR_1
144 #define SPI_BAUD(bus) SPI_BAUD_1
145 #define SPI_GCR(bus) SPI_GCR_1
146 #define SPI_CFG_MASK(bus) SPI_CFG_MASK_1
147 #define SPI_DMA_TX(bus) SPI_DMA_TX_1
148 #define SPI_DMA_RX(bus) SPI_DMA_RX_1
149 #define SPI_CFG(bus) SPI_CFG_1
150 #define SPI_SEL(bus) SPI_SEL_1
151 #define SPI_BITS(bus) SPI_BITS_1
152 #define SPI_CSS_BIT(bus) SPI_CSS_BIT_1
155 #endif /* MULTI_SPI */
158 #define CSS(bus) SPI_CSS_BIT(bus)
159 #define UxCSR_DIRECTION UxCSR_SLAVE
162 #define UxCSR_DIRECTION UxCSR_MASTER
165 /* Shared mutex to protect SPI bus, must cover the entire
166 * operation, from CS low to CS high. This means that any SPI
167 * user must protect the SPI bus with this mutex
169 __xdata uint8_t ao_spi_mutex[N_SPI];
170 __xdata uint8_t ao_spi_dma_in_done[N_SPI];
171 __xdata uint8_t ao_spi_dma_out_done[N_SPI];
173 uint8_t ao_spi_dma_out_id[N_SPI];
174 uint8_t ao_spi_dma_in_id[N_SPI];
176 static __xdata uint8_t ao_spi_const;
179 /* Send bytes over SPI.
181 * This sets up two DMA engines, one writing the data and another reading
182 * bytes coming back. We use the bytes coming back to tell when the transfer
183 * is complete, as the transmit register is double buffered and hence signals
184 * completion one byte before the transfer is actually complete
188 ao_spi_send(void __xdata *block, uint16_t len, uint8_t bus) __reentrant
191 ao_spi_send_bus(void __xdata *block, uint16_t len) __reentrant
195 ao_dma_set_transfer(ao_spi_dma_in_id[bus],
199 DMA_CFG0_WORDSIZE_8 |
200 DMA_CFG0_TMODE_SINGLE |
204 DMA_CFG1_PRIORITY_NORMAL);
205 ao_dma_set_transfer(ao_spi_dma_out_id[bus],
209 DMA_CFG0_WORDSIZE_8 |
210 DMA_CFG0_TMODE_SINGLE |
214 DMA_CFG1_PRIORITY_NORMAL);
216 ao_dma_start(ao_spi_dma_in_id[bus]);
217 ao_dma_start(ao_spi_dma_out_id[bus]);
218 ao_dma_trigger(ao_spi_dma_out_id[bus]);
220 __critical while (!ao_spi_dma_in_done[bus])
221 ao_sleep(&ao_spi_dma_in_done[bus]);
228 ao_spi_send_wait(void)
230 __critical while (!ao_spi_dma_in_done[0])
231 ao_sleep(&ao_spi_dma_in_done[0]);
235 /* Receive bytes over SPI.
237 * This sets up tow DMA engines, one reading the data and another
238 * writing constant values to the SPI transmitter as that is what
239 * clocks the data coming in.
243 ao_spi_recv(void __xdata *block, uint16_t len, uint8_t bus) __reentrant
246 ao_spi_recv_bus(void __xdata *block, uint16_t len) __reentrant
250 ao_dma_set_transfer(ao_spi_dma_in_id[bus],
254 DMA_CFG0_WORDSIZE_8 |
255 DMA_CFG0_TMODE_SINGLE |
259 DMA_CFG1_PRIORITY_NORMAL);
261 ao_spi_const = SPI_CONST;
264 ao_dma_set_transfer(ao_spi_dma_out_id[bus],
268 DMA_CFG0_WORDSIZE_8 |
269 DMA_CFG0_TMODE_SINGLE |
273 DMA_CFG1_PRIORITY_NORMAL);
276 ao_dma_start(ao_spi_dma_in_id[bus]);
278 ao_dma_start(ao_spi_dma_out_id[bus]);
279 ao_dma_trigger(ao_spi_dma_out_id[bus]);
280 __critical while (!ao_spi_dma_in_done[bus])
281 ao_sleep(&ao_spi_dma_in_done[bus]);
287 ao_spi_recv_wait(void)
289 __critical while (!ao_spi_dma_in_done[0])
290 ao_sleep(&ao_spi_dma_in_done[0]);
296 * SPI master/slave mode
298 /* Set the baud rate and signal parameters
300 * The cc1111 is limited to a 24/8 MHz SPI clock.
301 * Every peripheral I've ever seen goes faster than that,
302 * so set the clock to 3MHz (BAUD_E 17, BAUD_M 0)
304 #define SPI_INIT(bus,o) do { \
305 /* Set up the USART pin assignment */ \
306 PERCFG = (PERCFG & ~SPI_CFG_MASK(bus)) | SPI_CFG(bus); \
308 /* Make the SPI pins be controlled by the USART peripheral */ \
309 SPI_SEL(bus) |= SPI_BITS(bus) | CSS(bus); \
310 SPI_CSR(bus) = (UxCSR_MODE_SPI | UxCSR_RE | UxCSR_DIRECTION); \
312 SPI_GCR(bus) = (UxGCR_CPOL_NEGATIVE | \
313 UxGCR_CPHA_FIRST_EDGE | \
315 (17 << UxGCR_BAUD_E_SHIFT)); \
316 /* Set up OUT DMA */ \
317 ao_spi_dma_out_id[o] = ao_dma_alloc(&ao_spi_dma_out_done[o]); \
319 /* Set up IN DMA */ \
320 ao_spi_dma_in_id[o] = ao_dma_alloc(&ao_spi_dma_in_done[o]); \
326 /* Ensure that SPI USART takes precidence over the other USART
327 * for pins that they share
330 P2SEL = (P2SEL & ~P2SEL_PRI3P1_MASK) | SPI_PRI;
337 SPI_INIT(1, MULTI_SPI);