2 * Copyright © 2009 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
20 const __code struct ao_serial_speed ao_serial_speeds[] = {
21 /* [AO_SERIAL_SPEED_4800] = */ {
23 /* .gcr = */ (7 << UxGCR_BAUD_E_SHIFT) | UxGCR_ORDER_LSB
25 /* [AO_SERIAL_SPEED_9600] = */ {
27 /* .gcr = */ (8 << UxGCR_BAUD_E_SHIFT) | UxGCR_ORDER_LSB
29 /* [AO_SERIAL_SPEED_19200] = */ {
31 /* .gcr = */ (9 << UxGCR_BAUD_E_SHIFT) | UxGCR_ORDER_LSB
33 /* [AO_SERIAL_SPEED_57600] = */ {
35 /* .gcr = */ (11 << UxGCR_BAUD_E_SHIFT) | UxGCR_ORDER_LSB
37 /* [AO_SERIAL_SPEED_115200] = */ {
39 /* .gcr = */ (12 << UxGCR_BAUD_E_SHIFT) | UxGCR_ORDER_LSB
43 #define AO_SERIAL_SPEED_MAX AO_SERIAL_SPEED_115200
45 #if HAS_SERIAL_1_ALT_1
46 #define SERIAL_1_RTS P0_3
48 #define SERIAL_1_RTS P1_5
51 #if HAS_SERIAL_0_ALT_1
52 #define SERIAL_0_RTS P0_5
54 #define SERIAL_0_RTS P1_3
59 volatile __xdata struct ao_fifo ao_serial0_rx_fifo;
60 volatile __xdata struct ao_fifo ao_serial0_tx_fifo;
63 ao_serial0_rx_isr(void) __interrupt 2
65 if (!ao_fifo_full(ao_serial0_rx_fifo))
66 ao_fifo_insert(ao_serial0_rx_fifo, U0DBUF);
67 ao_wakeup(&ao_serial0_rx_fifo);
68 #if USE_SERIAL_0_STDIN
69 ao_wakeup(&ao_stdin_ready);
71 #if HAS_SERIAL_0_HW_FLOW
72 if (ao_fifo_mostly(ao_serial0_rx_fifo))
77 static __xdata uint8_t ao_serial0_tx_started;
80 ao_serial0_tx_start(void)
82 if (!ao_fifo_empty(ao_serial0_tx_fifo) &&
83 !ao_serial0_tx_started)
85 ao_serial0_tx_started = 1;
86 ao_fifo_remove(ao_serial0_tx_fifo, U0DBUF);
91 ao_serial0_tx_isr(void) __interrupt 7
94 ao_serial0_tx_started = 0;
95 ao_serial0_tx_start();
96 ao_wakeup(&ao_serial0_tx_fifo);
100 ao_serial0_getchar(void) __critical
103 while (ao_fifo_empty(ao_serial0_rx_fifo))
104 ao_sleep(&ao_serial0_rx_fifo);
105 ao_fifo_remove(ao_serial0_rx_fifo, c);
106 #if HAS_SERIAL_0_HW_FLOW
107 if (ao_fifo_barely(ao_serial0_rx_fifo))
113 #if USE_SERIAL_0_STDIN
115 _ao_serial0_pollchar(void)
118 if (ao_fifo_empty(ao_serial0_rx_fifo))
119 return AO_READ_AGAIN;
120 ao_fifo_remove(ao_serial0_rx_fifo,c);
121 #if HAS_SERIAL_0_HW_FLOW
122 if (ao_fifo_barely(ao_serial0_rx_fifo))
130 ao_serial0_putchar(char c) __critical
132 while (ao_fifo_full(ao_serial0_tx_fifo))
133 ao_sleep(&ao_serial0_tx_fifo);
134 ao_fifo_insert(ao_serial0_tx_fifo, c);
135 ao_serial0_tx_start();
139 ao_serial0_drain(void) __critical
141 while (!ao_fifo_empty(ao_serial0_tx_fifo))
142 ao_sleep(&ao_serial0_tx_fifo);
146 ao_serial0_set_speed(uint8_t speed)
149 if (speed > AO_SERIAL_SPEED_MAX)
151 U0UCR |= UxUCR_FLUSH;
152 U0BAUD = ao_serial_speeds[speed].baud;
153 U0GCR = ao_serial_speeds[speed].gcr;
155 #endif /* HAS_SERIAL_0 */
159 volatile __xdata struct ao_fifo ao_serial1_rx_fifo;
160 volatile __xdata struct ao_fifo ao_serial1_tx_fifo;
163 ao_serial1_rx_isr(void) __interrupt 3
165 if (!ao_fifo_full(ao_serial1_rx_fifo))
166 ao_fifo_insert(ao_serial1_rx_fifo, U1DBUF);
167 ao_wakeup(&ao_serial1_rx_fifo);
168 #if USE_SERIAL_1_STDIN
169 ao_wakeup(&ao_stdin_ready);
171 #if HAS_SERIAL_1_HW_FLOW
172 if (ao_fifo_mostly(ao_serial1_rx_fifo))
177 static __xdata uint8_t ao_serial1_tx_started;
180 ao_serial1_tx_start(void)
182 if (!ao_fifo_empty(ao_serial1_tx_fifo) &&
183 !ao_serial1_tx_started)
185 ao_serial1_tx_started = 1;
186 ao_fifo_remove(ao_serial1_tx_fifo, U1DBUF);
191 ao_serial1_tx_isr(void) __interrupt 14
194 ao_serial1_tx_started = 0;
195 ao_serial1_tx_start();
196 ao_wakeup(&ao_serial1_tx_fifo);
200 ao_serial1_getchar(void) __critical
203 while (ao_fifo_empty(ao_serial1_rx_fifo))
204 ao_sleep(&ao_serial1_rx_fifo);
205 ao_fifo_remove(ao_serial1_rx_fifo, c);
206 #if HAS_SERIAL_1_HW_FLOW
207 if (ao_fifo_barely(ao_serial1_rx_fifo))
213 #if USE_SERIAL_1_STDIN
215 _ao_serial1_pollchar(void)
218 if (ao_fifo_empty(ao_serial1_rx_fifo))
219 return AO_READ_AGAIN;
220 ao_fifo_remove(ao_serial1_rx_fifo,c);
221 #if HAS_SERIAL_1_HW_FLOW
222 if (ao_fifo_barely(ao_serial1_rx_fifo))
230 ao_serial1_putchar(char c) __critical
232 while (ao_fifo_full(ao_serial1_tx_fifo))
233 ao_sleep(&ao_serial1_tx_fifo);
234 ao_fifo_insert(ao_serial1_tx_fifo, c);
235 ao_serial1_tx_start();
239 ao_serial1_drain(void) __critical
241 while (!ao_fifo_empty(ao_serial1_tx_fifo))
242 ao_sleep(&ao_serial1_tx_fifo);
246 ao_serial1_set_speed(uint8_t speed)
249 if (speed > AO_SERIAL_SPEED_MAX)
251 U1UCR |= UxUCR_FLUSH;
252 U1BAUD = ao_serial_speeds[speed].baud;
253 U1GCR = ao_serial_speeds[speed].gcr;
256 #endif /* HAS_SERIAL_1 */
262 #if HAS_SERIAL_0_ALT_1
263 /* Set up the USART pin assignment */
264 PERCFG = (PERCFG & ~PERCFG_U0CFG_ALT_MASK) | PERCFG_U0CFG_ALT_1;
266 P2DIR = (P2DIR & ~P2DIR_PRIP0_MASK) | P2DIR_PRIP0_USART0_USART1;
268 /* Make the USART pins be controlled by the USART */
269 P0SEL |= (1 << 2) | (1 << 3);
270 #if HAS_SERIAL_0_HW_FLOW
278 /* Set up the USART pin assignment */
279 PERCFG = (PERCFG & ~PERCFG_U0CFG_ALT_MASK) | PERCFG_U0CFG_ALT_2;
281 P2SEL = (P2SEL & ~(P2SEL_PRI3P1_MASK | P2SEL_PRI0P1_MASK)) |
282 (P2SEL_PRI3P1_USART0 | P2SEL_PRI0P1_USART0);
284 /* Make the USART pins be controlled by the USART */
285 P1SEL |= (1 << 5) | (1 << 4);
286 #if HAS_SERIAL_0_HW_FLOW
295 /* UART mode with receiver enabled */
296 U0CSR = (UxCSR_MODE_UART | UxCSR_RE);
298 /* Pick a 9600 baud rate */
299 ao_serial0_set_speed(AO_SERIAL_SPEED_9600);
301 /* Reasonable serial parameters */
302 U0UCR = (UxUCR_FLUSH |
303 #if HAS_SERIAL_0_HW_FLOW
308 UxUCR_D9_EVEN_PARITY |
310 UxUCR_PARITY_DISABLE |
311 UxUCR_SPB_1_STOP_BIT |
317 #if USE_SERIAL_0_STDIN && !DELAY_SERIAL_0_STDIN
318 ao_add_stdio(_ao_serial0_pollchar,
322 #endif /* HAS_SERIAL_0 */
325 #if HAS_SERIAL_1_ALT_1
326 /* Set up the USART pin assignment */
327 PERCFG = (PERCFG & ~PERCFG_U1CFG_ALT_MASK) | PERCFG_U1CFG_ALT_1;
329 P2DIR = (P2DIR & ~P2DIR_PRIP0_MASK) | P2DIR_PRIP0_USART1_USART0;
331 /* Make the USART pins be controlled by the USART */
332 P0SEL |= (1 << 5) | (1 << 4);
333 #if HAS_SERIAL_1_HW_FLOW
334 /* SW RTS control (hw doesn't work) */
338 /* HW CTS. Maybe this works? */
343 /* Set up the USART pin assignment */
344 PERCFG = (PERCFG & ~PERCFG_U1CFG_ALT_MASK) | PERCFG_U1CFG_ALT_2;
346 P2SEL = (P2SEL & ~(P2SEL_PRI3P1_MASK | P2SEL_PRI2P1_MASK)) |
347 (P2SEL_PRI3P1_USART1 | P2SEL_PRI2P1_USART1);
349 /* Make the USART pins be controlled by the USART */
350 P1SEL |= (1 << 6) | (1 << 7);
351 #if HAS_SERIAL_1_HW_FLOW
352 /* SW RTS control (hw doesn't work) */
356 /* HW CTS. Maybe this works? */
362 /* UART mode with receiver enabled */
363 U1CSR = (UxCSR_MODE_UART | UxCSR_RE);
365 /* Pick a 4800 baud rate */
366 ao_serial1_set_speed(AO_SERIAL_SPEED_4800);
368 /* Reasonable serial parameters */
369 U1UCR = (UxUCR_FLUSH |
370 #if HAS_SERIAL_1_HW_FLOW
375 UxUCR_D9_EVEN_PARITY |
377 UxUCR_PARITY_DISABLE |
378 UxUCR_SPB_1_STOP_BIT |
385 #if USE_SERIAL_1_STDIN && !DELAY_SERIAL_1_STDIN
386 ao_add_stdio(_ao_serial1_pollchar,
390 #endif /* HAS_SERIAL_1 */