2 * Copyright © 2011 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
21 ao_spi_slave_recv(uint8_t *buf, uint8_t len)
24 while (!(SPSR & (1 << SPIF)))
25 if ((PINB & (1 << PINB0)))
33 ao_spi_slave_send(uint8_t *buf, uint8_t len)
37 while (!(SPSR & (1 << SPIF)))
38 if ((PINB & (1 << PINB0)))
41 /* Clear pending SPIF bit by reading */
45 static uint8_t ao_spi_slave_running;
47 ISR(PCINT0_vect, ISR_BLOCK)
50 if ((PINB & (1 << PORTB0)) == 0)
53 if ((PINB & (1 << PORTB2)) == 0)
56 if (!ao_spi_slave_running) {
57 ao_spi_slave_running = 1;
61 ao_spi_slave_running = 0;
66 ao_spi_slave_init(void)
68 /* We'd like to have a pull-up on SS so that disconnecting the
69 * TM would cause any SPI transaction to abort. However, when
70 * I tried that, SPI transactions would spontaneously abort,
71 * making me assume that we needed a less aggressive pull-up
72 * than is offered inside the AVR
75 PCMSK0 |= (1 << PCINT0); /* Enable PCINT0 pin change */
76 PCICR |= (1 << PCIE0); /* Enable pin change interrupt */
78 DDRB = ((DDRB & 0xf0) |
79 (1 << 3) | /* MISO, output */
80 (0 << 2) | /* MOSI, input */
81 (0 << 1) | /* SCK, input */
82 (0 << 0)); /* SS, input */
84 PORTB = ((PORTB & 0xf0) |
85 (1 << 3) | /* MISO, output */
86 (0 << 2) | /* MOSI, no pull-up */
87 (0 << 1) | /* SCK, no pull-up */
88 (1 << 0)); /* SS, pull-up */
91 PCMSK0 |= (1 << PCINT2); /* Enable PCINT2 pin change */
92 PCICR |= (1 << PCIE0); /* Enable pin change interrupt */
94 DDRB = ((DDRB & 0xf0) |
95 (0 << 5) | /* SCK, input */
96 (1 << 4) | /* MISO, output */
97 (0 << 3) | /* MOSI, input */
98 (0 << 2)); /* SS, input */
100 PORTB = ((PORTB & 0xf0) |
101 (0 << 5) | /* SCK, no pull-up */
102 (1 << 4) | /* MISO, output */
103 (0 << 3) | /* MOSI, no pull-up */
104 (1 << 2)); /* SS, pull-up */
107 SPCR = (0 << SPIE) | /* Disable SPI interrupts */
108 (1 << SPE) | /* Enable SPI */
109 (0 << DORD) | /* MSB first */
110 (0 << MSTR) | /* Slave mode */
111 (0 << CPOL) | /* Clock low when idle */
112 (0 << CPHA); /* Sample at leading clock edge */