2 * Copyright © 2011 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
22 ao_spi_slave_recv(void *buf, uint16_t len)
26 while (!(SPSR & (1 << SPIF)))
27 if ((PINB & (1 << PINB0)))
35 ao_spi_slave_send(void *buf, uint16_t len)
40 while (!(SPSR & (1 << SPIF)))
41 if ((PINB & (1 << PINB0)))
44 /* Clear pending SPIF bit by reading */
48 static uint8_t ao_spi_slave_running;
50 ISR(PCINT0_vect, ISR_BLOCK)
53 if ((PINB & (1 << PORTB0)) == 0)
56 if ((PINB & (1 << PORTB2)) == 0)
59 if (!ao_spi_slave_running) {
60 ao_spi_slave_running = 1;
64 ao_spi_slave_running = 0;
69 ao_spi_slave_init(void)
71 /* We'd like to have a pull-up on SS so that disconnecting the
72 * TM would cause any SPI transaction to abort. However, when
73 * I tried that, SPI transactions would spontaneously abort,
74 * making me assume that we needed a less aggressive pull-up
75 * than is offered inside the AVR
78 PCMSK0 |= (1 << PCINT0); /* Enable PCINT0 pin change */
79 PCICR |= (1 << PCIE0); /* Enable pin change interrupt */
81 DDRB = ((DDRB & 0xf0) |
82 (1 << 3) | /* MISO, output */
83 (0 << 2) | /* MOSI, input */
84 (0 << 1) | /* SCK, input */
85 (0 << 0)); /* SS, input */
87 PORTB = ((PORTB & 0xf0) |
88 (1 << 3) | /* MISO, output */
89 (0 << 2) | /* MOSI, no pull-up */
90 (0 << 1) | /* SCK, no pull-up */
91 (1 << 0)); /* SS, pull-up */
94 PCMSK0 |= (1 << PCINT2); /* Enable PCINT2 pin change */
95 PCICR |= (1 << PCIE0); /* Enable pin change interrupt */
97 DDRB = ((DDRB & 0xf0) |
98 (0 << 5) | /* SCK, input */
99 (1 << 4) | /* MISO, output */
100 (0 << 3) | /* MOSI, input */
101 (0 << 2)); /* SS, input */
103 PORTB = ((PORTB & 0xf0) |
104 (0 << 5) | /* SCK, no pull-up */
105 (1 << 4) | /* MISO, output */
106 (0 << 3) | /* MOSI, no pull-up */
107 (1 << 2)); /* SS, pull-up */
110 SPCR = (0 << SPIE) | /* Disable SPI interrupts */
111 (1 << SPE) | /* Enable SPI */
112 (0 << DORD) | /* MSB first */
113 (0 << MSTR) | /* Slave mode */
114 (0 << CPOL) | /* Clock low when idle */
115 (0 << CPHA); /* Sample at leading clock edge */