2 * Copyright © 2010 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
20 __xdata uint8_t ao_spi_mutex;
21 __xdata uint8_t ao_spi_dma_in_done;
22 __xdata uint8_t ao_spi_dma_out_done;
24 uint8_t ao_spi_dma_out_id;
25 uint8_t ao_spi_dma_in_id;
27 static __xdata uint8_t ao_spi_const = 0xff;
29 /* Send bytes over SPI.
31 * This sets up two DMA engines, one writing the data and another reading
32 * bytes coming back. We use the bytes coming back to tell when the transfer
33 * is complete, as the transmit register is double buffered and hence signals
34 * completion one byte before the transfer is actually complete
37 ao_spi_send(void __xdata *block, uint16_t len) __reentrant
39 ao_mutex_get(&ao_spi_mutex);
40 ao_dma_set_transfer(ao_spi_dma_in_id,
45 DMA_CFG0_TMODE_SINGLE |
46 DMA_CFG0_TRIGGER_URX0,
49 DMA_CFG1_PRIORITY_NORMAL);
51 ao_dma_set_transfer(ao_spi_dma_out_id,
56 DMA_CFG0_TMODE_SINGLE |
57 DMA_CFG0_TRIGGER_UTX0,
60 DMA_CFG1_PRIORITY_NORMAL);
62 ao_dma_start(ao_spi_dma_in_id);
63 ao_dma_start(ao_spi_dma_out_id);
64 ao_dma_trigger(ao_spi_dma_out_id);
65 __critical while (!ao_spi_dma_in_done)
66 ao_sleep(&ao_spi_dma_in_done);
67 ao_mutex_put(&ao_spi_mutex);
70 /* Receive bytes over SPI.
72 * This sets up tow DMA engines, one reading the data and another
73 * writing constant values to the SPI transmitter as that is what
74 * clocks the data coming in.
77 ao_spi_recv(void __xdata *block, uint16_t len) __reentrant
79 ao_mutex_get(&ao_spi_mutex);
80 ao_dma_set_transfer(ao_spi_dma_in_id,
85 DMA_CFG0_TMODE_SINGLE |
86 DMA_CFG0_TRIGGER_URX0,
89 DMA_CFG1_PRIORITY_NORMAL);
91 ao_dma_set_transfer(ao_spi_dma_out_id,
96 DMA_CFG0_TMODE_SINGLE |
97 DMA_CFG0_TRIGGER_UTX0,
100 DMA_CFG1_PRIORITY_NORMAL);
102 ao_dma_start(ao_spi_dma_in_id);
103 ao_dma_start(ao_spi_dma_out_id);
104 ao_dma_trigger(ao_spi_dma_out_id);
105 __critical while (!ao_spi_dma_in_done)
106 ao_sleep(&ao_spi_dma_in_done);
107 ao_mutex_put(&ao_spi_mutex);
111 * Initialize USART0 for SPI using config alt 2
117 * Chip select is the responsibility of the caller
123 /* Set up the USART pin assignment */
124 PERCFG = (PERCFG & ~PERCFG_U0CFG_ALT_MASK) | PERCFG_U0CFG_ALT_2;
126 /* Ensure that USART0 takes precidence over USART1 for pins that
129 P2SEL = (P2SEL & ~P2SEL_PRI3P1_MASK) | P2SEL_PRI3P1_USART0;
131 /* Make the SPI pins be controlled by the USART peripheral */
132 P1SEL |= ((1 << 5) | (1 << 4) | (1 << 3));
135 ao_spi_dma_out_id = ao_dma_alloc(&ao_spi_dma_out_done);
138 ao_spi_dma_in_id = ao_dma_alloc(&ao_spi_dma_in_done);
144 U0CSR = (UxCSR_MODE_SPI | UxCSR_RE | UxCSR_MASTER);
146 /* Set the baud rate and signal parameters
148 * The cc1111 is limited to a 24/8 MHz SPI clock.
149 * Every peripheral I've ever seen goes faster than that,
150 * so set the clock to 3MHz (BAUD_E 17, BAUD_M 0)
153 U0GCR = (UxGCR_CPOL_NEGATIVE |
154 UxGCR_CPHA_FIRST_EDGE |
156 (17 << UxGCR_BAUD_E_SHIFT));