2 * Copyright © 2010 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
20 /* Total bytes of available storage */
21 __pdata uint32_t ao_storage_total;
23 /* Block size - device is erased in these units. At least 256 bytes */
24 __pdata uint32_t ao_storage_block;
26 /* Byte offset of config block. Will be ao_storage_block bytes long */
27 __pdata uint32_t ao_storage_config;
29 /* Storage unit size - device reads and writes must be within blocks of this size. Usually 256 bytes. */
30 __pdata uint16_t ao_storage_unit;
33 * Each flash chip is arranged in 64kB sectors; the
34 * chip cannot erase in units smaller than that.
36 * Writing happens in units of 256 byte pages and
37 * can only change bits from 1 to 0. So, you can rewrite
38 * the same contents, or append to an existing page easily enough
41 #define M25_WREN 0x06 /* Write Enable */
42 #define M25_WRDI 0x04 /* Write Disable */
43 #define M25_RDID 0x9f /* Read Identification */
44 #define M25_RDSR 0x05 /* Read Status Register */
45 #define M25_WRSR 0x01 /* Write Status Register */
46 #define M25_READ 0x03 /* Read Data Bytes */
47 #define M25_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */
48 #define M25_PP 0x02 /* Page Program */
49 #define M25_SE 0xd8 /* Sector Erase */
50 #define M25_BE 0xc7 /* Bulk Erase */
51 #define M25_DP 0xb9 /* Deep Power-down */
54 #define M25_MANUF_OFFSET 0
55 #define M25_MEMORY_TYPE_OFFSET 1
56 #define M25_CAPACITY_OFFSET 2
57 #define M25_UID_OFFSET 3
58 #define M25_CFI_OFFSET 4
59 #define M25_RDID_LEN 4 /* that's all we need */
61 #define M25_CAPACITY_128KB 0x11
62 #define M25_CAPACITY_256KB 0x12
63 #define M25_CAPACITY_512KB 0x13
64 #define M25_CAPACITY_1MB 0x14
65 #define M25_CAPACITY_2MB 0x15
68 * Status register bits
71 #define M25_STATUS_SRWD (1 << 7) /* Status register write disable */
72 #define M25_STATUS_BP_MASK (7 << 2) /* Block protect bits */
73 #define M25_STATUS_BP_SHIFT (2)
74 #define M25_STATUS_WEL (1 << 1) /* Write enable latch */
75 #define M25_STATUS_WIP (1 << 0) /* Write in progress */
78 * On teleterra, the m25 chip select pins are
79 * wired on P0_0 through P0_3.
83 static uint8_t ao_m25_size[M25_MAX_CHIPS]; /* number of sectors in each chip */
84 static uint8_t ao_m25_pin[M25_MAX_CHIPS]; /* chip select pin for each chip */
85 static uint8_t ao_m25_numchips; /* number of chips detected */
87 static uint8_t ao_m25_total; /* total sectors available */
88 static uint8_t ao_m25_wip; /* write in progress */
90 static __xdata uint8_t ao_m25_mutex;
93 * This little array is abused to send and receive data. A particular
94 * caution -- the read and write addresses are written into the last
95 * three bytes of the array by ao_m25_set_page_address and then the
96 * first byte is used by ao_m25_wait_wip and ao_m25_write_enable, neither
97 * of which touch those last three bytes.
100 static __xdata uint8_t ao_m25_instruction[4];
102 #define M25_SELECT(cs) ao_spi_get_mask(SPI_CS_PORT,cs)
103 #define M25_DESELECT(cs) ao_spi_put_mask(SPI_CS_PORT,cs)
105 #define M25_BLOCK_SHIFT 16
106 #define M25_BLOCK 65536L
107 #define M25_POS_TO_SECTOR(pos) ((uint8_t) ((pos) >> M25_BLOCK_SHIFT))
108 #define M25_SECTOR_TO_POS(sector) (((uint32_t) (sector)) << M25_BLOCK_SHIFT)
111 * Block until the specified chip is done writing
114 ao_m25_wait_wip(uint8_t cs)
116 if (ao_m25_wip & cs) {
118 ao_m25_instruction[0] = M25_RDSR;
119 ao_spi_send(ao_m25_instruction, 1);
121 ao_spi_recv(ao_m25_instruction, 1);
122 } while (ao_m25_instruction[0] & M25_STATUS_WIP);
129 * Set the write enable latch so that page program and sector
130 * erase commands will work. Also mark the chip as busy writing
131 * so that future operations will block until the WIP bit goes off
134 ao_m25_write_enable(uint8_t cs)
137 ao_m25_instruction[0] = M25_WREN;
138 ao_spi_send(&ao_m25_instruction, 1);
145 * Returns the number of 64kB sectors
148 ao_m25_read_capacity(uint8_t cs)
152 ao_m25_instruction[0] = M25_RDID;
153 ao_spi_send(ao_m25_instruction, 1);
154 ao_spi_recv(ao_m25_instruction, M25_RDID_LEN);
157 /* Check to see if the chip is present */
158 if (ao_m25_instruction[0] == 0xff)
160 capacity = ao_m25_instruction[M25_CAPACITY_OFFSET];
162 /* Sanity check capacity number */
163 if (capacity < 0x11 || 0x1f < capacity)
165 return 1 << (capacity - 0x10);
169 ao_m25_set_address(uint32_t pos)
172 #if M25_MAX_CHIPS > 1
175 for (chip = 0; chip < ao_m25_numchips; chip++) {
176 size = ao_m25_size[chip];
177 if (M25_POS_TO_SECTOR(pos) < size)
179 pos -= M25_SECTOR_TO_POS(size);
181 if (chip == ao_m25_numchips)
184 chip = ao_m25_pin[chip];
188 ao_m25_wait_wip(chip);
190 ao_m25_instruction[1] = pos >> 16;
191 ao_m25_instruction[2] = pos >> 8;
192 ao_m25_instruction[3] = pos;
197 * Scan the possible chip select lines
198 * to see which flash chips are connected
203 #if M25_MAX_CHIPS > 1
210 #if M25_MAX_CHIPS > 1
212 for (pin = 1; pin != 0; pin <<= 1) {
213 if (M25_CS_MASK & pin) {
214 size = ao_m25_read_capacity(pin);
216 ao_m25_size[ao_m25_numchips] = size;
217 ao_m25_pin[ao_m25_numchips] = pin;
218 ao_m25_total += size;
224 ao_m25_total = ao_m25_read_capacity(M25_CS_MASK);
228 ao_storage_total = M25_SECTOR_TO_POS(ao_m25_total);
229 ao_storage_block = M25_BLOCK;
230 ao_storage_config = ao_storage_total - M25_BLOCK;
231 ao_storage_unit = 256;
236 * Erase the specified sector
239 ao_storage_erase(uint32_t pos) __reentrant
243 if (pos >= ao_storage_total || pos + ao_storage_block > ao_storage_total)
246 ao_mutex_get(&ao_m25_mutex);
249 cs = ao_m25_set_address(pos);
252 ao_m25_write_enable(cs);
254 ao_m25_instruction[0] = M25_SE;
256 ao_spi_send(ao_m25_instruction, 4);
260 ao_mutex_put(&ao_m25_mutex);
268 ao_storage_device_write(uint32_t pos, __xdata void *d, uint16_t len) __reentrant
272 if (pos >= ao_storage_total || pos + len > ao_storage_total)
275 ao_mutex_get(&ao_m25_mutex);
278 cs = ao_m25_set_address(pos);
279 ao_m25_write_enable(cs);
281 ao_m25_instruction[0] = M25_PP;
283 ao_spi_send(ao_m25_instruction, 4);
287 ao_mutex_put(&ao_m25_mutex);
295 ao_storage_device_read(uint32_t pos, __xdata void *d, uint16_t len) __reentrant
299 if (pos >= ao_storage_total || pos + len > ao_storage_total)
301 ao_mutex_get(&ao_m25_mutex);
304 cs = ao_m25_set_address(pos);
306 /* No need to use the FAST_READ as we're running at only 8MHz */
307 ao_m25_instruction[0] = M25_READ;
309 ao_spi_send(ao_m25_instruction, 4);
313 ao_mutex_put(&ao_m25_mutex);
318 ao_storage_flush(void) __reentrant
323 ao_storage_setup(void)
325 ao_mutex_get(&ao_m25_mutex);
327 ao_mutex_put(&ao_m25_mutex);
331 ao_storage_device_info(void) __reentrant
334 #if M25_MAX_CHIPS > 1
338 ao_mutex_get(&ao_m25_mutex);
340 ao_mutex_put(&ao_m25_mutex);
342 #if M25_MAX_CHIPS > 1
343 printf ("Detected chips %d size %d\n", ao_m25_numchips, ao_m25_total);
344 for (chip = 0; chip < ao_m25_numchips; chip++)
345 printf ("Flash chip %d select %02x size %d\n",
346 chip, ao_m25_pin[chip], ao_m25_size[chip]);
348 printf ("Detected chips 1 size %d\n", ao_m25_total);
351 printf ("Available chips:\n");
352 for (cs = 1; cs != 0; cs <<= 1) {
353 if ((M25_CS_MASK & cs) == 0)
356 ao_mutex_get(&ao_m25_mutex);
358 ao_m25_instruction[0] = M25_RDID;
359 ao_spi_send(ao_m25_instruction, 1);
360 ao_spi_recv(ao_m25_instruction, M25_RDID_LEN);
363 printf ("Select %02x manf %02x type %02x cap %02x uid %02x\n",
365 ao_m25_instruction[M25_MANUF_OFFSET],
366 ao_m25_instruction[M25_MEMORY_TYPE_OFFSET],
367 ao_m25_instruction[M25_CAPACITY_OFFSET],
368 ao_m25_instruction[M25_UID_OFFSET]);
369 ao_mutex_put(&ao_m25_mutex);
374 ao_storage_device_init(void)
376 /* Set up chip select wires */
377 SPI_CS_PORT |= M25_CS_MASK; /* raise all CS pins */
378 SPI_CS_DIR |= M25_CS_MASK; /* set CS pins as outputs */
379 SPI_CS_SEL &= ~M25_CS_MASK; /* set CS pins as GPIO */