2 * Copyright © 2009 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
22 * Using SPI on USART 0, with P1_2 as the chip select
28 __xdata uint8_t ao_ee_dma_in_done;
29 __xdata uint8_t ao_ee_dma_out_done;
30 __xdata uint8_t ao_ee_mutex;
32 uint8_t ao_ee_dma_out_id;
33 uint8_t ao_ee_dma_in_id;
35 static __xdata uint8_t ao_ee_const = 0xff;
37 #define ao_ee_delay() do { \
43 void ao_ee_cs_low(void)
50 void ao_ee_cs_high(void)
57 /* Send bytes over SPI.
59 * This sets up two DMA engines, one writing the data and another reading
60 * bytes coming back. We use the bytes coming back to tell when the transfer
61 * is complete, as the transmit register is double buffered and hence signals
62 * completion one byte before the transfer is actually complete
65 ao_ee_send(void __xdata *block, uint16_t len)
67 ao_dma_set_transfer(ao_ee_dma_in_id,
72 DMA_CFG0_TMODE_SINGLE |
73 DMA_CFG0_TRIGGER_URX0,
76 DMA_CFG1_PRIORITY_NORMAL);
78 ao_dma_set_transfer(ao_ee_dma_out_id,
83 DMA_CFG0_TMODE_SINGLE |
84 DMA_CFG0_TRIGGER_UTX0,
87 DMA_CFG1_PRIORITY_NORMAL);
89 ao_dma_start(ao_ee_dma_in_id);
90 ao_dma_start(ao_ee_dma_out_id);
91 ao_dma_trigger(ao_ee_dma_out_id);
92 __critical while (!ao_ee_dma_in_done)
93 ao_sleep(&ao_ee_dma_in_done);
96 /* Receive bytes over SPI.
98 * This sets up tow DMA engines, one reading the data and another
99 * writing constant values to the SPI transmitter as that is what
100 * clocks the data coming in.
103 ao_ee_recv(void __xdata *block, uint16_t len)
105 ao_dma_set_transfer(ao_ee_dma_in_id,
109 DMA_CFG0_WORDSIZE_8 |
110 DMA_CFG0_TMODE_SINGLE |
111 DMA_CFG0_TRIGGER_URX0,
114 DMA_CFG1_PRIORITY_NORMAL);
116 ao_dma_set_transfer(ao_ee_dma_out_id,
120 DMA_CFG0_WORDSIZE_8 |
121 DMA_CFG0_TMODE_SINGLE |
122 DMA_CFG0_TRIGGER_UTX0,
125 DMA_CFG1_PRIORITY_NORMAL);
127 ao_dma_start(ao_ee_dma_in_id);
128 ao_dma_start(ao_ee_dma_out_id);
129 ao_dma_trigger(ao_ee_dma_out_id);
130 __critical while (!ao_ee_dma_in_done)
131 ao_sleep(&ao_ee_dma_in_done);
136 struct ao_ee_instruction {
139 } __xdata ao_ee_instruction;
142 ao_ee_write_enable(void)
145 ao_ee_instruction.instruction = EE_WREN;
146 ao_ee_send(&ao_ee_instruction, 1);
154 ao_ee_instruction.instruction = EE_RDSR;
155 ao_ee_send(&ao_ee_instruction, 1);
156 ao_ee_recv(&ao_ee_instruction, 1);
158 return ao_ee_instruction.instruction;
162 ao_ee_wrsr(uint8_t status)
165 ao_ee_instruction.instruction = EE_WRSR;
166 ao_ee_instruction.address[0] = status;
167 ao_ee_send(&ao_ee_instruction, 2);
171 #define EE_BLOCK_NONE 0xffff
173 static __xdata uint8_t ao_ee_data[EE_BLOCK];
174 static __pdata uint16_t ao_ee_block = EE_BLOCK_NONE;
175 static __pdata uint8_t ao_ee_block_dirty;
177 /* Write the current block to the EEPROM */
179 ao_ee_write_block(void)
183 status = ao_ee_rdsr();
184 if (status & (EE_STATUS_BP0|EE_STATUS_BP1|EE_STATUS_WPEN)) {
185 status &= ~(EE_STATUS_BP0|EE_STATUS_BP1|EE_STATUS_WPEN);
188 ao_ee_write_enable();
190 ao_ee_instruction.instruction = EE_WRITE;
191 ao_ee_instruction.address[0] = ao_ee_block >> 8;
192 ao_ee_instruction.address[1] = ao_ee_block;
193 ao_ee_instruction.address[2] = 0;
194 ao_ee_send(&ao_ee_instruction, 4);
195 ao_ee_send(ao_ee_data, EE_BLOCK);
198 uint8_t status = ao_ee_rdsr();
199 if ((status & EE_STATUS_WIP) == 0)
204 /* Read the current block from the EEPROM */
206 ao_ee_read_block(void)
209 ao_ee_instruction.instruction = EE_READ;
210 ao_ee_instruction.address[0] = ao_ee_block >> 8;
211 ao_ee_instruction.address[1] = ao_ee_block;
212 ao_ee_instruction.address[2] = 0;
213 ao_ee_send(&ao_ee_instruction, 4);
214 ao_ee_recv(ao_ee_data, EE_BLOCK);
219 ao_ee_flush_internal(void)
221 if (ao_ee_block_dirty) {
223 ao_ee_block_dirty = 0;
228 ao_ee_fill(uint16_t block)
230 if (block != ao_ee_block) {
231 ao_ee_flush_internal();
238 ao_ee_write(uint32_t pos, uint8_t *buf, uint16_t len) __reentrant
244 if (pos >= AO_EE_DATA_SIZE || pos + len > AO_EE_DATA_SIZE)
248 /* Compute portion of transfer within
252 this_len = 256 - (uint16_t) this_off;
253 block = (uint16_t) (pos >> 8);
256 if (this_len & 0xff00)
257 ao_panic(AO_PANIC_EE);
259 /* Transfer the data */
260 ao_mutex_get(&ao_ee_mutex); {
264 ao_ee_flush_internal();
267 memcpy(ao_ee_data + this_off, buf, this_len);
268 ao_ee_block_dirty = 1;
269 } ao_mutex_put(&ao_ee_mutex);
271 /* See how much is left */
279 ao_ee_read(uint32_t pos, uint8_t *buf, uint16_t len) __reentrant
285 if (pos >= AO_EE_DATA_SIZE || pos + len > AO_EE_DATA_SIZE)
289 /* Compute portion of transfer within
293 this_len = 256 - (uint16_t) this_off;
294 block = (uint16_t) (pos >> 8);
297 if (this_len & 0xff00)
298 ao_panic(AO_PANIC_EE);
300 /* Transfer the data */
301 ao_mutex_get(&ao_ee_mutex); {
303 memcpy(buf, ao_ee_data + this_off, this_len);
304 } ao_mutex_put(&ao_ee_mutex);
306 /* See how much is left */
314 ao_ee_flush(void) __reentrant
316 ao_mutex_get(&ao_ee_mutex); {
317 ao_ee_flush_internal();
318 } ao_mutex_put(&ao_ee_mutex);
322 * Read/write the config block, which is in
323 * the last block of the ao_eeprom
326 ao_ee_write_config(uint8_t *buf, uint16_t len) __reentrant
328 if (len > AO_EE_BLOCK_SIZE)
330 ao_mutex_get(&ao_ee_mutex); {
331 ao_ee_fill(AO_EE_CONFIG_BLOCK);
332 memcpy(ao_ee_data, buf, len);
333 ao_ee_block_dirty = 1;
334 ao_ee_flush_internal();
335 } ao_mutex_put(&ao_ee_mutex);
340 ao_ee_read_config(uint8_t *buf, uint16_t len) __reentrant
342 if (len > AO_EE_BLOCK_SIZE)
344 ao_mutex_get(&ao_ee_mutex); {
345 ao_ee_fill(AO_EE_CONFIG_BLOCK);
346 memcpy(buf, ao_ee_data, len);
347 } ao_mutex_put(&ao_ee_mutex);
355 __xdata uint16_t block;
359 block = ao_cmd_lex_i;
360 if (ao_cmd_status != ao_cmd_success)
367 ao_cmd_put16((uint16_t) i);
370 ao_ee_read(((uint32_t) block << 8) | i, &b, 1);
380 __xdata uint16_t block;
382 __xdata uint16_t len;
384 __xdata uint32_t addr;
387 block = ao_cmd_lex_i;
390 addr = ((uint32_t) block << 8) | i;
393 if (ao_cmd_status != ao_cmd_success)
397 if (ao_cmd_status != ao_cmd_success)
400 ao_ee_write(addr, &b, 1);
406 __code struct ao_cmds ao_ee_cmds[] = {
407 { 'e', ee_dump, "e <block> Dump a block of EEPROM data" },
408 { 'w', ee_store, "w <block> <start> <len> <data> ... Write data to EEPROM" },
409 { 0, ee_store, NULL },
413 * To initialize the chip, set up the CS line and
421 P1DIR |= (1 << EE_CS_INDEX);
422 P1SEL &= ~(1 << EE_CS_INDEX);
424 /* Set up the USART pin assignment */
425 PERCFG = (PERCFG & ~PERCFG_U0CFG_ALT_MASK) | PERCFG_U0CFG_ALT_2;
427 /* Ensure that USART0 takes precidence over USART1 for pins that
430 P2SEL = (P2SEL & ~P2SEL_PRI3P1_MASK) | P2SEL_PRI3P1_USART0;
432 /* Make the SPI pins be controlled by the USART peripheral */
433 P1SEL |= ((1 << 5) | (1 << 4) | (1 << 3));
436 ao_ee_dma_out_id = ao_dma_alloc(&ao_ee_dma_out_done);
439 ao_ee_dma_in_id = ao_dma_alloc(&ao_ee_dma_in_done);
445 U0CSR = (UxCSR_MODE_SPI | UxCSR_RE | UxCSR_MASTER);
447 /* Set the baud rate and signal parameters
449 * The cc1111 is limited to a 24/8 MHz SPI clock,
450 * while the 25LC1024 is limited to 20MHz. So,
451 * use the 3MHz clock (BAUD_E 17, BAUD_M 0)
454 U0GCR = (UxGCR_CPOL_NEGATIVE |
455 UxGCR_CPHA_FIRST_EDGE |
457 (17 << UxGCR_BAUD_E_SHIFT));
458 ao_cmd_register(&ao_ee_cmds[0]);