2 * Simulator of microcontrollers (regsxa.h)
4 * Copyright (C) 1999,2002 Drotos Daniel, Talker Bt.
6 * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
7 * Other contributors include:
8 * Karl Bongers karl@turbobit.com,
13 /* This file is part of microcontroller simulator: ucsim.
15 UCSIM is free software; you can redistribute it and/or modify
16 it under the terms of the GNU General Public License as published by
17 the Free Software Foundation; either version 2 of the License, or
18 (at your option) any later version.
20 UCSIM is distributed in the hope that it will be useful,
21 but WITHOUT ANY WARRANTY; without even the implied warranty of
22 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 GNU General Public License for more details.
25 You should have received a copy of the GNU General Public License
26 along with UCSIM; see the file COPYING. If not, write to the Free
27 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
31 #ifndef REGSAVR_HEADER
32 #define REGSAVR_HEADER
41 /* macros suck, can we use inline functions instead
42 for the same effect? karl
45 /* direct is a special code space for built-in ram and SFR, 1K size */
46 #ifdef WORDS_BIGENDIAN
47 #define set_word_direct(_index, _value) { \
48 mem_direct[(_index)] = (_value >> 8); \
49 mem_direct[(_index)] = (_value & 0xff); }
51 #define get_word_direct(_index) \
52 ( (mem_direct[(_index)] << 8) | mem_direct[(_index)+1] )
54 #define set_word_direct(_index, _value) { \
55 wmem_direct[(_index) >> 1] = _value; }
56 #define get_word_direct(_index) (wmem_direct[(_index) >> 1] )
59 #define get_byte_direct(_index) (mem_direct[_index])
62 #define store2(addr, val) { ram->set((t_addr) (addr), val & 0xff); \
63 ram->set((t_addr) (addr+1), (val >> 8) & 0xff); }
64 #define store1(addr, val) ram->set((t_addr) (addr), val)
67 #define get1(addr) ram->get((t_addr) (addr))
68 #define get2(addr) (ram->get((t_addr) (addr)) | (ram->get((t_addr) (addr+1)) << 8) )
71 #define getcode1(addr) rom->get((t_addr) (addr))
72 #define getcode2(addr) (rom->get((t_addr) (addr)) | (rom->get((t_addr) (addr+1)) << 8) )
74 /* fetch from opcode code space */
75 #define fetch2() ((fetch() << 8) | fetch())
76 #define fetch1() fetch()
78 /* get a 1 or 2 byte register */
79 #define reg2(_index) get_reg(1, (_index))
80 #define reg1(_index) (unsigned char)get_reg(0, (_index))
82 #define set_byte_direct(_index, _value) { \
83 mem_direct[_index] = _value; \
86 #define set_reg1(_index, _value) { \
87 if ((_index) < 3) { /* banked */ \
88 mem_direct[0x400+(_index)] = _value; \
89 } else { /* non-banked */ \
90 mem_direct[0x400+(_index)] = _value; \
94 #define set_reg2(_index, _value) { \
95 if ((_index) < 3) { /* banked */ \
96 set_word_direct((0x400+_index), _value); \
97 } else { /* non-banked */ \
98 set_word_direct((0x400+_index), _value); \
102 #define set_reg(_word_flag, _index, _value) { \
104 { set_reg2((_index), _value) } \
106 { set_reg1((_index), _value) } \
110 #define get_bit(x) (x)
113 /* R7 mirrors 1 of 2 real SP's */
114 #define set_sp(_value) { \
115 { set_word_direct(0x400+(7*2), _value); } \
118 #define get_sp() ((TYPE_UWORD)(get_word_direct(0x400+(7*2))))
120 // fixme: I don't know where the psw is kept, just want to compile...
121 #define get_psw() ((TYPE_UWORD)(get_word_direct(0x400+(0x80*2))))
122 #define set_psw(_flags) set_word_direct(0x400+(0x80*2), _flags)
125 --------------------------------------------------------------------
129 f: {unused slot(word accessable only) for R8-R15}
130 e: R7h,R7l Stack pointer, ptr to USP(PSW.SM=0), or SSP(PSW.SM=1)
134 below are the banked registers which mirror(B0..B3) depending on
141 Registers are all bit addressable as:
142 2: bx1f,bx1e...b8(R0h) bx17,bx16..bx10(R0l)
143 0: bxf,bxe...b8(R0h) b7,b6..b0(R0l)
145 Memory is little endian:
149 Data word access limited to word boundaries. If non-word address used,
150 then will act as lesser word alignment used(addr b0=0).
151 (note: trigger an exception in simulator if otherwise).
153 Internal memory takes precedence over external memory, unless
156 64K segment memory layout, bank registers used include:
157 DS(data segment) and ES(extra segment) and forms high byte of
158 24 bit address. Stack is in DS, so ES typically used to access
161 SFR(1K direct space) is above normal 1K direct address space(0-3FFH)
162 between 400H to 7FFH.
164 Branch targets must reside on even boundaries
165 (note: trigger an exception in simulator if otherwise).
167 MOVC instructions use either PC(SSEL.4=0) or CS(SSEL.4=1) register.
170 PCON, SCR, SSEL, PSWH, PSWL, CS, ES, DS
172 400H-43FH are bit or byte accesable.
173 400H-5FFH is for built in SFR hardware.
174 600H-7FFH is for external SFR hardware access.
175 SFR access is independent of segment regs.
176 SFR inacessable from indirect addressing(must use direct-addr in opcodes).
180 100H to 1ffH - 20h to 3fH(direct ram, relative to DS)
181 200H to 3FFH - 400H to 43FH(on board SFRs)
183 PSW Flags: Carry(C), Aux Carry(AC), Overflow(V), Negative(N), Zero(Z).
185 Stack ptr is pre-decremented, followed by load(word operation),
186 default SPs are set to 100H. So first PUSH would go to FEH-FFH.
197 #define BIT_ALL (BIT_C | BIT_AC | BIT_V | BIT_N | BIT_Z)
200 /* End of xa.src/regsxa.h */