2 * Simulator of microcontrollers (inst.cc)
4 * Copyright (C) 1999,2002 Drotos Daniel, Talker Bt.
6 * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
7 * Other contributors include:
8 * Karl Bongers karl@turbobit.com,
13 /* This file is part of microcontroller simulator: ucsim.
15 UCSIM is free software; you can redistribute it and/or modify
16 it under the terms of the GNU General Public License as published by
17 the Free Software Foundation; either version 2 of the License, or
18 (at your option) any later version.
20 UCSIM is distributed in the hope that it will be useful,
21 but WITHOUT ANY WARRANTY; without even the implied warranty of
22 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 GNU General Public License for more details.
25 You should have received a copy of the GNU General Public License
26 along with UCSIM; see the file COPYING. If not, write to the Free
27 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
39 cl_xa::get_reg(int word_flag, unsigned int index)
41 //if (index < 3) { /* banked */
43 // return get_word_direct(0x400+index);
45 // return mem_direct[0x400+index];
46 //} else { /* non-banked */
48 return get_word_direct(0x400+index);
50 return mem_direct[0x400+index];
55 cl_xa::inst_NOP(uint code, int operands)
60 #define RI_F0 ((code >> 4) & 0xf)
61 #define RI_70 ((code >> 4) & 0x7)
62 #define RI_0F (code & 0xf)
63 #define RI_07 (code & 0x7)
66 cl_xa::inst_ADD(uint code, int operands)
72 #include "inst_gen.cc"
78 cl_xa::inst_ADDC(uint code, int operands)
84 #include "inst_gen.cc"
90 cl_xa::inst_SUB(uint code, int operands)
96 #include "inst_gen.cc"
101 cl_xa::inst_SUBB(uint code, int operands)
107 #include "inst_gen.cc"
112 cl_xa::inst_CMP(uint code, int operands)
118 #include "inst_gen.cc"
122 cl_xa::inst_AND(uint code, int operands)
128 #include "inst_gen.cc"
132 cl_xa::inst_OR(uint code, int operands)
138 #include "inst_gen.cc"
142 cl_xa::inst_XOR(uint code, int operands)
148 #include "inst_gen.cc"
152 cl_xa::inst_ADDS(uint code, int operands)
157 cl_xa::inst_NEG(uint code, int operands)
162 cl_xa::inst_SEXT(uint code, int operands)
167 cl_xa::inst_MUL(uint code, int operands)
172 cl_xa::inst_DIV(uint code, int operands)
177 cl_xa::inst_DA(uint code, int operands)
182 cl_xa::inst_ASL(uint code, int operands)
187 cl_xa::inst_ASR(uint code, int operands)
192 cl_xa::inst_LEA(uint code, int operands)
197 cl_xa::inst_CPL(uint code, int operands)
202 cl_xa::inst_LSR(uint code, int operands)
207 cl_xa::inst_NORM(uint code, int operands)
212 cl_xa::inst_RL(uint code, int operands)
217 cl_xa::inst_RLC(uint code, int operands)
222 cl_xa::inst_RR(uint code, int operands)
227 cl_xa::inst_RRC(uint code, int operands)
232 cl_xa::inst_MOVS(uint code, int operands)
237 cl_xa::inst_MOVC(uint code, int operands)
242 short srcreg = reg2(RI_07);
243 if (code & 0x0800) { /* word op */
256 if (operands == REG_IREGINC) {
257 set_reg2(RI_07, srcreg+1);
266 cl_xa::inst_MOVX(uint code, int operands)
271 cl_xa::inst_PUSH(uint code, int operands)
277 unsigned short direct_addr = ((operands & 0x7) << 8) | fetch();
281 if (code & 0x0800) { /* word op */
282 store2( sp, get_word_direct(direct_addr));
284 store2( sp, get_byte_direct(direct_addr));
291 unsigned char rlist = fetch();
292 rlist = rlist; //shutup compiler
299 cl_xa::inst_POP(uint code, int operands)
305 unsigned short direct_addr = ((operands & 0x7) << 8) | fetch();
308 if (code & 0x0800) { /* word op */
309 set_word_direct(direct_addr, get2(sp) );
311 set_byte_direct(direct_addr, get2(sp) & 0xff );
319 unsigned char rlist = fetch();
320 rlist = rlist; //shutup compiler
326 cl_xa::inst_XCH(uint code, int operands)
331 cl_xa::inst_SETB(uint code, int operands)
333 unsigned short bitAddr = (code&0x03 << 8) + fetch();
339 cl_xa::inst_CLR(uint code, int operands)
341 unsigned short bitAddr = (code&0x03 << 8) + fetch();
347 cl_xa::inst_MOV(uint code, int operands)
353 #include "inst_gen.cc"
357 cl_xa::inst_ANL(uint code, int operands)
362 cl_xa::inst_ORL(uint code, int operands)
367 cl_xa::inst_BEQ(uint code, int operands)
369 short jmpAddr = fetch1()*2;
370 if (get_psw() & BIT_Z) {
371 PC=(PC+jmpAddr)&0xfffffffe;
376 cl_xa::inst_BR(uint code, int operands)
378 short jmpAddr = fetch1()*2;
379 PC=(PC+jmpAddr)&0xfffffffe;
383 cl_xa::inst_JMP(uint code, int operands)
390 jmpAddr = (signed short)fetch2()*2;
391 PC = (PC + jmpAddr) & 0xfffffffe;
396 PC |= (reg2(RI_07) & 0xfffe); /* word aligned */
398 /* fixme 2 more... */
403 cl_xa::inst_CALL(uint code, int operands)
411 jmpaddr = (signed short)fetch2();
415 store2(sp+2, 0); /* segment(not sure about ordering...) */
417 PC = (PC + jmpaddr) & 0xfffffffe;
425 #if 0 // only in huge model
428 jmpaddr = reg2(RI_07);
430 PC = (PC + jmpaddr) & 0xfffffffe;
433 /* fixme 2 more... */ /* johan: which ones? */
438 cl_xa::inst_RET(uint code, int operands)
440 unsigned int retaddr;
444 #if 0 // only in huge model
445 retaddr |= get2(sp+2) << 16;
452 cl_xa::inst_Bcc(uint code, int operands)
457 cl_xa::inst_JB(uint code, int operands)
459 short bitAddr=((code&0x3)<<8) + fetch1();
460 short jmpAddr = (fetch1() * 2);
461 if (get_bit(bitAddr)) {
462 PC = (PC+jmpAddr)&0xfffffe;
467 cl_xa::inst_JNB(uint code, int operands)
469 short bitAddr=((code&0x3)<<8) + fetch1();
470 short jmpAddr = (fetch1() * 2);
471 if (!get_bit(bitAddr)) {
472 PC = (PC+jmpAddr)&0xfffffe;
478 cl_xa::inst_CJNE(uint code, int operands)
481 case REG_DIRECT_REL8:
484 if (code & 0x800) { // word op
486 int src = get_word_direct( ((code & 0x7)<<4) | fetch1());
487 int addr = (fetch1() * 2);
488 int dst = reg2(RI_F0);
491 flags &= ~BIT_ALL; /* clear these bits */
493 if (result == 0) flags |= BIT_Z;
494 if (result > 0xffff) flags |= BIT_C;
495 if (dst < src) flags |= BIT_N;
501 int src = get_byte_direct( ((code & 0x7)<<4) | fetch1());
502 int addr = (fetch1() * 2);
503 int dst = reg1(RI_F0);
506 flags &= ~BIT_ALL; /* clear these bits */
508 if (result == 0) flags |= BIT_Z;
509 if (result > 0xff) flags |= BIT_C;
510 if (dst < src) flags |= BIT_N;
520 int daddr = ((code & 0x7) << 8) | fetch();
521 int addr = fetch() * 2;
523 if (code & 0x800) { // word op
524 unsigned short tmp = get_word_direct(daddr)-1;
525 set_word_direct(daddr, tmp);
529 unsigned char tmp = get_word_direct(daddr)-1;
530 set_byte_direct(daddr, tmp);
540 cl_xa::inst_DJNZ(uint code, int operands)
545 int addr = (fetch1() * 2);
546 if (code & 0x800) { // word op
547 unsigned short tmp = mov2(0, reg2(RI_F0)-1);
548 set_reg2(RI_F0, tmp);
552 unsigned char tmp = mov1(0, reg1(RI_F0)-1);
553 set_reg1(RI_F0, tmp);
562 int daddr = ((code & 0x7) << 8) | fetch();
563 int addr = fetch() * 2;
565 if (code & 0x800) { // word op
566 unsigned short tmp = get_word_direct(daddr)-1;
567 set_word_direct(daddr, tmp);
571 unsigned char tmp = get_word_direct(daddr)-1;
572 set_byte_direct(daddr, tmp);
583 cl_xa::inst_JZ(uint code, int operands)
585 /* reg1(8) = R4L, is ACC for MCS51 compatiblility */
586 short saddr = (fetch1() * 2);
593 cl_xa::inst_JNZ(uint code, int operands)
595 short saddr = (fetch1() * 2);
596 /* reg1(8) = R4L, is ACC for MCS51 compatiblility */
598 PC = (PC + saddr) & 0xfffffe;
603 cl_xa::inst_BKPT(uint code, int operands)
608 cl_xa::inst_TRAP(uint code, int operands)
613 cl_xa::inst_RESET(uint code, int operands)
619 /* End of xa.src/inst.cc */