3 * pic18f6680.h - PIC18F6680 Device Library Header
5 * This file is part of the GNU PIC Library.
8 * The GNU PIC Library is maintained by,
9 * Vangelis Rokas <vrokas@otenet.gr>
15 #ifndef __PIC18F6680_H__
16 #define __PIC18F6680_H__
18 extern __sfr __at (0xf00) RXF0SIDH;
19 extern __sfr __at (0xf01) RXF0SIDL;
33 extern volatile __RXF0SIDLbits_t __at (0xf01) RXF0SIDLbits;
35 extern __sfr __at (0xf02) RXF0EIDH;
36 extern __sfr __at (0xf03) RXF0EIDL;
37 extern __sfr __at (0xf04) RXF1SIDH;
38 extern __sfr __at (0xf05) RXF1SIDL;
52 extern volatile __RXF1SIDLbits_t __at (0xf05) RXF1SIDLbits;
54 extern __sfr __at (0xf06) RXF1EIDH;
55 extern __sfr __at (0xf07) RXF1EIDL;
56 extern __sfr __at (0xf08) RXF2SIDH;
57 extern __sfr __at (0xf09) RXF2SIDL;
58 extern __sfr __at (0xf0a) RXF2EIDH;
59 extern __sfr __at (0xf0b) RXF2EIDL;
73 extern volatile __RXF2EIDLbits_t __at (0xf0b) RXF2EIDLbits;
75 extern __sfr __at (0xf0c) RXF3SIDH;
76 extern __sfr __at (0xf0d) RXF3SIDL;
90 extern volatile __RXF3SIDLbits_t __at (0xf0d) RXF3SIDLbits;
92 extern __sfr __at (0xf0e) RXF3EIDH;
93 extern __sfr __at (0xf0f) RXF3EIDL;
94 extern __sfr __at (0xf10) RXF4SIDH;
95 extern __sfr __at (0xf11) RXF4SIDL;
109 extern volatile __RXF4SIDLbits_t __at (0xf11) RXF4SIDLbits;
111 extern __sfr __at (0xf12) RXF4EIDH;
112 extern __sfr __at (0xf13) RXF4EIDL;
113 extern __sfr __at (0xf14) RXF5SIDH;
114 extern __sfr __at (0xf15) RXF5SIDL;
128 extern volatile __RXF5SIDLbits_t __at (0xf15) RXF5SIDLbits;
130 extern __sfr __at (0xf16) RXF5EIDH;
131 extern __sfr __at (0xf17) RXF5EIDL;
132 extern __sfr __at (0xf18) RXM0SIDH;
133 extern __sfr __at (0xf19) RXM0SIDL;
147 extern volatile __RXM0SIDLbits_t __at (0xf19) RXM0SIDLbits;
149 extern __sfr __at (0xf1a) RXM0EIDH;
150 extern __sfr __at (0xf1b) RXM0EIDL;
151 extern __sfr __at (0xf1c) RXM1SIDH;
152 extern __sfr __at (0xf1d) RXM1SIDL;
166 extern volatile __RXM1SIDLbits_t __at (0xf1d) RXM1SIDLbits;
168 extern __sfr __at (0xf1e) RXM1EIDH;
169 extern __sfr __at (0xf1f) RXM1EIDL;
170 extern __sfr __at (0xf20) TXB2CON;
184 extern volatile __TXB2CONbits_t __at (0xf20) TXB2CONbits;
186 extern __sfr __at (0xf21) TXB2SIDH;
187 extern __sfr __at (0xf22) TXB2SIDL;
201 extern volatile __TXB2SIDLbits_t __at (0xf22) TXB2SIDLbits;
203 extern __sfr __at (0xf23) TXB2EIDH;
204 extern __sfr __at (0xf24) TXB2EIDL;
205 extern __sfr __at (0xf25) TXB2DLC;
219 extern volatile __TXB2DLCbits_t __at (0xf25) TXB2DLCbits;
221 extern __sfr __at (0xf26) TXB2D0;
222 extern __sfr __at (0xf27) TXB2D1;
223 extern __sfr __at (0xf28) TXB2D2;
224 extern __sfr __at (0xf29) TXB2D3;
225 extern __sfr __at (0xf2a) TXB2D4;
226 extern __sfr __at (0xf2b) TXB2D5;
227 extern __sfr __at (0xf2c) TXB2D6;
228 extern __sfr __at (0xf2d) TXB2D7;
229 extern __sfr __at (0xf2e) CANSTATRO3;
230 extern __sfr __at (0xf30) TXB1CON;
244 extern volatile __TXB1CONbits_t __at (0xf30) TXB1CONbits;
246 extern __sfr __at (0xf31) TXB1SIDH;
247 extern __sfr __at (0xf32) TXB1SIDL;
261 extern volatile __TXB1SIDLbits_t __at (0xf32) TXB1SIDLbits;
263 extern __sfr __at (0xf33) TXB1EIDH;
264 extern __sfr __at (0xf34) TXB1EIDL;
265 extern __sfr __at (0xf35) TXB1DLC;
279 extern volatile __TXB1DLCbits_t __at (0xf35) TXB1DLCbits;
281 extern __sfr __at (0xf36) TXB1D0;
282 extern __sfr __at (0xf37) TXB1D1;
283 extern __sfr __at (0xf38) TXB1D2;
284 extern __sfr __at (0xf39) TXB1D3;
285 extern __sfr __at (0xf3a) TXB1D4;
286 extern __sfr __at (0xf3b) TXB1D5;
287 extern __sfr __at (0xf3c) TXB1D6;
288 extern __sfr __at (0xf3d) TXB1D7;
289 extern __sfr __at (0xf3e) CANSTATRO2;
290 extern __sfr __at (0xf40) TXB0CON;
304 extern volatile __TXB0CONbits_t __at (0xf40) TXB0CONbits;
306 extern __sfr __at (0xf41) TXB0SIDH;
307 extern __sfr __at (0xf42) TXB0SIDL;
308 extern __sfr __at (0xf43) TXB0EIDH;
309 extern __sfr __at (0xf44) TXB0EIDL;
310 extern __sfr __at (0xf45) TXB0DLC;
324 extern volatile __TXB0DLCbits_t __at (0xf45) TXB0DLCbits;
326 extern __sfr __at (0xf46) TXB0D0;
327 extern __sfr __at (0xf47) TXB0D1;
328 extern __sfr __at (0xf48) TXB0D2;
329 extern __sfr __at (0xf49) TXB0D3;
330 extern __sfr __at (0xf4a) TXB0D4;
331 extern __sfr __at (0xf4b) TXB0D5;
332 extern __sfr __at (0xf4c) TXB0D6;
333 extern __sfr __at (0xf4d) TXB0D7;
334 extern __sfr __at (0xf4e) CANSTATRO1;
335 extern __sfr __at (0xf50) RXB1CON;
349 extern volatile __RXB1CONbits_t __at (0xf50) RXB1CONbits;
351 extern __sfr __at (0xf51) RXB1SIDH;
352 extern __sfr __at (0xf52) RXB1SIDL;
366 extern volatile __RXB1SIDLbits_t __at (0xf52) RXB1SIDLbits;
368 extern __sfr __at (0xf53) RXB1EIDH;
369 extern __sfr __at (0xf54) RXB1EIDL;
370 extern __sfr __at (0xf55) RXB1DLC;
384 extern volatile __RXB1DLCbits_t __at (0xf55) RXB1DLCbits;
386 extern __sfr __at (0xf56) RXB1D0;
387 extern __sfr __at (0xf57) RXB1D1;
388 extern __sfr __at (0xf58) RXB1D2;
389 extern __sfr __at (0xf59) RXB1D3;
390 extern __sfr __at (0xf5a) RXB1D4;
391 extern __sfr __at (0xf5b) RXB1D5;
392 extern __sfr __at (0xf5c) RXB1D6;
393 extern __sfr __at (0xf5d) RXB1D7;
394 extern __sfr __at (0xf5e) CANSTATRO0;
395 extern __sfr __at (0xf60) RXB0CON;
409 extern volatile __RXB0CONbits_t __at (0xf60) RXB0CONbits;
411 extern __sfr __at (0xf61) RXB0SIDH;
412 extern __sfr __at (0xf62) RXB0SIDL;
426 extern volatile __RXB0SIDLbits_t __at (0xf62) RXB0SIDLbits;
428 extern __sfr __at (0xf63) RXB0EIDH;
429 extern __sfr __at (0xf64) RXB0EIDL;
430 extern __sfr __at (0xf65) RXB0DLC;
431 extern __sfr __at (0xf66) RXB0D0;
432 extern __sfr __at (0xf67) RXB0D1;
433 extern __sfr __at (0xf68) RXB0D2;
434 extern __sfr __at (0xf69) RXB0D3;
435 extern __sfr __at (0xf6a) RXB0D4;
436 extern __sfr __at (0xf6b) RXB0D5;
437 extern __sfr __at (0xf6c) RXB0D6;
438 extern __sfr __at (0xf6d) RXB0D7;
439 extern __sfr __at (0xf6e) CANSTAT;
453 extern volatile __CANSTATbits_t __at (0xf6e) CANSTATbits;
455 extern __sfr __at (0xf6f) CANCON;
469 extern volatile __CANCONbits_t __at (0xf6f) CANCONbits;
471 extern __sfr __at (0xf70) BRGCON1;
485 extern volatile __BRGCON1bits_t __at (0xf70) BRGCON1bits;
487 extern __sfr __at (0xf71) BRGCON2;
501 extern volatile __BRGCON2bits_t __at (0xf71) BRGCON2bits;
503 extern __sfr __at (0xf72) BRGCON3;
517 extern volatile __BRGCON3bits_t __at (0xf72) BRGCON3bits;
519 extern __sfr __at (0xf73) CIOCON;
533 extern volatile __CIOCONbits_t __at (0xf73) CIOCONbits;
535 extern __sfr __at (0xf74) COMSTAT;
549 extern volatile __COMSTATbits_t __at (0xf74) COMSTATbits;
551 extern __sfr __at (0xf75) RXERRCNT;
565 extern volatile __RXERRCNTbits_t __at (0xf75) RXERRCNTbits;
567 extern __sfr __at (0xf76) TXERRCNT;
581 extern volatile __TXERRCNTbits_t __at (0xf76) TXERRCNTbits;
583 extern __sfr __at (0xf80) PORTA;
630 extern volatile __PORTAbits_t __at (0xf80) PORTAbits;
632 extern __sfr __at (0xf81) PORTB;
657 extern volatile __PORTBbits_t __at (0xf81) PORTBbits;
659 extern __sfr __at (0xf82) PORTC;
695 extern volatile __PORTCbits_t __at (0xf82) PORTCbits;
697 extern __sfr __at (0xf83) PORTD;
722 extern volatile __PORTDbits_t __at (0xf83) PORTDbits;
724 extern __sfr __at (0xf84) PORTE;
760 extern volatile __PORTEbits_t __at (0xf84) PORTEbits;
762 extern __sfr __at (0xf85) PORTF;
776 extern volatile __PORTFbits_t __at (0xf85) PORTFbits;
778 extern __sfr __at (0xf86) PORTG;
792 extern volatile __PORTGbits_t __at (0xf86) PORTGbits;
794 extern __sfr __at (0xf89) LATA;
808 extern volatile __LATAbits_t __at (0xf89) LATAbits;
810 extern __sfr __at (0xf8a) LATB;
824 extern volatile __LATBbits_t __at (0xf8a) LATBbits;
826 extern __sfr __at (0xf8b) LATC;
840 extern volatile __LATCbits_t __at (0xf8b) LATCbits;
842 extern __sfr __at (0xf8c) LATD;
856 extern volatile __LATDbits_t __at (0xf8c) LATDbits;
858 extern __sfr __at (0xf8d) LATE;
872 extern volatile __LATEbits_t __at (0xf8d) LATEbits;
874 extern __sfr __at (0xf8e) LATF;
888 extern volatile __LATFbits_t __at (0xf8e) LATFbits;
890 extern __sfr __at (0xf8f) LATG;
904 extern volatile __LATGbits_t __at (0xf8f) LATGbits;
906 extern __sfr __at (0xf92) TRISA;
920 extern volatile __TRISAbits_t __at (0xf92) TRISAbits;
922 extern __sfr __at (0xf93) TRISB;
936 extern volatile __TRISBbits_t __at (0xf93) TRISBbits;
938 extern __sfr __at (0xf94) TRISC;
952 extern volatile __TRISCbits_t __at (0xf94) TRISCbits;
954 extern __sfr __at (0xf95) TRISD;
968 extern volatile __TRISDbits_t __at (0xf95) TRISDbits;
970 extern __sfr __at (0xf96) TRISE;
984 extern volatile __TRISEbits_t __at (0xf96) TRISEbits;
986 extern __sfr __at (0xf97) TRISF;
1000 extern volatile __TRISFbits_t __at (0xf97) TRISFbits;
1002 extern __sfr __at (0xf98) TRISG;
1016 extern volatile __TRISGbits_t __at (0xf98) TRISGbits;
1018 extern __sfr __at (0xf9d) PIE1;
1032 extern volatile __PIE1bits_t __at (0xf9d) PIE1bits;
1034 extern __sfr __at (0xf9e) PIR1;
1048 extern volatile __PIR1bits_t __at (0xf9e) PIR1bits;
1050 extern __sfr __at (0xf9f) IPR1;
1064 extern volatile __IPR1bits_t __at (0xf9f) IPR1bits;
1066 extern __sfr __at (0xfa0) PIE2;
1080 extern volatile __PIE2bits_t __at (0xfa0) PIE2bits;
1082 extern __sfr __at (0xfa1) PIR2;
1096 extern volatile __PIR2bits_t __at (0xfa1) PIR2bits;
1098 extern __sfr __at (0xfa2) IPR2;
1112 extern volatile __IPR2bits_t __at (0xfa2) IPR2bits;
1114 extern __sfr __at (0xfa3) PIE3;
1128 extern volatile __PIE3bits_t __at (0xfa3) PIE3bits;
1130 extern __sfr __at (0xfa4) PIR3;
1144 extern volatile __PIR3bits_t __at (0xfa4) PIR3bits;
1146 extern __sfr __at (0xfa5) IPR3;
1160 extern volatile __IPR3bits_t __at (0xfa5) IPR3bits;
1162 extern __sfr __at (0xfa6) EECON1;
1176 extern volatile __EECON1bits_t __at (0xfa6) EECON1bits;
1178 extern __sfr __at (0xfa7) EECON2;
1179 extern __sfr __at (0xfa8) EEDATA;
1180 extern __sfr __at (0xfa9) EEADR;
1181 extern __sfr __at (0xfaa) EEADRH;
1182 extern __sfr __at (0xfab) RCSTA;
1196 extern volatile __RCSTAbits_t __at (0xfab) RCSTAbits;
1198 extern __sfr __at (0xfac) TXSTA;
1212 extern volatile __TXSTAbits_t __at (0xfac) TXSTAbits;
1214 extern __sfr __at (0xfad) TXREG;
1215 extern __sfr __at (0xfae) RCREG;
1216 extern __sfr __at (0xfaf) SPBRG;
1217 extern __sfr __at (0xfb0) PSPCON;
1231 extern volatile __PSPCONbits_t __at (0xfb0) PSPCONbits;
1233 extern __sfr __at (0xfb1) T3CON;
1247 extern volatile __T3CONbits_t __at (0xfb1) T3CONbits;
1249 extern __sfr __at (0xfb2) TMR3L;
1250 extern __sfr __at (0xfb3) TMR3H;
1251 extern __sfr __at (0xfb4) CMCON;
1265 extern volatile __CMCONbits_t __at (0xfb4) CMCONbits;
1267 extern __sfr __at (0xfb5) CVRCON;
1281 extern volatile __CVRCONbits_t __at (0xfb5) CVRCONbits;
1283 extern __sfr __at (0xfb6) ECCPAS;
1297 extern volatile __ECCPASbits_t __at (0xfb6) ECCPASbits;
1299 extern __sfr __at (0xfb7) ECCP1DEL;
1313 extern volatile __ECCP1DELbits_t __at (0xfb7) ECCP1DELbits;
1315 extern __sfr __at (0xfba) ECCP1CON;
1329 extern volatile __ECCP1CONbits_t __at (0xfba) ECCP1CONbits;
1331 extern __sfr __at (0xfba) CCP2CON;
1345 extern volatile __CCP2CONbits_t __at (0xfba) CCP2CONbits;
1347 extern __sfr __at (0xfbb) ECCPR1L;
1348 extern __sfr __at (0xfbb) CCPR2L;
1349 extern __sfr __at (0xfbc) ECCPR1H;
1350 extern __sfr __at (0xfbc) CCPR2H;
1351 extern __sfr __at (0xfc0) ADCON2;
1365 extern volatile __ADCON2bits_t __at (0xfc0) ADCON2bits;
1367 extern __sfr __at (0xfc1) ADCON1;
1381 extern volatile __ADCON1bits_t __at (0xfc1) ADCON1bits;
1383 extern __sfr __at (0xfc2) ADCON0;
1397 extern volatile __ADCON0bits_t __at (0xfc2) ADCON0bits;
1399 extern __sfr __at (0xfc3) ADRESL;
1400 extern __sfr __at (0xfc4) ADRESH;
1401 extern __sfr __at (0xfc5) SSPCON2;
1415 extern volatile __SSPCON2bits_t __at (0xfc5) SSPCON2bits;
1417 extern __sfr __at (0xfc6) SSPCON1;
1431 extern volatile __SSPCON1bits_t __at (0xfc6) SSPCON1bits;
1433 extern __sfr __at (0xfc7) SSPSTAT;
1447 extern volatile __SSPSTATbits_t __at (0xfc7) SSPSTATbits;
1449 extern __sfr __at (0xfc8) SSPADD;
1450 extern __sfr __at (0xfc9) SSPBUF;
1451 extern __sfr __at (0xfca) T2CON;
1465 extern volatile __T2CONbits_t __at (0xfca) T2CONbits;
1467 extern __sfr __at (0xfcb) PR2;
1468 extern __sfr __at (0xfcc) TMR2;
1469 extern __sfr __at (0xfcd) T1CON;
1474 unsigned NOT_T1SYNC:1;
1483 extern volatile __T1CONbits_t __at (0xfcd) T1CONbits;
1485 extern __sfr __at (0xfce) TMR1L;
1486 extern __sfr __at (0xfcf) TMR1H;
1487 extern __sfr __at (0xfd0) RCON;
1501 extern volatile __RCONbits_t __at (0xfd0) RCONbits;
1503 extern __sfr __at (0xfd1) WDTCON;
1528 extern volatile __WDTCONbits_t __at (0xfd1) WDTCONbits;
1530 extern __sfr __at (0xfd2) LVDCON;
1555 extern volatile __LVDCONbits_t __at (0xfd2) LVDCONbits;
1557 extern __sfr __at (0xfd3) OSCCON;
1571 extern volatile __OSCCONbits_t __at (0xfd3) OSCCONbits;
1573 extern __sfr __at (0xfd5) T0CON;
1574 extern __sfr __at (0xfd6) TMR0L;
1575 extern __sfr __at (0xfd7) TMR0H;
1576 extern __sfr __at (0xfd8) STATUS;
1590 extern volatile __STATUSbits_t __at (0xfd8) STATUSbits;
1592 extern __sfr __at (0xfd9) FSR2L;
1593 extern __sfr __at (0xfda) FSR2H;
1594 extern __sfr __at (0xfdb) PLUSW2;
1595 extern __sfr __at (0xfdc) PREINC2;
1596 extern __sfr __at (0xfdd) POSTDEC2;
1597 extern __sfr __at (0xfde) POSTINC2;
1598 extern __sfr __at (0xfdf) INDF2;
1599 extern __sfr __at (0xfe0) BSR;
1600 extern __sfr __at (0xfe1) FSR1L;
1601 extern __sfr __at (0xfe2) FSR1H;
1602 extern __sfr __at (0xfe3) PLUSW1;
1603 extern __sfr __at (0xfe4) PREINC1;
1604 extern __sfr __at (0xfe5) POSTDEC1;
1605 extern __sfr __at (0xfe6) POSTINC1;
1606 extern __sfr __at (0xfe7) INDF1;
1607 extern __sfr __at (0xfe8) WREG;
1608 extern __sfr __at (0xfe9) FSR0L;
1609 extern __sfr __at (0xfea) FSR0H;
1610 extern __sfr __at (0xfeb) PLUSW0;
1611 extern __sfr __at (0xfec) PREINC0;
1612 extern __sfr __at (0xfed) POSTDEC0;
1613 extern __sfr __at (0xfee) POSTINC0;
1614 extern __sfr __at (0xfef) INDF0;
1615 extern __sfr __at (0xff0) INTCON3;
1640 extern volatile __INTCON3bits_t __at (0xff0) INTCON3bits;
1642 extern __sfr __at (0xff1) INTCON2;
1656 extern volatile __INTCON2bits_t __at (0xff1) INTCON2bits;
1658 extern __sfr __at (0xff2) INTCON;
1672 extern volatile __INTCONbits_t __at (0xff2) INTCONbits;
1674 extern __sfr __at (0xff3) PRODL;
1675 extern __sfr __at (0xff4) PRODH;
1676 extern __sfr __at (0xff5) TABLAT;
1677 extern __sfr __at (0xff6) TBLPTRL;
1678 extern __sfr __at (0xff7) TBLPTRH;
1679 extern __sfr __at (0xff8) TBLPTRU;
1680 extern __sfr __at (0xff9) PCL;
1681 extern __sfr __at (0xffa) PCLATH;
1682 extern __sfr __at (0xffb) PCLATU;
1683 extern __sfr __at (0xffc) STKPTR;
1697 extern volatile __STKPTRbits_t __at (0xffc) STKPTRbits;
1699 extern __sfr __at (0xffd) TOSL;
1700 extern __sfr __at (0xffe) TOSH;
1701 extern __sfr __at (0xfff) TOSU;
1704 /* Configuration registers locations */
1705 #define __CONFIG1H 0x300001
1706 #define __CONFIG2L 0x300002
1707 #define __CONFIG2H 0x300003
1708 #define __CONFIG3H 0x300005
1709 #define __CONFIG4L 0x300006
1710 #define __CONFIG5L 0x300008
1711 #define __CONFIG5H 0x300009
1712 #define __CONFIG6L 0x30000A
1713 #define __CONFIG6H 0x30000B
1714 #define __CONFIG7L 0x30000C
1715 #define __CONFIG7H 0x30000D
1719 /* Oscillator 1H options */
1720 #define _OSC_RC_CLKOUT_1H 0xFF /* RC-CLKOUT on RA6 */
1721 #define _OSC_HS_SOFTWARE_1H 0xFE /* HS-Software enabled PLL */
1722 #define _OSC_EC_CLKOUT_Software_nabld_PLL_1H 0xFD /* EC-CLKOUT on RA6,Software_enabled_PLL */
1723 #define _OSC_EC_CLKOUT_PLL_enabld_frq_4xFosc1_1H 0xFC /* EC-CLKOUT on RA6,PLL_enabled_freq_4xFosc1 */
1724 #define _OSC_EXT_Port_on_RA6_1H 0xF7 /* EXT RC-Port_on_RA6 */
1725 #define _OSC_HS_PLL_1H 0xF6 /* HS-PLL enabled freq=4xFosc1 */
1726 #define _OSC_EC_PORT_1H 0xF5 /* EC-Port on RA6 */
1727 #define _OSC_EC_CLKOUT__1H 0xF4 /* EC-CLKOUT on RA6 */
1728 #define _OSC_EXT_CLKOUT_on_RA6_1H 0xF3 /* EXT RC-CLKOUT_on_RA6 */
1729 #define _OSC_HS_1H 0xF2 /* HS */
1730 #define _OSC_XT_1H 0xF1 /* XT */
1731 #define _OSC_LP_1H 0xF0 /* LP */
1733 /* Low Power System Clock Timer1 Enable 1H options */
1734 #define _OSCSEN_ON_1H 0xDF /* Enabled */
1735 #define _OSCSEN_OFF_1H 0xFF /* Disabled */
1737 /* Power Up Timer 2L options */
1738 #define _PUT_OFF_2L 0xFF /* Disabled */
1739 #define _PUT_ON_2L 0xFE /* Enabled */
1741 /* Brown Out Detect 2L options */
1742 #define _BODEN_ON_2L 0xFF /* Enabled */
1743 #define _BODEN_OFF_2L 0xFD /* Disabled */
1745 /* Brown Out Voltage 2L options */
1746 #define _BODENV_2_0V_2L 0xFF /* 2.0V */
1747 #define _BODENV_2_7V_2L 0xFB /* 2.7V */
1748 #define _BODENV_4_2V_2L 0xF7 /* 4.2V */
1749 #define _BODENV_4_5V_2L 0xF3 /* 4.5V */
1751 /* Watchdog Timer 2H options */
1752 #define _WDT_ON_2H 0xFF /* Enabled */
1753 #define _WDT_DISABLED_CONTROLLED_2H 0xFE /* Disabled-Controlled by SWDTEN bit */
1755 /* Watchdog Postscaler 2H options */
1756 #define _WDTPS_1_32768_2H 0xFF /* 1:32768 */
1757 #define _WDTPS_1_16384_2H 0xFD /* 1:16384 */
1758 #define _WDTPS_1_8192_2H 0xFB /* 1:8192 */
1759 #define _WDTPS_1_4096_2H 0xF9 /* 1:4096 */
1760 #define _WDTPS_1_2048_2H 0xF7 /* 1:2048 */
1761 #define _WDTPS_1_1024_2H 0xF5 /* 1:1024 */
1762 #define _WDTPS_1_512_2H 0xF3 /* 1:512 */
1763 #define _WDTPS_1_256_2H 0xF1 /* 1:256 */
1764 #define _WDTPS_1_128_2H 0xEF /* 1:128 */
1765 #define _WDTPS_1_64_2H 0xED /* 1:64 */
1766 #define _WDTPS_1_32_2H 0xEB /* 1:32 */
1767 #define _WDTPS_1_16_2H 0xE9 /* 1:16 */
1768 #define _WDTPS_1_8_2H 0xE7 /* 1:8 */
1769 #define _WDTPS_1_4_2H 0xE5 /* 1:4 */
1770 #define _WDTPS_1_2_2H 0xE3 /* 1:2 */
1771 #define _WDTPS_1_1_2H 0xE1 /* 1:1 */
1773 /* CCP2 Mux 3H options */
1774 #define _CCP2MUX_RC1_3H 0xFF /* RC1 */
1775 #define _CCP2MUX_RB3_3H 0xFE /* RB3 */
1777 /* ECCP Mux 3H options */
1778 #define _ECCPMX_ECCP1_E6E3_3H 0xFF /* ECCP1 and ECCP6 are muxed onto RE6 through RE3 */
1779 #define _ECCPMX_ECCP1_H7H4_3H 0xFD /* ECCP1 and ECCP6 are muxed onto RH7 through RH4 */
1781 /* MCLR enable 3H options */
1782 #define _MCLRE_MCLR_Enabled_RE3_Disabled_3H 0xFF /* MCLR Enabled_RE3_Disabled */
1783 #define _MCLRE_MCLR_Disabled_RE3_Enabled_3H 0x7F /* MCLR Disabled__RE3_Enabled */
1785 /* Stack Overflow Reset 4L options */
1786 #define _STVR_ON_4L 0xFF /* Enabled */
1787 #define _STVR_OFF_4L 0xFE /* Disabled */
1789 /* Low Voltage Program 4L options */
1790 #define _LVP_ON_4L 0xFF /* Enabled */
1791 #define _LVP_OFF_4L 0xFB /* Disabled */
1793 /* Background Debug 4L options */
1794 #define _BACKBUG_OFF_4L 0xFF /* Disabled */
1795 #define _BACKBUG_ON_4L 0x7F /* Enabled */
1797 /* Code Protect 000800-0003FFF 5L options */
1798 #define _CP_0_OFF_5L 0xFF /* Disabled */
1799 #define _CP_0_ON_5L 0xFE /* Enabled */
1801 /* Code Protect 0004000-007FFF 5L options */
1802 #define _CP_1_OFF_5L 0xFF /* Disabled */
1803 #define _CP_1_ON_5L 0xFD /* Enabled */
1805 /* Code Protect 008000-00BFFF 5L options */
1806 #define _CP_2_OFF_5L 0xFF /* Disabled */
1807 #define _CP_2_ON_5L 0xFB /* Enabled */
1809 /* Code Protect 00C000F-00FFFF 5L options */
1810 #define _CP_3_OFF_5L 0xFF /* Disabled */
1811 #define _CP_3_ON_5L 0xF7 /* Enabled */
1813 /* Data EE Read Protect 5H options */
1814 #define _CPD_OFF_5H 0xFF /* Disabled */
1815 #define _CPD_ON_5H 0x7F /* Enabled */
1817 /* Code Protect Boot 5H options */
1818 #define _CPB_OFF_5H 0xFF /* Disabled */
1819 #define _CPB_ON_5H 0xBF /* Enabled */
1821 /* Table Write Protect 00800-003FFF 6L options */
1822 #define _WRT_0_OFF_6L 0xFF /* Disabled */
1823 #define _WRT_0_ON_6L 0xFE /* Enabled */
1825 /* Table Write Protect 004000-007FFF 6L options */
1826 #define _WRT_1_OFF_6L 0xFF /* Disabled */
1827 #define _WRT_1_ON_6L 0xFD /* Enabled */
1829 /* Table Write Protect 08000-0BFFF 6L options */
1830 #define _WRT_2_OFF_6L 0xFF /* Disabled */
1831 #define _WRT_2_ON_6L 0xFB /* Enabled */
1833 /* Table Write Protect 0C000-0FFFF 6L options */
1834 #define _WRT_3_OFF_6L 0xFF /* Disabled */
1835 #define _WRT_3_ON_6L 0xF7 /* Enabled */
1837 /* Data EE Write Protect 6H options */
1838 #define _WRTD_OFF_6H 0xFF /* Disabled */
1839 #define _WRTD_ON_6H 0x7F /* Enabled */
1841 /* Table Write Protect Boot 6H options */
1842 #define _WRTB_OFF_6H 0xFF /* Disabled */
1843 #define _WRTB_ON_6H 0xBF /* Enabled */
1845 /* Config. Write Protect 6H options */
1846 #define _WRTC_OFF_6H 0xFF /* Disabled */
1847 #define _WRTC_ON_6H 0xDF /* Enabled */
1849 /* Table Read Protect 00800-003FFF 7L options */
1850 #define _EBTR_0_OFF_7L 0xFF /* Disabled */
1851 #define _EBTR_0_ON_7L 0xFE /* Enabled */
1853 /* Table Read Protect 004000-07FFF 7L options */
1854 #define _EBTR_1_OFF_7L 0xFF /* Disabled */
1855 #define _EBTR_1_ON_7L 0xFD /* Enabled */
1857 /* Table Read Protect 08000-0BFFF 7L options */
1858 #define _EBTR_2_OFF_7L 0xFF /* Disabled */
1859 #define _EBTR_2_ON_7L 0xFB /* Enabled */
1861 /* Table Read Protect 0C000-0FFFF 7L options */
1862 #define _EBTR_3_OFF_7L 0xFF /* Disabled */
1863 #define _EBTR_3_ON_7L 0xF7 /* Enabled */
1865 /* Table Read Protect Boot 7H options */
1866 #define _EBTRB_OFF_7H 0xFF /* Disabled */
1867 #define _EBTRB_ON_7H 0xBF /* Enabled */
1870 /* Device ID locations */
1871 #define __IDLOC0 0x200000
1872 #define __IDLOC1 0x200001
1873 #define __IDLOC2 0x200002
1874 #define __IDLOC3 0x200003
1875 #define __IDLOC4 0x200004
1876 #define __IDLOC5 0x200005
1877 #define __IDLOC6 0x200006
1878 #define __IDLOC7 0x200007