1 /*-------------------------------------------------------------------------
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2 Register Declarations for ST's uPSD33xx "Fast 8032 MCU with Programmable Logic"
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3 (Based on preliminary datasheet from Jan/2005 )
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5 Written By - Jesus Calvino-Fraga / jesusc at ece.ubc.ca (May 2007)
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7 This library is free software; you can redistribute it and/or
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8 modify it under the terms of the GNU Lesser General Public
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9 License as published by the Free Software Foundation; either
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10 version 2.1 of the License, or (at your option); any later version
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12 This library is distributed in the hope that it will be useful,
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13 but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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15 Lesser General Public License for more details
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17 You should have received a copy of the GNU Lesser General Public
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18 License along with this library; if not, write to the Free Software
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19 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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21 In other words, you are welcome to use, share and improve this program
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22 You are forbidden to forbid anyone else to use, share and improve
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23 what you give them. Help stamp out software-hoarding!
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24 -------------------------------------------------------------------------*/
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25 #ifndef REG_UPSD33XX_H
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26 #define REG_UPSD33XX_H
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28 #include <compiler.h>
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30 //Interrupt vector numbers (see table 16 on datasheet)
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31 #define EXT0_INTERRUPT ((0x03-3)/8)
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32 #define TIMER0_INTERRUPT ((0x0B-3)/8)
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33 #define EXT1_INTERRUPT ((0x13-3)/8)
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34 #define TIMER1_INTERRUPT ((0x1B-3)/8)
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35 #define UART0_INTERRUPT ((0x23-3)/8)
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36 #define TIMER2_INTERRUPT ((0x2B-3)/8)
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37 #define TX2_INTERRUPT ((0x2B-3)/8)
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38 #define SPI_INTERRUPT ((0x53-3)/8)
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39 #define I2C_INTERRUPT ((0x43-3)/8)
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40 #define ADC_INTERRUPT ((0x3B-3)/8)
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41 #define PCA_INTERRUPT ((0x5B-3)/8)
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42 #define UART1_INTERRUPT ((0x4B-3)/8)
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44 SFR(SP, 0x81); // Stack Pointer.
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45 SFR(DPL, 0x82); // Data Pointer Low.
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46 SFR(DPH, 0x83); // Data Pointer High.
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48 SFR(DPTC, 0x85); // Data Pointer Control Register.
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49 #define AT 0x40 //0:Manually Select Data Pointer / 1:Auto Toggle between DPTR0 and DPTR1
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50 #define DPSE0 0x01 // 0:DPTR0 Selected for use as DPTR / 1:DPTR1 Selected for use as DPTR
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52 SFR(DPTM, 0x86); // Data Pointer Mode Register.
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53 #define DP1_1 0x08 // DPTR1 Mode Bit 1.
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54 #define DP1_0 0x04 // DPTR1 Mode Bit 0.
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55 #define DP0_1 0x02 // DPTR0 Mode Bit 1.
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56 #define DP0_0 0x01 // DPTR0 Mode Bit 0.
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58 // 0 0 : DPTRx No Change
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60 // 1 0 : DPTRx Auto Increment
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61 // 1 1 : DPTRx Auto Decrement
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63 SFR(PCON, 0x87); // Power Control.
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64 #define SMOD0 0x80 //Baud Rate Double Bit (UART0)
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65 #define SMOD1 0x40 //Baud Rate Double Bit (UART1)
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66 #define POR 0x10 //Only a power-on reset sets this bit (cold reset).
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67 #define RCLK1 0x08 //Receive Clock Flag (UART1)
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68 #define TCLK1 0x04 //Transmit Clock Flag (UART1)
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69 #define PD 0x02 //Power-Down Mode Enable.
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70 #define IDL 0x01 //Idle Mode Enable.
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72 SFR(TCON, 0x88); // Timer/Counter Control.
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73 SBIT(TF1, 0x88, 7); // Timer 1 overflow flag.
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74 SBIT(TR1, 0x88, 6); // Timer 1 run control flag.
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75 SBIT(TF0, 0x88, 5); // Timer 0 overflow flag.
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76 SBIT(TR0, 0x88, 4); // Timer 0 run control flag.
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77 SBIT(IE1, 0x88, 3); // Interrupt 1 flag.
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78 SBIT(IT1, 0x88, 2); // Interrupt 1 type control bit.
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79 SBIT(IE0, 0x88, 1); // Interrupt 0 flag.
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80 SBIT(IT0, 0x88, 0); // Interrupt 0 type control bit.
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82 SFR(TMOD, 0x89); // Timer/Counter Mode Control.
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83 #define GATE1 0x80 // External enable for timer 1.
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84 #define C_T1 0x40 // Timer or counter select for timer 1.
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85 #define M1_1 0x20 // Operation mode bit 1 for timer 1.
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86 #define M0_1 0x10 // Operation mode bit 0 for timer 1.
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87 #define GATE0 0x08 // External enable for timer 0.
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88 #define C_T0 0x04 // Timer or counter select for timer 0.
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89 #define M1_0 0x02 // Operation mode bit 1 for timer 0.
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90 #define M0_0 0x01 // Operation mode bit 0 for timer 0.
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92 SFR(TL0, 0x8A); // Timer 0 LSB.
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93 SFR(TL1, 0x8B); // Timer 1 LSB.
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94 SFR(TH0, 0x8C); // Timer 0 MSB.
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95 SFR(TH1, 0x8D); // Timer 1 MSB.
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97 //For P1SFS0 and P1SFS1 SFRs details check datasheet Table 31.
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98 SFR(P1SFS0, 0x8E); //Port 1 Special Function Select 0 Register.
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100 #define P1SF06 0x40
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101 #define P1SF05 0x20
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102 #define P1SF04 0x10
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103 #define P1SF03 0x08
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104 #define P1SF02 0x04
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105 #define P1SF01 0x02
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106 #define P1SF00 0x01
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107 SFR(P1SFS1, 0x8F); //Port 1 Special Function Select 1 Register.
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108 #define P1SF17 0x80
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109 #define P1SF16 0x40
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110 #define P1SF15 0x20
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111 #define P1SF14 0x10
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112 #define P1SF13 0x08
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113 #define P1SF12 0x04
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114 #define P1SF11 0x02
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115 #define P1SF10 0x01
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117 SFR(P1, 0x90); // Port 1
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118 SBIT(P1_0, 0x90, 0); // Port 1 bit 0.
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119 SBIT(P1_1, 0x90, 1); // Port 1 bit 1.
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120 SBIT(P1_2, 0x90, 2); // Port 1 bit 2.
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121 SBIT(P1_3, 0x90, 3); // Port 1 bit 3.
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122 SBIT(P1_4, 0x90, 4); // Port 1 bit 4.
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123 SBIT(P1_5, 0x90, 5); // Port 1 bit 5.
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124 SBIT(P1_6, 0x90, 6); // Port 1 bit 6.
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125 SBIT(P1_7, 0x90, 7); // Port 1 bit 7.
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126 //Alternate names (from figure 3)
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127 SBIT(T2, 0x90, 0); //Input to Timer/Counter 2.
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128 SBIT(T2X, 0x90, 1); //Capture/reload trigger for Counter 2.
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129 SBIT(RXD1, 0x90, 2);
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130 SBIT(TXD1, 0x90, 3);
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131 SBIT(SPICLK, 0x90, 4);
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132 SBIT(SPIRXD, 0x90, 5);
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133 SBIT(SPITXD, 0x90, 6);
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134 SBIT(SPISEL, 0x90, 7);
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136 SFR(P3SFS, 0x91); // Port 3 Special Function Select Register
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146 //For P4SFS0 and P4SFS1 SFRs details check datasheet Table 34.
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147 SFR(P4SFS0, 0x92); //Port 4 Special Function Select 0 Register.
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148 #define P4SF07 0x80
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149 #define P4SF06 0x40
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150 #define P4SF05 0x20
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151 #define P4SF04 0x10
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152 #define P4SF03 0x08
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153 #define P4SF02 0x04
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154 #define P4SF01 0x02
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155 #define P4SF00 0x01
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156 SFR(P4SFS1, 0x93); //Port 4 Special Function Select 1 Register.
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157 #define P4SF17 0x80
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158 #define P4SF16 0x40
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159 #define P4SF15 0x20
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160 #define P4SF14 0x10
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161 #define P4SF13 0x08
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162 #define P4SF12 0x04
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163 #define P4SF11 0x02
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164 #define P4SF10 0x01
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166 SFR(ADCPS, 0x94); // ADC pre-scaller?
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167 #define ADCCE 0x08 // ADC Conversion Reference Clock Enable.
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168 //ADC Reference Clock PreScaler. Only three Prescaler values are allowed:
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169 #define ADCPS2 0x02 // Resulting ADC clock is fOSC.
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170 #define ADCPS1 0x01 // Resulting ADC clock is fOSC/2.
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171 #define ADCPS0 0x00 // Resulting ADC clock is fOSC/4.
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173 SFR(ADAT0, 0x95); // A/D result register (bits 0 to 7).
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174 SFR(ADAT1, 0x96); // A/D result register (bits 8 and 9).
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175 SFR(ACON, 0x97); // A/D control register.
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176 #define AINTF 0x80 // ADC Interrupt flag. This bit must be cleared with software.
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177 #define AINTEN 0x40 // ADC Interrupt Enable.
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178 #define ADEN 0x20 // ADC Enable Bit.
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179 #define ADS2 0x10 // Analog channel Select bit 3.
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180 #define ADS1 0x08 // Analog channel Select bit 2.
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181 #define ADS0 0x04 // Analog channel Select bit 1.
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182 #define ADST 0x02 // ADC Start Bit.
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183 #define ADSF 0x01 // ADC Status Bit.
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185 SFR(SCON, 0x98); // For compatibity with legacy code
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186 SFR(SCON0, 0x98); // Serial Port UART0 Control Register
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187 SBIT(SM0, 0x98, 7); // Serial Port Mode Bit 0.
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188 SBIT(SM1, 0x98, 6); // Serial Port Mode Bit 1.
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189 SBIT(SM2, 0x98, 5); // Serial Port Mode Bit 2.
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190 SBIT(REN, 0x98, 4); // Enables serial reception.
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191 SBIT(TB8, 0x98, 3); // The 9th data bit that will be transmitted in Modes 2 and 3.
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192 SBIT(RB8, 0x98, 2); // In Modes 2 and 3, the 9th data bit that was received.
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193 SBIT(TI, 0x98, 1); // Transmit interrupt flag.
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194 SBIT(RI, 0x98, 0); // Receive interrupt flag.
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196 SFR(SBUF, 0x99); // For compatibity with legacy code.
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197 SFR(SBUF0, 0x99); // Serial Port UART0 Data Buffer.
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199 SFR(BUSCON, 0x9D); // Bus Control Register.
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200 #define EPFQ 0x80 // Enable Pre-Fetch Queue.
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201 #define EBC 0x40 // Enable Branch Cache.
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202 #define WRW1 0x20 // WR Wait bit 2.
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203 #define WRW0 0x10 // WR Wait bit 1.
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204 #define RDW1 0x08 // RD Wait bit 2.
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205 #define RDW0 0x04 // RD Wait bit 1.
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206 #define CW1 0x02 // PSEN Wait bit 2.
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207 #define CW0 0x01 // PSEN Wait bit 1.
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209 SFR(PCACL0, 0xA2); // The low 8 bits of PCA 0 16-bit counter.
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210 SFR(PCACH0, 0xA3); // The high 8 bits of PCA 0 16-bit counter.
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211 SFR(PCACON0, 0xA4); // PCA 0 Control Register.
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212 SFR(PCASTA, 0xA5); // PCA 0 and PCA 1 Status Register.
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213 SFR(PCACL1, 0xBA); // The low 8 bits of PCA 1 16-bit counter.
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214 SFR(PCACH1, 0xBB); // The high 8 bits of PCA 1 16-bit counter.
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215 SFR(PCACON1, 0xBC); // PCA 1 Control Register.
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217 SFR(IEA, 0xA7); // Interrupt Enable Addition Register.
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218 #define EADC 0x80 // Enable ADC Interrupt.
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219 #define ESPI 0x40 // Enable SPI Interrupt.
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220 #define EPCA 0x20 // Enable Programmable Counter Array Interrupt.
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221 #define ES1 0x10 // Enable UART1 Interrupt.
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222 #define EI2C 0x02 // Enable I2C Interrupt.
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224 SFR(IE, 0xA8); // Interrupt Enable Register.
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225 SBIT(EA, 0xA8, 7); // Global disable bit.
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226 SBIT(ET2, 0xA8, 5); // Enable Timer 2 Interrupt.
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227 SBIT(ES0, 0xA8, 4); // Enable UART0 Interrupt.
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228 SBIT(ET1, 0xA8, 3); // Enable Timer 1 Interrupt.
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229 SBIT(EX1, 0xA8, 2); // Enable External Interrupt INT1.
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230 SBIT(ET0, 0xA8, 1); // Enable Timer 0 Interrupt.
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231 SBIT(EX0, 0xA8, 0); // Enable External Interrupt INT0.
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233 SFR(TCMMODE0, 0xA9); // TCM 0 Mode.
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234 SFR(TCMMODE1, 0xAA); // TCM 1 Mode.
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235 SFR(TCMMODE2, 0xAB); // TCM 2 Mode.
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236 SFR(TCMMODE3, 0xBD); // TCM 3 Mode.
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237 SFR(TCMMODE4, 0xBE); // TCM 4 Mode.
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238 SFR(TCMMODE5, 0xBF); // TCM 5 Mode.
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239 //These are the bits for the six SFRs above:
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240 #define EINTF 0x80 // Enable the interrupt flags (INTF) in the Status Register to generate an interrupt.
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241 #define E_COMP 0x40 // Enable the comparator when set.
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242 #define CAP_PE 0x20 // Enable Capture Mode, a positive edge on the CEXn pin.
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243 #define CAP_NE 0x20 // Enable Capture Mode, a negative edge on the CEXn pin.
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244 #define MATCH 0x08 // A match from the comparator sets the INTF bits in the Status Register.
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245 #define TOGGLE 0x04 // A match on the comparator results in a toggling output on CEXn pin.
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246 #define PWM1 0x02 // PWM mode bit 2.
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247 #define PWM0 0x01 // PWM mode bit 1.
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249 SFR(CAPCOML0, 0xAC); // Capture/Compare register low of TCM 0.
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250 SFR(CAPCOMH0, 0xAD); // Capture/Compare register High of TCM 0.
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251 SFR(CAPCOML1, 0xAF); // Capture/Compare register low of TCM 1.
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252 SFR(CAPCOMH1, 0xB1); // Capture/Compare register High of TCM 1.
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253 SFR(CAPCOML2, 0xB2); // Capture/Compare register low of TCM 2.
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254 SFR(CAPCOMH2, 0xB3); // Capture/Compare register High of TCM 2.
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255 SFR(CAPCOML3, 0xC1); // Capture/Compare register low of TCM 3.
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256 SFR(CAPCOMH3, 0xC2); // Capture/Compare register High of TCM 3.
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257 SFR(CAPCOML4, 0xC3); // Capture/Compare register low of TCM 4.
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258 SFR(CAPCOMH4, 0xC4); // Capture/Compare register High of TCM 4.
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259 SFR(CAPCOML5, 0xC5); // Capture/Compare register low of TCM 5.
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260 SFR(CAPCOMH5, 0xC6); // Capture/Compare register High of TCM 5.
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262 SFR(IPA, 0xB7); // Interrupt Priority Addition register.
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263 #define PADC 0x80 // ADC Interrupt priority level.
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264 #define PSPI 0x40 // SPI Interrupt priority level.
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265 #define PPCA 0x20 // PCA Interrupt level.
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266 #define PS1 0x10 // UART1 Interrupt priority.
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267 #define PI2C 0x02 // I2C Interrupt priority level.
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269 SFR(IP, 0xB8); // Interrupt Priority Register.
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270 SBIT(PT2, 0xB8, 5); // Timer 2 Interrupt priority level.
\r
271 SBIT(PS0, 0xB8, 4); // UART0 Interrupt priority level.
\r
272 SBIT(PT1, 0xB8, 3); // Timer 1 Interrupt priority level.
\r
273 SBIT(PX1, 0xB8, 2); // External Interrupt INT1 priority level.
\r
274 SBIT(PT0, 0xB8, 1); // Timer 0 Interrupt priority level.
\r
275 SBIT(PX0, 0xB8, 0); // External Interrupt INT0 priority level.
\r
277 SFR(WDTRST, 0xA6); // Watchdog Timer Reset Counter Register.
\r
278 SFR(WDTKEY, 0xAE); //Watchdog Timer Key Register.
\r
280 SFR(P3, 0xB0); // I/O Port 3 Register
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281 SBIT(P3_0, 0xB0, 0); // Port 3 bit 0.
\r
282 SBIT(P3_1, 0xB0, 1); // Port 3 bit 1.
\r
283 SBIT(P3_2, 0xB0, 2); // Port 3 bit 2.
\r
284 SBIT(P3_3, 0xB0, 3); // Port 3 bit 3.
\r
285 SBIT(P3_4, 0xB0, 4); // Port 3 bit 4.
\r
286 SBIT(P3_5, 0xB0, 5); // Port 3 bit 5.
\r
287 SBIT(P3_6, 0xB0, 6); // Port 3 bit 6.
\r
288 SBIT(P3_7, 0xB0, 7); // Port 3 bit 7.
\r
290 SFR(P4, 0xC0); // I/O Port 4 Register
\r
291 SBIT(P4_0, 0xC0, 0); // Port 4 bit 0.
\r
292 SBIT(P4_1, 0xC0, 1); // Port 4 bit 1.
\r
293 SBIT(P4_2, 0xC0, 2); // Port 4 bit 2.
\r
294 SBIT(P4_3, 0xC0, 3); // Port 4 bit 3.
\r
295 SBIT(P4_4, 0xC0, 4); // Port 4 bit 4.
\r
296 SBIT(P4_5, 0xC0, 5); // Port 4 bit 5.
\r
297 SBIT(P4_6, 0xC0, 6); // Port 4 bit 6.
\r
298 SBIT(P4_7, 0xC0, 7); // Port 4 bit 7.
\r
300 SFR(PWMF0, 0xB4); // PWM frequency register 0.
\r
301 SFR(PWMF1, 0xC7); // PWM frequency register 1.
\r
303 SFR(T2CON, 0xC8); // Timer / Counter 2 Control.
\r
304 SBIT(TF2, 0xC8, 7); // Timer 2 overflow flag.
\r
305 SBIT(EXF2, 0xC8, 6); // Timer 2 external flag.
\r
306 SBIT(RCLK, 0xC8, 5); // Receive clock flag.
\r
307 SBIT(TCLK, 0xC8, 4); // Transmit clock flag.
\r
308 SBIT(EXEN2, 0xC8, 3); // Timer 2 external enable flag.
\r
309 SBIT(TR2, 0xC8, 2); // Start/stop control for timer 2.
\r
310 SBIT(CNT2, 0xC8, 1); // Timer or coutner select.
\r
311 SBIT(CAP2, 0xC8, 0); // Capture/reload flag.
\r
313 SFR(RCAP2L, 0xCA); // Timer 2 Capture LSB.
\r
314 SFR(RCAP2H, 0xCB); // Timer 2 Capture MSB.
\r
315 SFR(TL2, 0xCC); // Timer 2 LSB.
\r
316 SFR(TH2, 0xCD); // Timer 2 MSB.
\r
318 SFR(IRDACON, 0xCE); //IrDA control register
\r
319 #define IRDAEN 0x40 // IrDA Enable bit
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320 #define PULSE 0x20 // IrDA Pulse Modulation Select. 0: 1.627us, 1: 3/16 bit time pulses.
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321 #define CDIV4 0x10 //Specify Clock Divider bit 5.
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322 #define CDIV3 0x08 //Specify Clock Divider bit 4.
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323 #define CDIV2 0x04 //Specify Clock Divider bit 3.
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324 #define CDIV1 0x02 //Specify Clock Divider bit 2.
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325 #define CDIV0 0x01 //Specify Clock Divider bit 1.
\r
327 SFR(CCON0, 0xF9); // Clock Control Register.
\r
328 #define DBGCE 0x10 // Debug Unit Breakpoint Comparator Enable.
\r
329 #define CPUAR 0x08 // Automatic MCU Clock Recovery.
\r
330 #define CPUPS2 0x04 // MCUCLK Pre-Scaler bit 3.
\r
331 #define CPUPS1 0x02 // MCUCLK Pre-Scaler bit 2.
\r
332 #define CPUPS0 0x01 // MCUCLK Pre-Scaler bit 1.
\r
334 SFR(CCON2, 0xFB); // Pre-scaler value for PCA0.
\r
335 #define PCA0CE 0x10 // PCA0 Clock Enable.
\r
336 #define PCA0PS3 0x08 // PCA0 Pre-Scaler bit 4.
\r
337 #define PCA0PS2 0x04 // PCA0 Pre-Scaler bit 3.
\r
338 #define PCA0PS1 0x02 // PCA0 Pre-Scaler bit 2.
\r
339 #define PCA0PS0 0x01 // PCA0 Pre-Scaler bit 1.
\r
341 SFR(CCON3, 0xFC); // Pre-scaler value for PCA1.
\r
342 #define PCA1CE 0x10 // PCA1 Clock Enable.
\r
343 #define PCA1PS3 0x08 // PCA1 Pre-Scaler bit 4.
\r
344 #define PCA1PS2 0x04 // PCA1 Pre-Scaler bit 3.
\r
345 #define PCA1PS1 0x02 // PCA1 Pre-Scaler bit 2.
\r
346 #define PCA1PS0 0x01 // PCA1 Pre-Scaler bit 1.
\r
348 SFR(SPICLKD, 0xD2); // SPI Prescaler (Clock Divider) Register.
\r
349 #define DIV128 0x80
\r
356 SFR(SPISTAT, 0xD3); // SPI Interface Status Register.
\r
357 #define BUSY 0x10 // SPI Busy.
\r
358 #define TEISF 0x08 // Transmission End Interrupt Source flag.
\r
359 #define RORISF 0x04 // Receive Overrun Interrupt Source flag.
\r
360 #define TISF 0x02 // Transfer Interrupt Source flag.
\r
361 #define RISF 0x01 // Receive Interrupt Source flag.
\r
363 SFR(SPITDR, 0xD4); // SPI transmit data register.
\r
364 SFR(SPIRDR, 0xD5); // SPI receive data register.
\r
366 SFR(SPICON0, 0xD6); // SPI Control Register 0.
\r
367 #define TE 0x40 // Transmitter Enable.
\r
368 #define RE 0x20 // Receiver Enable.
\r
369 #define SPIEN 0x10 // SPI Enable.
\r
370 #define SSEL 0x08 // Slave Selection.
\r
371 #define FLSB 0x04 // First LSB.
\r
372 #define SPO 0x02 // Sampling Polarity.
\r
374 SFR(SPICON1, 0xD7); // SPI Interface Control Register 1.
\r
375 #define TEIE 0x08 // Transmission End Interrupt Enable.
\r
376 #define RORIE 0x04 // Receive Overrun Interrupt Enable.
\r
377 #define TIE 0x02 // Transmission Interrupt Enable.
\r
378 #define RIE 0x01 // Reception Interrupt Enable.
\r
380 SFR(SCON1, 0x98); // Serial Port Control.
\r
381 SBIT(SM0, 0x98, 7); // Serial Port Mode Bit 0.
\r
382 SBIT(SM1, 0x98, 6); // Serial Port Mode Bit 1.
\r
383 SBIT(SM2, 0x98, 5); // Serial Port Mode Bit 2.
\r
384 SBIT(REN, 0x98, 4); // Enables serial reception.
\r
385 SBIT(TB8, 0x98, 3); // The 9th data bit that will be transmitted in Modes 2 and 3.
\r
386 SBIT(RB8, 0x98, 2); // In Modes 2 and 3, the 9th data bit that was received.
\r
387 SBIT(TI, 0x98, 1); // Transmit interrupt flag.
\r
388 SBIT(RI, 0x98, 0); // Receive interrupt flag.
\r
390 SFR(SBUF1, 0xD9); // Data buffer for UART1.
\r
391 SFR(S1SETUP, 0xDB); // I2C START Condition Sample Setup register.
\r
392 #define EN_SS 0x80 // Enable Sample Setup.
\r
393 #define SMPL_SET6 0x40 // Sample Setting bit 7.
\r
394 #define SMPL_SET5 0x20 // Sample Setting bit 6.
\r
395 #define SMPL_SET4 0x10 // Sample Setting bit 5.
\r
396 #define SMPL_SET3 0x08 // Sample Setting bit 4.
\r
397 #define SMPL_SET2 0x04 // Sample Setting bit 3.
\r
398 #define SMPL_SET1 0x02 // Sample Setting bit 2.
\r
399 #define SMPL_SET0 0x01 // Sample Setting bit 1.
\r
401 SFR(S1CON, 0xDC); // I2C Interface Control Register.
\r
402 #define CR2 0x80 // SCL clock frequency select bit 3.
\r
403 #define ENI1 0x40 // I2C Interface Enable.
\r
404 #define STA 0x20 // START flag.
\r
405 #define STO 0x10 // STOP flag.
\r
406 #define ADDR 0x08 // Slave mode address.
\r
407 #define AA 0x04 // Assert Acknowledge enable.
\r
408 #define CR1 0x02 // SCL clock frequency select bit 2.
\r
409 #define CR0 0x01 // SCL clock frequency select bit 1.
\r
411 SFR(S1STA, 0xDD); // I2C Interface Status Register.
\r
412 #define GC 0x80 // General Call flag.
\r
413 #define STOP 0x40 // STOP flag.
\r
414 #define INTR 0x20 // Interrupt flag.
\r
415 #define TX_MODE 0x10 // Transmission Mode flag.
\r
416 #define BBUSY 0x08 // Bus Busy flag.
\r
417 #define BLOST 0x04 // Bus Lost flag.
\r
418 #define ACK_RESP 0x02 // Not Acknowledge Response flag.
\r
419 #define SLV 0x01 // Slave Mode flag.
\r
421 SFR(S1DAT, 0xDE); // I2C Data Shift Register.
\r
422 SFR(S1ADR, 0xDF); // I2C Address Register (bit 0 not used).
\r
424 SFR(PSW, 0xD0); // Program Status Word.
\r
425 SBIT(CY, 0xD0, 7); // Carry Flag.
\r
426 SBIT(AC, 0xD0, 6); // Auxiliary Carry Flag.
\r
427 SBIT(F0, 0xD0, 5); // User-Defined Flag.
\r
428 SBIT(RS1, 0xD0, 4); // Register Bank Select 1.
\r
429 SBIT(RS0, 0xD0, 3); // Register Bank Select 0.
\r
430 SBIT(OV, 0xD0, 2); // Overflow Flag.
\r
431 SBIT(P, 0xD0, 0); // Parity Flag.
\r
434 SFR(ACC, 0xE0); // Accumulator
\r
435 SBIT(ACC_0, 0xE0, 0); // Accumulator bit 0.
\r
436 SBIT(ACC_1, 0xE0, 1); // Accumulator bit 1.
\r
437 SBIT(ACC_2, 0xE0, 2); // Accumulator bit 2.
\r
438 SBIT(ACC_3, 0xE0, 3); // Accumulator bit 3.
\r
439 SBIT(ACC_4, 0xE0, 4); // Accumulator bit 4.
\r
440 SBIT(ACC_5, 0xE0, 5); // Accumulator bit 5.
\r
441 SBIT(ACC_6, 0xE0, 6); // Accumulator bit 6.
\r
442 SBIT(ACC_7, 0xE0, 7); // Accumulator bit 7.
\r
444 SFR(B, 0xF0); // B Register
\r
445 SBIT(B_0, 0xF0, 0); // Register B bit 0.
\r
446 SBIT(B_1, 0xF0, 1); // Register B bit 1.
\r
447 SBIT(B_2, 0xF0, 2); // Register B bit 2.
\r
448 SBIT(B_3, 0xF0, 3); // Register B bit 3.
\r
449 SBIT(B_4, 0xF0, 4); // Register B bit 4.
\r
450 SBIT(B_5, 0xF0, 5); // Register B bit 5.
\r
451 SBIT(B_6, 0xF0, 6); // Register B bit 6.
\r
452 SBIT(B_7, 0xF0, 7); // Register B bit 7.
\r
454 #endif //REG_UPSD33XX_H
\r
projects / fw / sdcc / blob