1 /*-------------------------------------------------------------------------
2 Register Declarations for SIEMENS/INFINEON SAB 80515 Processor
4 Written By - Bela Torok
6 based on reg51.h by Sandeep Dutta sandeep.dutta@usa.net
7 KEIL C compatible definitions are included
9 This library is free software; you can redistribute it and/or
10 modify it under the terms of the GNU Lesser General Public
11 License as published by the Free Software Foundation; either
12 version 2.1 of the License, or (at your option) any later version.
14 This library is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 Lesser General Public License for more details.
19 You should have received a copy of the GNU Lesser General Public
20 License along with this library; if not, write to the Free Software
21 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 In other words, you are welcome to use, share and improve this program.
24 You are forbidden to forbid anyone else to use, share and improve
25 what you give them. Help stamp out software-hoarding!
26 -------------------------------------------------------------------------*/
31 /* BYTE addressable registers */
36 __sfr __at 0x87 PCON ;
37 __sfr __at 0x88 TCON ;
38 __sfr __at 0x89 TMOD ;
44 __sfr __at 0x98 SCON ;
45 __sfr __at 0x99 SBUF ;
48 __sfr __at 0xA8 IEN0 ; /* as called by Siemens */
49 __sfr __at 0xA9 IP0 ; /* interrupt priority register - SAB80515 specific */
51 __sfr __at 0xB8 IEN1 ; /* interrupt enable register - SAB80515 specific */
52 __sfr __at 0xB9 IP1 ; /* interrupt priority register as called by Siemens */
53 __sfr __at 0xC0 IRCON ; /* interrupt control register - SAB80515 specific */
54 __sfr __at 0xC1 CCEN ; /* compare/capture enable register */
55 __sfr __at 0xC2 CCL1 ; /* compare/capture register 1, low byte */
56 __sfr __at 0xC3 CCH1 ; /* compare/capture register 1, high byte */
57 __sfr __at 0xC4 CCL2 ; /* compare/capture register 2, low byte */
58 __sfr __at 0xC5 CCH2 ; /* compare/capture register 2, high byte */
59 __sfr __at 0xC6 CCL3 ; /* compare/capture register 3, low byte */
60 __sfr __at 0xC7 CCH3 ; /* compare/capture register 3, high byte */
61 __sfr __at 0xC8 T2CON ;
62 __sfr __at 0xCA CRCL ; /* compare/reload/capture register, low byte */
63 __sfr __at 0xCB CRCH ; /* compare/reload/capture register, high byte */
67 __sfr __at 0xD8 ADCON ; /* A/D-converter control register */
68 __sfr __at 0xD9 ADDAT ; /* A/D-converter data register */
69 __sfr __at 0xDA DAPR ; /* D/A-converter program register */
70 __sfr __at 0xDB P6 ; /* Port 6 - SAB80515 specific */
73 __sfr __at 0xE8 P4 ; /* Port 4 - SAB80515 specific */
75 __sfr __at 0xF8 P5 ; /* Port 5 - SAB80515 specific */
78 /* BIT addressable registers */
80 __sbit __at 0x80 P0_0 ;
81 __sbit __at 0x81 P0_1 ;
82 __sbit __at 0x82 P0_2 ;
83 __sbit __at 0x83 P0_3 ;
84 __sbit __at 0x84 P0_4 ;
85 __sbit __at 0x85 P0_5 ;
86 __sbit __at 0x86 P0_6 ;
87 __sbit __at 0x87 P0_7 ;
90 __sbit __at 0x88 IT0 ;
91 __sbit __at 0x89 IE0 ;
92 __sbit __at 0x8A IT1 ;
93 __sbit __at 0x8B IE1 ;
94 __sbit __at 0x8C TR0 ;
95 __sbit __at 0x8D TF0 ;
96 __sbit __at 0x8E TR1 ;
97 __sbit __at 0x8F TF1 ;
100 __sbit __at 0x90 P1_0 ;
101 __sbit __at 0x91 P1_1 ;
102 __sbit __at 0x92 P1_2 ;
103 __sbit __at 0x93 P1_3 ;
104 __sbit __at 0x94 P1_4 ;
105 __sbit __at 0x95 P1_5 ;
106 __sbit __at 0x96 P1_6 ;
107 __sbit __at 0x97 P1_7 ;
109 __sbit __at 0x90 INT3_CC0 ; /* P1 alternate functions - SAB80515 specific */
110 __sbit __at 0x91 INT4_CC1 ;
111 __sbit __at 0x92 INT5_CC2 ;
112 __sbit __at 0x93 INT6_CC3 ;
113 __sbit __at 0x94 INT2 ;
114 __sbit __at 0x95 T2EX ;
115 __sbit __at 0x96 CLKOUT ;
116 __sbit __at 0x97 T2 ;
119 __sbit __at 0x98 RI ;
120 __sbit __at 0x99 TI ;
121 __sbit __at 0x9A RB8 ;
122 __sbit __at 0x9B TB8 ;
123 __sbit __at 0x9C REN ;
124 __sbit __at 0x9D SM2 ;
125 __sbit __at 0x9E SM1 ;
126 __sbit __at 0x9F SM0 ;
129 __sbit __at 0xA0 P2_0 ;
130 __sbit __at 0xA1 P2_1 ;
131 __sbit __at 0xA2 P2_2 ;
132 __sbit __at 0xA3 P2_3 ;
133 __sbit __at 0xA4 P2_4 ;
134 __sbit __at 0xA5 P2_5 ;
135 __sbit __at 0xA6 P2_6 ;
136 __sbit __at 0xA7 P2_7 ;
139 __sbit __at 0xA8 EX0 ;
140 __sbit __at 0xA9 ET0 ;
141 __sbit __at 0xAA EX1 ;
142 __sbit __at 0xAB ET1 ;
143 __sbit __at 0xAC ES ;
144 __sbit __at 0xAD ET2 ;
145 __sbit __at 0xAE WDT ; /* watchdog timer reset - SAB80515 specific */
146 __sbit __at 0xAF EA ;
148 __sbit __at 0xAF EAL ; /* EA as called by Siemens */
151 __sbit __at 0xB0 P3_0 ;
152 __sbit __at 0xB1 P3_1 ;
153 __sbit __at 0xB2 P3_2 ;
154 __sbit __at 0xB3 P3_3 ;
155 __sbit __at 0xB4 P3_4 ;
156 __sbit __at 0xB5 P3_5 ;
157 __sbit __at 0xB6 P3_6 ;
158 __sbit __at 0xB7 P3_7 ;
160 __sbit __at 0xB0 RXD ;
161 __sbit __at 0xB1 TXD ;
162 __sbit __at 0xB2 INT0 ;
163 __sbit __at 0xB3 INT1 ;
164 __sbit __at 0xB4 T0 ;
165 __sbit __at 0xB5 T1 ;
166 __sbit __at 0xB6 WR ;
167 __sbit __at 0xB7 RD ;
170 __sbit __at 0xB8 EADC ; /* A/D converter interrupt enable */
171 __sbit __at 0xB9 EX2 ;
172 __sbit __at 0xBA EX3 ;
173 __sbit __at 0xBB EX4 ;
174 __sbit __at 0xBC EX5 ;
175 __sbit __at 0xBD EX6 ;
176 __sbit __at 0xBE SWDT ; /* watchdog timer start/reset */
177 __sbit __at 0xBF EXEN2 ; /* timer2 external reload interrupt enable */
180 __sbit __at 0xC0 IADC ; /* A/D converter irq flag */
181 __sbit __at 0xC1 IEX2 ; /* external interrupt edge detect flag */
182 __sbit __at 0xC2 IEX3 ;
183 __sbit __at 0xC3 IEX4 ;
184 __sbit __at 0xC4 IEX5 ;
185 __sbit __at 0xC5 IEX6 ;
186 __sbit __at 0xC6 TF2 ; /* timer 2 owerflow flag */
187 __sbit __at 0xC7 EXF2 ; /* timer2 reload flag */
190 __sbit __at 0xC8 T2CON_0 ;
191 __sbit __at 0xC9 T2CON_1 ;
192 __sbit __at 0xCA T2CON_2 ;
193 __sbit __at 0xCB T2CON_3 ;
194 __sbit __at 0xCC T2CON_4 ;
195 __sbit __at 0xCD T2CON_5 ;
196 __sbit __at 0xCE T2CON_6 ;
197 __sbit __at 0xCF T2CON_7 ;
199 __sbit __at 0xC8 T2I0 ;
200 __sbit __at 0xC9 T2I1 ;
201 __sbit __at 0xCA T2CM ;
202 __sbit __at 0xCB T2R0 ;
203 __sbit __at 0xCC T2R1 ;
204 __sbit __at 0xCD I2FR ;
205 __sbit __at 0xCE I3FR ;
206 __sbit __at 0xCF T2PS ;
211 __sbit __at 0xD1 FL ;
212 __sbit __at 0xD2 OV ;
213 __sbit __at 0xD3 RS0 ;
214 __sbit __at 0xD4 RS1 ;
215 __sbit __at 0xD5 F0 ;
216 __sbit __at 0xD6 AC ;
217 __sbit __at 0xD7 CY ;
219 __sbit __at 0xD1 F1 ;
222 __sbit __at 0xD8 MX0 ;
223 __sbit __at 0xD9 MX1 ;
224 __sbit __at 0xDA MX2 ;
225 __sbit __at 0xDB ADM ;
226 __sbit __at 0xDC BSY ;
228 __sbit __at 0xDE CLK ;
229 __sbit __at 0xDF BD ;
232 __sbit __at 0xA0 AREG_F0 ;
233 __sbit __at 0xA1 AREG_F1 ;
234 __sbit __at 0xA2 AREG_F2 ;
235 __sbit __at 0xA3 AREG_F3 ;
236 __sbit __at 0xA4 AREG_F4 ;
237 __sbit __at 0xA5 AREG_F5 ;
238 __sbit __at 0xA6 AREG_F6 ;
239 __sbit __at 0xA7 AREG_F7 ;
242 __sbit __at 0xE8 P4_0 ;
243 __sbit __at 0xE9 P4_1 ;
244 __sbit __at 0xEA P4_2 ;
245 __sbit __at 0xEB P4_3 ;
246 __sbit __at 0xEC P4_4 ;
247 __sbit __at 0xED P4_5 ;
248 __sbit __at 0xEE P4_6 ;
249 __sbit __at 0xEF P4_7 ;
252 __sbit __at 0xF0 BREG_F0 ;
253 __sbit __at 0xF1 BREG_F1 ;
254 __sbit __at 0xF2 BREG_F2 ;
255 __sbit __at 0xF3 BREG_F3 ;
256 __sbit __at 0xF4 BREG_F4 ;
257 __sbit __at 0xF5 BREG_F5 ;
258 __sbit __at 0xF6 BREG_F6 ;
259 __sbit __at 0xF7 BREG_F7 ;
262 __sbit __at 0xF8 P5_0 ;
263 __sbit __at 0xF9 P5_1 ;
264 __sbit __at 0xFA P5_2 ;
265 __sbit __at 0xFB P5_3 ;
266 __sbit __at 0xFC P5_4 ;
267 __sbit __at 0xFD P5_5 ;
268 __sbit __at 0xFE P5_6 ;
269 __sbit __at 0xFF P5_7 ;
271 /* BIT definitions for bits that are not directly accessible */
316 #define T0_GATE_ 0x08
320 #define T1_GATE_ 0x80
325 #define T0_MASK_ 0x0F
326 #define T1_MASK_ 0xF0
336 #define WMCON_WDTEN 0x01
337 #define WMCON_WDTRST 0x02
338 #define WMCON_DPS 0x04
339 #define WMCON_EEMEN 0x08
340 #define WMCON_EEMWE 0x10
341 #define WMCON_PS0 0x20
342 #define WMCON_PS1 0x40
343 #define WMCON_PS2 0x80
346 #define SPCR_SPR0 0x01
347 #define SPCR_SPR1 0x02
348 #define SPCR_CPHA 0x04
349 #define SPCR_CPOL 0x08
350 #define SPCR_MSTR 0x10
351 #define SPCR_DORD 0x20
352 #define SPCR_SPE 0x40
353 #define SPCR_SPIE 0x80
356 #define SPSR_WCOL 0x40
357 #define SPSR_SPIF 0x80
360 #define SPDR_SPD0 0x10
361 #define SPDR_SPD1 0x20
362 #define SPDR_SPD2 0x40
363 #define SPDR_SPD3 0x80
364 #define SPDR_SPD4 0x10
365 #define SPDR_SPD5 0x20
366 #define SPDR_SPD6 0x40
367 #define SPDR_SPD7 0x80
369 /* Interrupt numbers: address = (number * 8) + 3 */
370 #define IE0_VECTOR 0 /* 0x03 external interrupt 0 */
371 #define TF0_VECTOR 1 /* 0x0b timer 0 */
372 #define IE1_VECTOR 2 /* 0x13 external interrupt 1 */
373 #define TF1_VECTOR 3 /* 0x1b timer 1 */
374 #define SI0_VECTOR 4 /* 0x23 serial port 0 */
375 #define TF2_VECTOR 5 /* 0x2B timer 2 */
376 #define EX2_VECTOR 5 /* 0x2B external interrupt 2 */
378 #define IADC_VECTOR 8 /* 0x43 A/D converter interrupt */
379 #define IEX2_VECTOR 9 /* 0x4B external interrupt 2 */
380 #define IEX3_VECTOR 10 /* 0x53 external interrupt 3 */
381 #define IEX4_VECTOR 11 /* 0x5B external interrupt 4 */
382 #define IEX5_VECTOR 12 /* 0x63 external interrupt 5 */
383 #define IEX6_VECTOR 13 /* 0x6B external interrupt 6 */