1 /*-------------------------------------------------------------------------
2 Register Declarations for the ChipCon CC1111 Processor Range
4 Copyright © 2008 Keith Packard <keithp@keithp.com>
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful, but
12 WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 General Public License for more details.
16 You should have received a copy of the GNU General Public License along
17 with this program; if not, write to the Free Software Foundation, Inc.,
18 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
20 Adapted from the Cygnal C8051F12x config file which is:
22 Copyright (C) 2003 - Maarten Brock, sourceforge.brock@dse.nl
24 This library is free software; you can redistribute it and/or
25 modify it under the terms of the GNU Lesser General Public
26 License as published by the Free Software Foundation; either
27 version 2.1 of the License, or (at your option) any later version.
29 This library is distributed in the hope that it will be useful,
30 but WITHOUT ANY WARRANTY; without even the implied warranty of
31 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
32 Lesser General Public License for more details.
34 You should have received a copy of the GNU Lesser General Public
35 License along with this library; if not, write to the Free Software
36 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
37 -------------------------------------------------------------------------*/
44 sfr at 0xA8 IEN0; /* Interrupt Enable 0 Register */
46 sbit at 0xA8 RFTXRXIE; /* RF TX/RX done interrupt enable */
47 sbit at 0xA9 ADCIE; /* ADC interrupt enable */
48 sbit at 0xAA URX0IE; /* USART0 RX interrupt enable */
49 sbit at 0xAB URX1IE; /* USART1 RX interrupt enable (shared with I2S RX) */
50 sbit at 0xAB I2SRXIE; /* I2S RX interrupt enable (shared with USART1 RX) */
51 sbit at 0xAC ENCIE; /* AES encryption/decryption interrupt enable */
52 sbit at 0xAD STIE; /* Sleep Timer interrupt enable */
53 sbit at 0xAF EA; /* Enable All */
55 #define IEN0_EA (1 << 7)
56 #define IEN0_STIE (1 << 5)
57 #define IEN0_ENCIE (1 << 4)
58 #define IEN0_URX1IE (1 << 3)
59 #define IEN0_I2SRXIE (1 << 3)
60 #define IEN0_URX0IE (1 << 2)
61 #define IEN0_ADCIE (1 << 1)
62 #define IEN0_RFTXRXIE (1 << 0)
64 sfr at 0xB8 IEN1; /* Interrupt Enable 1 Register */
66 #define IEN1_P0IE (1 << 5) /* Port 0 interrupt enable */
67 #define IEN1_T4IE (1 << 4) /* Timer 4 interrupt enable */
68 #define IEN1_T3IE (1 << 3) /* Timer 3 interrupt enable */
69 #define IEN1_T2IE (1 << 2) /* Timer 2 interrupt enable */
70 #define IEN1_T1IE (1 << 1) /* Timer 1 interrupt enable */
71 #define IEN1_DMAIE (1 << 0) /* DMA transfer interrupt enable */
74 sfr at 0x9A IEN2; /* Interrupt Enable 2 Register */
76 #define IEN2_WDTIE (1 << 5) /* Watchdog timer interrupt enable */
77 #define IEN2_P1IE (1 << 4) /* Port 1 interrupt enable */
78 #define IEN2_UTX1IE (1 << 3) /* USART1 TX interrupt enable */
79 #define IEN2_I2STXIE (1 << 3) /* I2S TX interrupt enable */
80 #define IEN2_UTX0IE (1 << 2) /* USART0 TX interrupt enable */
81 #define IEN2_P2IE (1 << 1) /* Port 2 interrupt enable */
82 #define IEN2_USBIE (1 << 1) /* USB interrupt enable */
83 #define IEN2_RFIE (1 << 0) /* RF general interrupt enable */
86 #define SLEEP_USB_EN (1 << 7)
87 #define SLEEP_XOSC_STB (1 << 6)
88 #define SLEEP_HFRC_STB (1 << 5)
89 #define SLEEP_RST_POWER (0 << 3)
90 #define SLEEP_RST_EXTERNAL (1 << 3)
91 #define SLEEP_RST_WATCHDOG (2 << 3)
92 #define SLEEP_RST_MASK (3 << 3)
93 #define SLEEP_OSC_PD (1 << 2)
94 #define SLEEP_MODE_PM0 (0 << 0)
95 #define SLEEP_MODE_PM1 (1 << 0)
96 #define SLEEP_MODE_PM2 (2 << 0)
97 #define SLEEP_MODE_PM3 (3 << 0)
98 #define SLEEP_MODE_MASK (3 << 0)
103 sfr at 0x88 TCON; /* CPU Interrupt Flag 1 */
105 sbit at 0x8F URX1IF; /* USART1 RX interrupt flag. Automatically cleared */
106 sbit at 0x8F I2SRXIF; /* I2S RX interrupt flag. Automatically cleared */
107 sbit at 0x8D ADCIF; /* ADC interrupt flag. Automatically cleared */
108 sbit at 0x8B URX0IF; /* USART0 RX interrupt flag. Automatically cleared */
109 sbit at 0x89 RFTXRXIF; /* RF TX/RX complete interrupt flag. Automatically cleared */
111 #define TCON_URX1IF (1 << 7)
112 #define TCON_I2SRXIF (1 << 7)
113 #define TCON_ADCIF (1 << 5)
114 #define TCON_URX0IF (1 << 3)
115 #define TCON_RFTXRXIF (1 << 1)
120 sfr at 0x98 S0CON; /* CPU Interrupt Flag 2 */
122 sbit at 0x98 ENCIF_0; /* AES interrupt 0. */
123 sbit at 0x99 ENCIF_1; /* AES interrupt 1. */
125 #define S0CON_ENCIF_1 (1 << 1)
126 #define S0CON_ENCIF_0 (1 << 0)
131 sfr at 0x9B S1CON; /* CPU Interrupt Flag 3 */
133 #define S1CON_RFIF_1 (1 << 1)
134 #define S1CON_RFIF_0 (1 << 0)
139 sfr at 0xC0 IRCON; /* CPU Interrupt Flag 4 */
141 sbit at 0xC0 DMAIF; /* DMA complete interrupt flag */
142 sbit at 0xC1 T1IF; /* Timer 1 interrupt flag. Automatically cleared */
143 sbit at 0xC2 T2IF; /* Timer 2 interrupt flag. Automatically cleared */
144 sbit at 0xC3 T3IF; /* Timer 3 interrupt flag. Automatically cleared */
145 sbit at 0xC4 T4IF; /* Timer 4 interrupt flag. Automatically cleared */
146 sbit at 0xC5 P0IF; /* Port0 interrupt flag */
147 sbit at 0xC7 STIF; /* Sleep Timer interrupt flag */
149 #define IRCON_DMAIF (1 << 0) /* DMA complete interrupt flag */
150 #define IRCON_T1IF (1 << 1) /* Timer 1 interrupt flag. Automatically cleared */
151 #define IRCON_T2IF (1 << 2) /* Timer 2 interrupt flag. Automatically cleared */
152 #define IRCON_T3IF (1 << 3) /* Timer 3 interrupt flag. Automatically cleared */
153 #define IRCON_T4IF (1 << 4) /* Timer 4 interrupt flag. Automatically cleared */
154 #define IRCON_P0IF (1 << 5) /* Port0 interrupt flag */
155 #define IRCON_STIF (1 << 7) /* Sleep Timer interrupt flag */
160 sfr at 0xE8 IRCON2; /* CPU Interrupt Flag 5 */
162 sbit at 0xE8 USBIF; /* USB interrupt flag (shared with Port2) */
163 sbit at 0xE8 P2IF; /* Port2 interrupt flag (shared with USB) */
164 sbit at 0xE9 UTX0IF; /* USART0 TX interrupt flag */
165 sbit at 0xEA UTX1IF; /* USART1 TX interrupt flag (shared with I2S TX) */
166 sbit at 0xEA I2STXIF; /* I2S TX interrupt flag (shared with USART1 TX) */
167 sbit at 0xEB P1IF; /* Port1 interrupt flag */
168 sbit at 0xEC WDTIF; /* Watchdog timer interrupt flag */
170 #define IRCON2_USBIF (1 << 0) /* USB interrupt flag (shared with Port2) */
171 #define IRCON2_P2IF (1 << 0) /* Port2 interrupt flag (shared with USB) */
172 #define IRCON2_UTX0IF (1 << 1) /* USART0 TX interrupt flag */
173 #define IRCON2_UTX1IF (1 << 2) /* USART1 TX interrupt flag (shared with I2S TX) */
174 #define IRCON2_I2STXIF (1 << 2) /* I2S TX interrupt flag (shared with USART1 TX) */
175 #define IRCON2_P1IF (1 << 3) /* Port1 interrupt flag */
176 #define IRCON2_WDTIF (1 << 4) /* Watchdog timer interrupt flag */
179 * IP1 - Interrupt Priority 1
183 * Interrupt priority groups:
186 * IPG1 ADC T1 P2INT/USB
188 * IPG3 URX1/I2SRX T3 UTX1 / I2STX
192 * Priority = (IP1 << 1) | IP0. Higher priority interrupts served first
195 sfr at 0xB9 IP1; /* Interrupt Priority 1 */
196 sfr at 0xA9 IP0; /* Interrupt Priority 0 */
198 #define IP1_IPG5 (1 << 5)
199 #define IP1_IPG4 (1 << 4)
200 #define IP1_IPG3 (1 << 3)
201 #define IP1_IPG2 (1 << 2)
202 #define IP1_IPG1 (1 << 1)
203 #define IP1_IPG0 (1 << 0)
205 #define IP0_IPG5 (1 << 5)
206 #define IP0_IPG4 (1 << 4)
207 #define IP0_IPG3 (1 << 3)
208 #define IP0_IPG2 (1 << 2)
209 #define IP0_IPG1 (1 << 1)
210 #define IP0_IPG0 (1 << 0)
215 #define T1CTL_MODE_SUSPENDED (0 << 0)
216 #define T1CTL_MODE_FREE (1 << 0)
217 #define T1CTL_MODE_MODULO (2 << 0)
218 #define T1CTL_MODE_UP_DOWN (3 << 0)
219 #define T1CTL_MODE_MASK (3 << 0)
220 #define T1CTL_DIV_1 (0 << 2)
221 #define T1CTL_DIV_8 (1 << 2)
222 #define T1CTL_DIV_32 (2 << 2)
223 #define T1CTL_DIV_128 (3 << 2)
224 #define T1CTL_DIV_MASK (3 << 2)
225 #define T1CTL_OVFIF (1 << 4)
226 #define T1CTL_CH0IF (1 << 5)
227 #define T1CTL_CH1IF (1 << 6)
228 #define T1CTL_CH2IF (1 << 7)
230 #define T1CCTL_NO_CAPTURE (0 << 0)
231 #define T1CCTL_CAPTURE_RISING (1 << 0)
232 #define T1CCTL_CAPTURE_FALLING (2 << 0)
233 #define T1CCTL_CAPTURE_BOTH (3 << 0)
234 #define T1CCTL_CAPTURE_MASK (3 << 0)
236 #define T1CCTL_MODE_CAPTURE (0 << 2)
237 #define T1CCTL_MODE_COMPARE (1 << 2)
239 #define T1CTL_CMP_SET (0 << 3)
240 #define T1CTL_CMP_CLEAR (1 << 3)
241 #define T1CTL_CMP_TOGGLE (2 << 3)
242 #define T1CTL_CMP_SET_CLEAR (3 << 3)
243 #define T1CTL_CMP_CLEAR_SET (4 << 3)
245 #define T1CTL_IM_DISABLED (0 << 6)
246 #define T1CTL_IM_ENABLED (1 << 6)
248 #define T1CTL_CPSEL_NORMAL (0 << 7)
249 #define T1CTL_CPSEL_RF (1 << 7)
252 * Timer 3 and Timer 4
264 #define TxCTL_DIV_1 (0 << 5)
265 #define TxCTL_DIV_2 (1 << 5)
266 #define TxCTL_DIV_4 (2 << 5)
267 #define TxCTL_DIV_8 (3 << 5)
268 #define TxCTL_DIV_16 (4 << 5)
269 #define TxCTL_DIV_32 (5 << 5)
270 #define TxCTL_DIV_64 (6 << 5)
271 #define TxCTL_DIV_128 (7 << 5)
272 #define TxCTL_START (1 << 4)
273 #define TxCTL_OVFIM (1 << 3)
274 #define TxCTL_CLR (1 << 2)
275 #define TxCTL_MODE_FREE (0 << 0)
276 #define TxCTL_MODE_DOWN (1 << 0)
277 #define TxCTL_MODE_MODULO (2 << 0)
278 #define TxCTL_MODE_UP_DOWN (3 << 0)
280 /* Timer 4 channel 0 compare control */
287 #define TxCCTLy_IM (1 << 6)
288 #define TxCCTLy_CMP_SET (0 << 3)
289 #define TxCCTLy_CMP_CLEAR (1 << 3)
290 #define TxCCTLy_CMP_TOGGLE (2 << 3)
291 #define TxCCTLy_CMP_SET_UP_CLEAR_DOWN (3 << 3)
292 #define TxCCTLy_CMP_CLEAR_UP_SET_DOWN (4 << 3)
293 #define TxCCTLy_CMP_SET_CLEAR_FF (5 << 3)
294 #define TxCCTLy_CMP_CLEAR_SET_00 (6 << 3)
295 #define TxCCTLy_CMP_MODE_ENABLE (1 << 2)
297 /* Timer compare value */
308 #define PERCFG_T1CFG_ALT_1 (0 << 6)
309 #define PERCFG_T1CFG_ALT_2 (1 << 6)
310 #define PERCFG_T1CFG_ALT_MASK (1 << 6)
312 #define PERCFG_T3CFG_ALT_1 (0 << 5)
313 #define PERCFG_T3CFG_ALT_2 (1 << 5)
314 #define PERCFG_T3CFG_ALT_MASK (1 << 5)
316 #define PERCFG_T4CFG_ALT_1 (0 << 4)
317 #define PERCFG_T4CFG_ALT_2 (1 << 4)
318 #define PERCFG_T4CFG_ALT_MASK (1 << 4)
320 #define PERCFG_U1CFG_ALT_1 (0 << 1)
321 #define PERCFG_U1CFG_ALT_2 (1 << 1)
322 #define PERCFG_U1CFG_ALT_MASK (1 << 1)
324 #define PERCFG_U0CFG_ALT_1 (0 << 0)
325 #define PERCFG_U0CFG_ALT_2 (1 << 0)
326 #define PERCFG_U0CFG_ALT_MASK (1 << 0)
328 /* directly addressed USB registers */
329 __xdata __at (0xde00) volatile uint8_t USBADDR;
330 __xdata __at (0xde01) volatile uint8_t USBPOW;
331 __xdata __at (0xde02) volatile uint8_t USBIIF;
333 __xdata __at (0xde04) volatile uint8_t USBOIF;
335 __xdata __at (0xde06) volatile uint8_t USBCIF;
336 __xdata __at (0xde07) volatile uint8_t USBIIE;
338 __xdata __at (0xde09) volatile uint8_t USBOIE;
340 __xdata __at (0xde0b) volatile uint8_t USBCIE;
342 # define USBCIE_SOFIE (1 << 3)
343 # define USBCIE_RSTIE (1 << 2)
344 # define USBCIE_RESUMEIE (1 << 1)
345 # define USBCIE_SUSPENDIE (1 << 0)
347 __xdata __at (0xde0c) volatile uint8_t USBFRML;
348 __xdata __at (0xde0d) volatile uint8_t USBFRMH;
349 __xdata __at (0xde0e) volatile uint8_t USBINDEX;
351 /* indexed USB registers, must set USBINDEX to 0-5 */
352 __xdata __at (0xde10) volatile uint8_t USBMAXI;
353 __xdata __at (0xde11) volatile uint8_t USBCS0;
355 # define USBCS0_CLR_SETUP_END (1 << 7)
356 # define USBCS0_CLR_OUTPKT_RDY (1 << 6)
357 # define USBCS0_SEND_STALL (1 << 5)
358 # define USBCS0_SETUP_END (1 << 4)
359 # define USBCS0_DATA_END (1 << 3)
360 # define USBCS0_SENT_STALL (1 << 2)
361 # define USBCS0_INPKT_RDY (1 << 1)
362 # define USBCS0_OUTPKT_RDY (1 << 0)
364 __xdata __at (0xde11) volatile uint8_t USBCSIL;
366 # define USBCSIL_CLR_DATA_TOG (1 << 6)
367 # define USBCSIL_SENT_STALL (1 << 5)
368 # define USBCSIL_SEND_STALL (1 << 4)
369 # define USBCSIL_FLUSH_PACKET (1 << 3)
370 # define USBCSIL_UNDERRUN (1 << 2)
371 # define USBCSIL_PKT_PRESENT (1 << 1)
372 # define USBCSIL_INPKT_RDY (1 << 0)
374 __xdata __at (0xde12) volatile uint8_t USBCSIH;
376 # define USBCSIH_AUTOSET (1 << 7)
377 # define USBCSIH_ISO (1 << 6)
378 # define USBCSIH_FORCE_DATA_TOG (1 << 3)
379 # define USBCSIH_IN_DBL_BUF (1 << 0)
381 __xdata __at (0xde13) volatile uint8_t USBMAXO;
382 __xdata __at (0xde14) volatile uint8_t USBCSOL;
384 # define USBCSOL_CLR_DATA_TOG (1 << 7)
385 # define USBCSOL_SENT_STALL (1 << 6)
386 # define USBCSOL_SEND_STALL (1 << 5)
387 # define USBCSOL_FLUSH_PACKET (1 << 4)
388 # define USBCSOL_DATA_ERROR (1 << 3)
389 # define USBCSOL_OVERRUN (1 << 2)
390 # define USBCSOL_FIFO_FULL (1 << 1)
391 # define USBCSOL_OUTPKT_RDY (1 << 0)
393 __xdata __at (0xde15) volatile uint8_t USBCSOH;
395 # define USBCSOH_AUTOCLEAR (1 << 7)
396 # define USBCSOH_ISO (1 << 6)
397 # define USBCSOH_OUT_DBL_BUF (1 << 0)
399 __xdata __at (0xde16) volatile uint8_t USBCNT0;
400 __xdata __at (0xde16) volatile uint8_t USBCNTL;
401 __xdata __at (0xde17) volatile uint8_t USBCNTH;
403 __xdata __at (0xde20) volatile uint8_t USBFIFO[12];
405 /* ADC Data register, low and high */
408 __xdata __at (0xDFBA) volatile uint16_t ADCXDATA;
410 /* ADC Control Register 1 */
413 # define ADCCON1_EOC (1 << 7) /* conversion complete */
414 # define ADCCON1_ST (1 << 6) /* start conversion */
416 # define ADCCON1_STSEL_MASK (3 << 4) /* start select */
417 # define ADCCON1_STSEL_EXTERNAL (0 << 4) /* P2_0 pin triggers */
418 # define ADCCON1_STSEL_FULLSPEED (1 << 4) /* full speed, no waiting */
419 # define ADCCON1_STSEL_TIMER1 (2 << 4) /* timer 1 channel 0 */
420 # define ADCCON1_STSEL_START (3 << 4) /* set start bit */
422 # define ADCCON1_RCTRL_MASK (3 << 2) /* random number control */
423 # define ADCCON1_RCTRL_COMPLETE (0 << 2) /* operation completed */
424 # define ADCCON1_RCTRL_CLOCK_LFSR (1 << 2) /* Clock the LFSR once */
426 /* ADC Control Register 2 */
429 # define ADCCON2_SREF_MASK (3 << 6) /* reference voltage */
430 # define ADCCON2_SREF_1_25V (0 << 6) /* internal 1.25V */
431 # define ADCCON2_SREF_EXTERNAL (1 << 6) /* external on AIN7 cc1110 */
432 # define ADCCON2_SREF_VDD (2 << 6) /* VDD on the AVDD pin */
433 # define ADCCON2_SREF_EXTERNAL_DIFF (3 << 6) /* external on AIN6-7 cc1110 */
435 # define ADCCON2_SDIV_MASK (3 << 4) /* decimation rate */
436 # define ADCCON2_SDIV_64 (0 << 4) /* 7 bits */
437 # define ADCCON2_SDIV_128 (1 << 4) /* 9 bits */
438 # define ADCCON2_SDIV_256 (2 << 4) /* 10 bits */
439 # define ADCCON2_SDIV_512 (3 << 4) /* 12 bits */
441 # define ADCCON2_SCH_MASK (0xf << 0) /* Sequence channel select */
442 # define ADCCON2_SCH_SHIFT 0
443 # define ADCCON2_SCH_AIN0 (0 << 0)
444 # define ADCCON2_SCH_AIN1 (1 << 0)
445 # define ADCCON2_SCH_AIN2 (2 << 0)
446 # define ADCCON2_SCH_AIN3 (3 << 0)
447 # define ADCCON2_SCH_AIN4 (4 << 0)
448 # define ADCCON2_SCH_AIN5 (5 << 0)
449 # define ADCCON2_SCH_AIN6 (6 << 0)
450 # define ADCCON2_SCH_AIN7 (7 << 0)
451 # define ADCCON2_SCH_AIN0_AIN1 (8 << 0)
452 # define ADCCON2_SCH_AIN2_AIN3 (9 << 0)
453 # define ADCCON2_SCH_AIN4_AIN5 (0xa << 0)
454 # define ADCCON2_SCH_AIN6_AIN7 (0xb << 0)
455 # define ADCCON2_SCH_GND (0xc << 0)
456 # define ADCCON2_SCH_VREF (0xd << 0)
457 # define ADCCON2_SCH_TEMP (0xe << 0)
458 # define ADCCON2_SCH_VDD_3 (0xf << 0)
461 /* ADC Control Register 3 */
464 # define ADCCON3_EREF_MASK (3 << 6) /* extra conversion reference */
465 # define ADCCON3_EREF_1_25 (0 << 6) /* internal 1.25V */
466 # define ADCCON3_EREF_EXTERNAL (1 << 6) /* external AIN7 cc1110 */
467 # define ADCCON3_EREF_VDD (2 << 6) /* VDD on the AVDD pin */
468 # define ADCCON3_EREF_EXTERNAL_DIFF (3 << 6) /* external AIN6-7 cc1110 */
469 # define ADCCON3_EDIV_MASK (3 << 4) /* extral decimation */
470 # define ADCCON3_EDIV_64 (0 << 4) /* 7 bits */
471 # define ADCCON3_EDIV_128 (1 << 4) /* 9 bits */
472 # define ADCCON3_EDIV_256 (2 << 4) /* 10 bits */
473 # define ADCCON3_EDIV_512 (3 << 4) /* 12 bits */
474 # define ADCCON3_ECH_MASK (0xf << 0) /* Sequence channel select */
475 # define ADCCON3_ECH_SHIFT 0
476 # define ADCCON3_ECH_AIN0 (0 << 0)
477 # define ADCCON3_ECH_AIN1 (1 << 0)
478 # define ADCCON3_ECH_AIN2 (2 << 0)
479 # define ADCCON3_ECH_AIN3 (3 << 0)
480 # define ADCCON3_ECH_AIN4 (4 << 0)
481 # define ADCCON3_ECH_AIN5 (5 << 0)
482 # define ADCCON3_ECH_AIN6 (6 << 0)
483 # define ADCCON3_ECH_AIN7 (7 << 0)
484 # define ADCCON3_ECH_AIN0_AIN1 (8 << 0)
485 # define ADCCON3_ECH_AIN2_AIN3 (9 << 0)
486 # define ADCCON3_ECH_AIN4_AIN5 (0xa << 0)
487 # define ADCCON3_ECH_AIN6_AIN7 (0xb << 0)
488 # define ADCCON3_ECH_GND (0xc << 0)
489 # define ADCCON3_ECH_VREF (0xd << 0)
490 # define ADCCON3_ECH_TEMP (0xe << 0)
491 # define ADCCON3_ECH_VDD_3 (0xf << 0)
494 * ADC configuration register, this selects which
495 * GPIO pins are to be used as ADC inputs
500 * Pin selectors, these set which pins are
501 * using their peripheral function
507 #define P2SEL_PRI3P1_USART0 (0 << 6)
508 #define P2SEL_PRI3P1_USART1 (1 << 6)
509 #define P2SEL_PRI3P1_MASK (1 << 6)
510 #define P2SEL_PRI2P1_USART1 (0 << 5)
511 #define P2SEL_PRI2P1_TIMER3 (1 << 5)
512 #define P2SEL_PRI1P1_TIMER1 (0 << 4)
513 #define P2SEL_PRI1P1_TIMER4 (1 << 4)
514 #define P2SEL_PRI0P1_USART0 (0 << 3)
515 #define P2SEL_PRI0P1_TIMER1 (1 << 3)
516 #define P2SEL_SELP2_4_GPIO (0 << 2)
517 #define P2SEL_SELP2_4_PERIPHERAL (1 << 2)
518 #define P2SEL_SELP2_3_GPIO (0 << 1)
519 #define P2SEL_SELP2_3_PERIPHERAL (1 << 1)
520 #define P2SEL_SELP2_0_GPIO (0 << 0)
521 #define P2SEL_SELP2_0_PERIPHERAL (1 << 0)
522 #define P2SEL_SELP2_0_MASK (1 << 0)
525 * For pins used as GPIOs, these set which are used as outputs
533 /* Select between tri-state and pull up/down
534 * for pins P0_0 - P0_7.
536 #define P0INP_MDP0_7_PULL (0 << 7)
537 #define P0INP_MDP0_7_TRISTATE (1 << 7)
538 #define P0INP_MDP0_6_PULL (0 << 6)
539 #define P0INP_MDP0_6_TRISTATE (1 << 6)
540 #define P0INP_MDP0_5_PULL (0 << 5)
541 #define P0INP_MDP0_5_TRISTATE (1 << 5)
542 #define P0INP_MDP0_4_PULL (0 << 4)
543 #define P0INP_MDP0_4_TRISTATE (1 << 4)
544 #define P0INP_MDP0_3_PULL (0 << 3)
545 #define P0INP_MDP0_3_TRISTATE (1 << 3)
546 #define P0INP_MDP0_2_PULL (0 << 2)
547 #define P0INP_MDP0_2_TRISTATE (1 << 2)
548 #define P0INP_MDP0_1_PULL (0 << 1)
549 #define P0INP_MDP0_1_TRISTATE (1 << 1)
550 #define P0INP_MDP0_0_PULL (0 << 0)
551 #define P0INP_MDP0_0_TRISTATE (1 << 0)
555 /* Select between tri-state and pull up/down
556 * for pins P1_2 - P1_7. Pins P1_0 and P1_1 are
559 #define P1INP_MDP1_7_PULL (0 << 7)
560 #define P1INP_MDP1_7_TRISTATE (1 << 7)
561 #define P1INP_MDP1_6_PULL (0 << 6)
562 #define P1INP_MDP1_6_TRISTATE (1 << 6)
563 #define P1INP_MDP1_5_PULL (0 << 5)
564 #define P1INP_MDP1_5_TRISTATE (1 << 5)
565 #define P1INP_MDP1_4_PULL (0 << 4)
566 #define P1INP_MDP1_4_TRISTATE (1 << 4)
567 #define P1INP_MDP1_3_PULL (0 << 3)
568 #define P1INP_MDP1_3_TRISTATE (1 << 3)
569 #define P1INP_MDP1_2_PULL (0 << 2)
570 #define P1INP_MDP1_2_TRISTATE (1 << 2)
573 /* P2INP has three extra bits which are used to choose
574 * between pull-up and pull-down when they are not tri-stated
576 #define P2INP_PDUP2_PULL_UP (0 << 7)
577 #define P2INP_PDUP2_PULL_DOWN (1 << 7)
578 #define P2INP_PDUP1_PULL_UP (0 << 6)
579 #define P2INP_PDUP1_PULL_DOWN (1 << 6)
580 #define P2INP_PDUP0_PULL_UP (0 << 5)
581 #define P2INP_PDUP0_PULL_DOWN (1 << 5)
583 /* For the P2 pins, choose between tri-state and pull up/down
586 #define P2INP_MDP2_4_PULL (0 << 4)
587 #define P2INP_MDP2_4_TRISTATE (1 << 4)
588 #define P2INP_MDP2_3_PULL (0 << 3)
589 #define P2INP_MDP2_3_TRISTATE (1 << 3)
590 #define P2INP_MDP2_2_PULL (0 << 2)
591 #define P2INP_MDP2_2_TRISTATE (1 << 2)
592 #define P2INP_MDP2_1_PULL (0 << 1)
593 #define P2INP_MDP2_1_TRISTATE (1 << 1)
594 #define P2INP_MDP2_0_PULL (0 << 0)
595 #define P2INP_MDP2_0_TRISTATE (1 << 0)
597 /* GPIO interrupt status flags */
602 #define P0IFG_USB_RESUME (1 << 7)
639 struct cc_dma_channel {
650 # define DMA_LEN_HIGH_VLEN_MASK (7 << 5)
651 # define DMA_LEN_HIGH_VLEN_LEN (0 << 5)
652 # define DMA_LEN_HIGH_VLEN_PLUS_1 (1 << 5)
653 # define DMA_LEN_HIGH_VLEN (2 << 5)
654 # define DMA_LEN_HIGH_VLEN_PLUS_2 (3 << 5)
655 # define DMA_LEN_HIGH_VLEN_PLUS_3 (4 << 5)
656 # define DMA_LEN_HIGH_MASK (0x1f)
658 # define DMA_CFG0_WORDSIZE_8 (0 << 7)
659 # define DMA_CFG0_WORDSIZE_16 (1 << 7)
660 # define DMA_CFG0_TMODE_MASK (3 << 5)
661 # define DMA_CFG0_TMODE_SINGLE (0 << 5)
662 # define DMA_CFG0_TMODE_BLOCK (1 << 5)
663 # define DMA_CFG0_TMODE_REPEATED_SINGLE (2 << 5)
664 # define DMA_CFG0_TMODE_REPEATED_BLOCK (3 << 5)
669 # define DMA_CFG0_TRIGGER_NONE 0
670 # define DMA_CFG0_TRIGGER_PREV 1
671 # define DMA_CFG0_TRIGGER_T1_CH0 2
672 # define DMA_CFG0_TRIGGER_T1_CH1 3
673 # define DMA_CFG0_TRIGGER_T1_CH2 4
674 # define DMA_CFG0_TRIGGER_T2_OVFL 6
675 # define DMA_CFG0_TRIGGER_T3_CH0 7
676 # define DMA_CFG0_TRIGGER_T3_CH1 8
677 # define DMA_CFG0_TRIGGER_T4_CH0 9
678 # define DMA_CFG0_TRIGGER_T4_CH1 10
679 # define DMA_CFG0_TRIGGER_IOC_0 12
680 # define DMA_CFG0_TRIGGER_IOC_1 13
681 # define DMA_CFG0_TRIGGER_URX0 14
682 # define DMA_CFG0_TRIGGER_UTX0 15
683 # define DMA_CFG0_TRIGGER_URX1 16
684 # define DMA_CFG0_TRIGGER_UTX1 17
685 # define DMA_CFG0_TRIGGER_FLASH 18
686 # define DMA_CFG0_TRIGGER_RADIO 19
687 # define DMA_CFG0_TRIGGER_ADC_CHALL 20
688 # define DMA_CFG0_TRIGGER_ADC_CH0 21
689 # define DMA_CFG0_TRIGGER_ADC_CH1 22
690 # define DMA_CFG0_TRIGGER_ADC_CH2 23
691 # define DMA_CFG0_TRIGGER_ADC_CH3 24
692 # define DMA_CFG0_TRIGGER_ADC_CH4 25
693 # define DMA_CFG0_TRIGGER_ADC_CH5 26
694 # define DMA_CFG0_TRIGGER_ADC_CH6 27
695 # define DMA_CFG0_TRIGGER_I2SRX 27
696 # define DMA_CFG0_TRIGGER_ADC_CH7 28
697 # define DMA_CFG0_TRIGGER_I2STX 28
698 # define DMA_CFG0_TRIGGER_ENC_DW 29
699 # define DMA_CFG0_TRIGGER_DNC_UP 30
701 # define DMA_CFG1_SRCINC_MASK (3 << 6)
702 # define DMA_CFG1_SRCINC_0 (0 << 6)
703 # define DMA_CFG1_SRCINC_1 (1 << 6)
704 # define DMA_CFG1_SRCINC_2 (2 << 6)
705 # define DMA_CFG1_SRCINC_MINUS_1 (3 << 6)
707 # define DMA_CFG1_DESTINC_MASK (3 << 4)
708 # define DMA_CFG1_DESTINC_0 (0 << 4)
709 # define DMA_CFG1_DESTINC_1 (1 << 4)
710 # define DMA_CFG1_DESTINC_2 (2 << 4)
711 # define DMA_CFG1_DESTINC_MINUS_1 (3 << 4)
713 # define DMA_CFG1_IRQMASK (1 << 3)
714 # define DMA_CFG1_M8 (1 << 2)
716 # define DMA_CFG1_PRIORITY_MASK (3 << 0)
717 # define DMA_CFG1_PRIORITY_LOW (0 << 0)
718 # define DMA_CFG1_PRIORITY_NORMAL (1 << 0)
719 # define DMA_CFG1_PRIORITY_HIGH (2 << 0)
722 * DMAARM - DMA Channel Arm
727 # define DMAARM_ABORT (1 << 7)
728 # define DMAARM_DMAARM4 (1 << 4)
729 # define DMAARM_DMAARM3 (1 << 3)
730 # define DMAARM_DMAARM2 (1 << 2)
731 # define DMAARM_DMAARM1 (1 << 1)
732 # define DMAARM_DMAARM0 (1 << 0)
735 * DMAREQ - DMA Channel Start Request and Status
740 # define DMAREQ_DMAREQ4 (1 << 4)
741 # define DMAREQ_DMAREQ3 (1 << 3)
742 # define DMAREQ_DMAREQ2 (1 << 2)
743 # define DMAREQ_DMAREQ1 (1 << 1)
744 # define DMAREQ_DMAREQ0 (1 << 0)
747 * DMA configuration 0 address
750 sfr at 0xD5 DMA0CFGH;
751 sfr at 0xD4 DMA0CFGL;
754 * DMA configuration 1-4 address
757 sfr at 0xD3 DMA1CFGH;
758 sfr at 0xD2 DMA1CFGL;
761 * DMAIRQ - DMA Interrupt Flag
766 # define DMAIRQ_DMAIF4 (1 << 4)
767 # define DMAIRQ_DMAIF3 (1 << 3)
768 # define DMAIRQ_DMAIF2 (1 << 2)
769 # define DMAIRQ_DMAIF1 (1 << 1)
770 # define DMAIRQ_DMAIF0 (1 << 0)
776 /* USART config/status registers */
780 # define UxCSR_MODE_UART (1 << 7)
781 # define UxCSR_MODE_SPI (0 << 7)
782 # define UxCSR_RE (1 << 6)
783 # define UxCSR_SLAVE (1 << 5)
784 # define UxCSR_MASTER (0 << 5)
785 # define UxCSR_FE (1 << 4)
786 # define UxCSR_ERR (1 << 3)
787 # define UxCSR_RX_BYTE (1 << 2)
788 # define UxCSR_TX_BYTE (1 << 1)
789 # define UxCSR_ACTIVE (1 << 0)
791 /* UART configuration registers */
795 # define UxUCR_FLUSH (1 << 7)
796 # define UxUCR_FLOW_DISABLE (0 << 6)
797 # define UxUCR_FLOW_ENABLE (1 << 6)
798 # define UxUCR_D9_EVEN_PARITY (0 << 5)
799 # define UxUCR_D9_ODD_PARITY (1 << 5)
800 # define UxUCR_BIT9_8_BITS (0 << 4)
801 # define UxUCR_BIT9_9_BITS (1 << 4)
802 # define UxUCR_PARITY_DISABLE (0 << 3)
803 # define UxUCR_PARITY_ENABLE (1 << 3)
804 # define UxUCR_SPB_1_STOP_BIT (0 << 2)
805 # define UxUCR_SPB_2_STOP_BITS (1 << 2)
806 # define UxUCR_STOP_LOW (0 << 1)
807 # define UxUCR_STOP_HIGH (1 << 1)
808 # define UxUCR_START_LOW (0 << 0)
809 # define UxUCR_START_HIGH (1 << 0)
811 /* USART General configuration registers (mostly SPI) */
815 # define UxGCR_CPOL_NEGATIVE (0 << 7)
816 # define UxGCR_CPOL_POSITIVE (1 << 7)
817 # define UxGCR_CPHA_FIRST_EDGE (0 << 6)
818 # define UxGCR_CPHA_SECOND_EDGE (1 << 6)
819 # define UxGCR_ORDER_LSB (0 << 5)
820 # define UxGCR_ORDER_MSB (1 << 5)
821 # define UxGCR_BAUD_E_MASK (0x1f)
822 # define UxGCR_BAUD_E_SHIFT 0
824 /* USART data registers */
826 __xdata __at (0xDFC1) volatile uint8_t U0DBUFXADDR;
828 __xdata __at (0xDFF9) volatile uint8_t U1DBUFXADDR;
830 /* USART baud rate registers, M value */