2 * Copyright © 2008 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
22 * Validate the SPI-connected EEPROM
31 # define SLEEP_USB_EN (1 << 7)
32 # define SLEEP_XOSC_STB (1 << 6)
35 #define PERCFG_T1CFG_ALT_1 (0 << 6)
36 #define PERCFG_T1CFG_ALT_2 (1 << 6)
38 #define PERCFG_T3CFG_ALT_1 (0 << 5)
39 #define PERCFG_T3CFG_ALT_2 (1 << 5)
41 #define PERCFG_T4CFG_ALT_1 (0 << 4)
42 #define PERCFG_T4CFG_ALT_2 (1 << 4)
44 #define PERCFG_U1CFG_ALT_1 (0 << 1)
45 #define PERCFG_U1CFG_ALT_2 (1 << 1)
47 #define PERCFG_U0CFG_ALT_1 (0 << 0)
48 #define PERCFG_U0CFG_ALT_2 (1 << 0)
82 # define UxCSR_MODE_UART (1 << 7)
83 # define UxCSR_MODE_SPI (0 << 7)
84 # define UxCSR_RE (1 << 6)
85 # define UxCSR_SLAVE (1 << 5)
86 # define UxCSR_MASTER (0 << 5)
87 # define UxCSR_FE (1 << 4)
88 # define UxCSR_ERR (1 << 3)
89 # define UxCSR_RX_BYTE (1 << 2)
90 # define UxCSR_TX_BYTE (1 << 1)
91 # define UxCSR_ACTIVE (1 << 0)
99 # define UxGCR_CPOL_NEGATIVE (0 << 7)
100 # define UxGCR_CPOL_POSITIVE (1 << 7)
101 # define UxGCR_CPHA_FIRST_EDGE (0 << 6)
102 # define UxGCR_CPHA_SECOND_EDGE (1 << 6)
103 # define UxGCR_ORDER_LSB (0 << 5)
104 # define UxGCR_ORDER_MSB (1 << 5)
105 # define UxGCR_BAUD_E_MASK (0x1f)
106 # define UxGCR_BAUD_E_SHIFT 0
123 #define nop() _asm nop _endasm;
126 delay (unsigned char n)
140 * This version directly manipulates the GPIOs to synthesize SPI
144 bitbang_cs(uint8_t b)
152 bitbang_out_bit(uint8_t b)
162 bitbang_out_byte(uint8_t byte)
166 for (s = 0; s < 8; s++) {
167 uint8_t b = (byte & 0x80) ? 1 : 0;
187 bitbang_in_byte(void)
193 for (s = 0; s < 8; s++) {
194 b = bitbang_in_bit();
213 #define spi_init() bitbang_init()
214 #define spi_out_byte(b) bitbang_out_byte(b)
215 #define spi_in_byte() bitbang_in_byte()
216 #define spi_cs(b) bitbang_cs(b)
222 * This version uses the USART in SPI mode
228 * Configure our chip select line
233 * Configure the peripheral pin choices
234 * for both of the serial ports
236 * Note that telemetrum will use U1CFG_ALT_2
237 * but that overlaps with SPI ALT_2, so until
238 * we can test that this works, we'll set this
241 PERCFG = (PERCFG_U1CFG_ALT_1 |
245 * Make the SPI pins controlled by the SPI
248 P1SEL |= ((1 << 5) | (1 << 4) | (1 << 3));
253 U0CSR = (UxCSR_MODE_SPI |
257 * The cc1111 is limited to a 24/8 MHz SPI clock,
258 * while the 25LC1024 is limited to 20MHz. So,
259 * use the 3MHz clock (BAUD_E 17, BAUD_M 0)
262 U0GCR = (UxGCR_CPOL_NEGATIVE |
263 UxGCR_CPHA_FIRST_EDGE |
265 (17 << UxGCR_BAUD_E_SHIFT));
275 usart_in_out(uint8_t byte)
278 while ((U0CSR & UxCSR_TX_BYTE) == 0)
280 U0CSR &= ~UxCSR_TX_BYTE;
285 usart_out_byte(uint8_t byte)
287 (void) usart_in_out(byte);
293 return usart_in_out(0xff);
296 #define spi_init() usart_init()
297 #define spi_out_byte(b) usart_out_byte(b)
298 #define spi_in_byte() usart_in_byte()
299 #define spi_cs(b) usart_cs(b)
309 status = spi_in_byte();
319 spi_out_byte(status);
332 write(uint32_t addr, uint8_t *bytes, uint16_t len)
337 spi_out_byte(addr >> 16);
338 spi_out_byte(addr >> 8);
341 spi_out_byte(*bytes++);
344 uint8_t status = rdsr();
345 if ((status & (1 << 0)) == 0)
351 read(uint32_t addr, uint8_t *bytes, uint16_t len)
355 spi_out_byte(addr >> 16);
356 spi_out_byte(addr >> 8);
359 *bytes++ = spi_in_byte();
364 debug_byte(uint8_t byte)
368 for (s = 0; s < 8; s++) {
375 #define STRING "\360\252"
386 while (!(SLEEP & SLEEP_XOSC_STB))
393 * Turn off both block-protect bits
395 status &= ~((1 << 3) | (1 << 2));
397 * Turn off write protect enable
401 write(0x0, STRING, LENGTH);
403 read(0x0, buf, LENGTH);
404 for (i = 0; i < LENGTH; i++)