2 * Copyright © 2011 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
19 #include <avr/interrupt.h>
22 #define F_CPU 16000000UL // 16 MHz
24 #define F_CPU 8000000UL // 8 MHz
26 #include <util/delay.h>
36 ISR(TIMER1_COMPA_vect)
44 TCCR1A = ((0 << WGM11) | /* CTC mode, OCR1A */
45 (0 << WGM10)); /* CTC mode, OCR1A */
46 TCCR1B = ((0 << ICNC1) | /* no input capture noise canceler */
47 (0 << ICES1) | /* input capture on falling edge (don't care) */
48 (0 << WGM13) | /* CTC mode, OCR1A */
49 (1 << WGM12) | /* CTC mode, OCR1A */
50 (3 << CS10)); /* clk/64 from prescaler */
53 OCR1A = 2500; /* 16MHz clock */
55 OCR1A = 1250; /* 8MHz clock */
58 TIMSK1 = (1 << OCIE1A); /* Interrupt on compare match */
64 /* disable RC clock */
65 CLKSEL0 &= ~(1 << RCE);
68 PLLCSR &= ~(1 << PLLE);
70 /* Enable external clock */
71 CLKSEL0 |= (1 << EXTE);
73 /* wait for external clock to be ready */
74 while ((CLKSTA & (1 << EXTON)) == 0)
77 /* select external clock */
78 CLKSEL0 |= (1 << CLKS);
80 /* Disable the clock prescaler */
82 CLKPR = (1 << CLKPCE);
86 /* Set up the PLL to use the crystal */
88 /* Use primary system clock as PLL source */
89 PLLFRQ = ((0 << PINMUX) | /* Use primary clock */
90 (0 << PLLUSB) | /* No divide by 2 for USB */
91 (0 << PLLTM0) | /* Disable high speed timer */
92 (0x4 << PDIV0)); /* 48MHz PLL clock */
94 /* Set the frequency of the crystal */
96 PLLCSR |= (1 << PINDIV); /* For 16MHz crystal on Teensy board */
98 PLLCSR &= ~(1 << PINDIV); /* For 8MHz crystal on TeleScience board */
102 PLLCSR |= (1 << PLLE);
103 while (!(PLLCSR & (1 << PLOCK)))
110 TCCR0A = ((1 << COM0A1) |
119 TCCR0B = ((0 << WGM02) |
128 #define ADC_CHANNEL 0x25 /* Channel ADC13 */
129 #define ADC_CHANNEL_LOW(c) (((c) & 0x1f) << MUX0)
130 #define ADC_CHANNEL_HIGH(c) ((((c) & 0x20) >> 5) << MUX5)
132 #define ADCSRA_INIT ((1 << ADEN) | /* Enable ADC */ \
133 (0 << ADATE) | /* No auto ADC trigger */ \
134 (1 << ADIE) | /* Enable interrupt */ \
135 (6 << ADPS0)) /* Prescale clock by 64 */
137 #define ADCSRB_INIT ((0 << ADHSM) | /* No high-speed mode */ \
138 (0 << ACME) | /* Some comparitor thing */ \
139 (0 << ADTS0)) /* Free running mode (don't care) */
144 ADMUX = ((0 << REFS1) | /* AVcc reference */
145 (1 << REFS0) | /* AVcc reference */
146 (1 << ADLAR) | /* Left-shift results */
147 (ADC_CHANNEL_LOW(ADC_CHANNEL))); /* Select channel */
149 ADCSRB = ADCSRB_INIT | ADC_CHANNEL_HIGH(ADC_CHANNEL);
151 ADCSRA = ADCSRA_INIT | (1 << ADSC); /* Start conversion */
157 ADCSRA = ADCSRA_INIT;
158 ADCSRB = ADCSRB_INIT;
169 LEDDDR |= (1 << LEDDDRPIN);