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make sure all silk elements are within board outline
fab-v0.1
author
Bdale Garbee
<bdale@gag.com>
Tue, 23 Nov 2010 06:16:59 +0000
(23:16 -0700)
committer
Bdale Garbee
<bdale@gag.com>
Tue, 23 Nov 2010 06:16:59 +0000
(23:16 -0700)
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projects / hw / telenano / commitdiff