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lose C9 since it's redundant on such a tight board
author
Bdale Garbee
<bdale@gag.com>
Thu, 18 Nov 2010 23:16:16 +0000
(16:16 -0700)
committer
Bdale Garbee
<bdale@gag.com>
Thu, 18 Nov 2010 23:16:16 +0000
(16:16 -0700)
telenano.pcb
patch
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telenano.sch
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blob
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diff --git
a/telenano.pcb
b/telenano.pcb
index 6ddaeafd6b8bc0618344f361692b5e46b57a812d..757151f5bff5126ed9960cc88eb524c09a1e8af4 100644
(file)
--- a/
telenano.pcb
+++ b/
telenano.pcb
@@
-1,5
+1,5
@@
# release: pcb 20091103
# release: pcb 20091103
-# date:
Wed Nov 10 20:40:49
2010
+# date:
Thu Nov 18 16:16:00
2010
# user: bdale (Bdale Garbee,KB0G)
# host: rover
# user: bdale (Bdale Garbee,KB0G)
# host: rover
@@
-13,7
+13,7
@@
Cursor[0 50000 0.000000]
PolyArea[200000000.000000]
Thermal[0.500000]
DRC[600 1000 600 500 1500 700]
PolyArea[200000000.000000]
Thermal[0.500000]
DRC[600 1000 600 500 1500 700]
-Flags("nameonpcb,
clearnew,
liveroute,hidenames")
+Flags("nameonpcb,liveroute,hidenames")
Groups("1,c:2,s:3")
Styles["Signal,1000,2900,1500,1000:Power,2500,6000,3500,1000:Fat,2500,6000,3500,1000:Skinny,600,2402,1181,600"]
Groups("1,c:2,s:3")
Styles["Signal,1000,2900,1500,1000:Power,2500,6000,3500,1000:Fat,2500,6000,3500,1000:Skinny,600,2402,1181,600"]
@@
-821,7
+821,7
@@
Via[33000 36200 2900 2000 0 1500 "" "thermal(1S)"]
Via[31700 1600 2900 2000 0 1500 "" "thermal(1S)"]
Via[71900 11700 2900 2000 0 1500 "" "thermal(1S)"]
Via[59000 40100 2900 2000 0 1500 "" "thermal(1S)"]
Via[31700 1600 2900 2000 0 1500 "" "thermal(1S)"]
Via[71900 11700 2900 2000 0 1500 "" "thermal(1S)"]
Via[59000 40100 2900 2000 0 1500 "" "thermal(1S)"]
-Via[6
48
00 2000 2900 2000 0 1500 "" "thermal(0,1S)"]
+Via[6
10
00 2000 2900 2000 0 1500 "" "thermal(0,1S)"]
Via[6500 26600 2900 2000 0 1500 "" ""]
Via[53500 9800 2900 2000 0 1500 "" ""]
Via[96000 35000 2900 2000 0 1500 "" "thermal(1S)"]
Via[6500 26600 2900 2000 0 1500 "" ""]
Via[53500 9800 2900 2000 0 1500 "" ""]
Via[96000 35000 2900 2000 0 1500 "" "thermal(1S)"]
@@
-838,7
+838,7
@@
Via[24900 43300 2900 2000 0 1500 "" ""]
Via[19500 33400 2900 2000 0 1500 "" ""]
Via[24400 39400 2900 2000 0 1500 "" ""]
Via[19500 33400 2900 2000 0 1500 "" ""]
Via[24400 39400 2900 2000 0 1500 "" ""]
-Element["" "0402" "C
9" "0.1uF" 66207 16326 -3068 -8116 0
100 ""]
+Element["" "0402" "C
21" "220pF" 66207 16274 -3537 -6852 3
100 ""]
(
Pad[-393 1574 393 1574 1968 2000 2568 "1" "1" "square"]
Pad[-393 -1574 393 -1574 1968 2000 2568 "2" "2" "square"]
(
Pad[-393 1574 393 1574 1968 2000 2568 "1" "1" "square"]
Pad[-393 -1574 393 -1574 1968 2000 2568 "2" "2" "square"]
@@
-877,7
+877,7
@@
Element["" "0402" "C5" "1uF" 7326 34493 2567 -11130 0 100 ""]
)
)
-Element["" "0605" "D2" "
unknown
" 9333 24126 7464 5700 2 100 ""]
+Element["" "0605" "D2" "
LED
" 9333 24126 7464 5700 2 100 ""]
(
Pad[1280 -1280 2067 -1280 2559 -1771 3159 "2" "2" "square"]
Pad[1280 -4626 2067 -4626 2559 -1771 3159 "1" "1" "square"]
(
Pad[1280 -1280 2067 -1280 2559 -1771 3159 "2" "2" "square"]
Pad[1280 -4626 2067 -4626 2559 -1771 3159 "1" "1" "square"]
@@
-978,10
+978,12
@@
Element["" "0402" "C23" "8.2pF" 73807 16274 -2959 -4751 1 100 ""]
)
)
-Element["" "
0402" "C21" "220pF" 61407 3574 -3537 -6852 3
100 ""]
+Element["" "
530470410" "J6" "Debug" 18300 47800 0 0 0
100 ""]
(
(
- Pad[-393 1574 393 1574 1968 2000 2568 "1" "1" "square"]
- Pad[-393 -1574 393 -1574 1968 2000 2568 "2" "2" "square"]
+ Pin[14764 0 3500 1200 4100 2047 "4" "4" "edge2"]
+ Pin[9843 0 3500 1200 4100 2047 "3" "3" "edge2"]
+ Pin[4921 0 3500 1200 4100 2047 "2" "2" "edge2"]
+ Pin[0 0 3500 1200 4100 2047 "1" "1" "square,edge2,thermal(1t)"]
)
)
@@
-1234,15
+1236,6
@@
Element["" "0402" "R18" "10k" 32831 10588 3150 3150 2 100 ""]
Pad[1574 -393 1574 393 1968 2000 2568 "1" "1" "square"]
Pad[-1574 -393 -1574 393 1968 2000 2568 "2" "2" "square"]
Pad[1574 -393 1574 393 1968 2000 2568 "1" "1" "square"]
Pad[-1574 -393 -1574 393 1968 2000 2568 "2" "2" "square"]
- )
-
-Element["" "530470410" "J6" "Debug" 18300 47800 0 0 0 100 ""]
-(
- Pin[14764 0 3500 1200 4100 2047 "4" "4" "edge2"]
- Pin[9843 0 3500 1200 4100 2047 "3" "3" "edge2"]
- Pin[4921 0 3500 1200 4100 2047 "2" "2" "edge2"]
- Pin[0 0 3500 1200 4100 2047 "1" "1" "square,edge2,thermal(1t)"]
-
)
Layer(1 "top")
(
)
Layer(1 "top")
(
@@
-1271,7
+1264,7
@@
Layer(1 "top")
Line[4000 47300 2700 47300 1000 2000 "clearline"]
Line[9400 43500 17462 43500 2500 2000 "clearline"]
Line[35386 1600 35800 2014 1000 2000 "clearline"]
Line[4000 47300 2700 47300 1000 2000 "clearline"]
Line[9400 43500 17462 43500 2500 2000 "clearline"]
Line[35386 1600 35800 2014 1000 2000 "clearline"]
- Line[58000 2000 6
4800 20
00 1000 2000 "clearline"]
+ Line[58000 2000 6
1100 19
00 1000 2000 "clearline"]
Line[2700 47300 1500 46100 1000 2000 "clearline"]
Line[77374 17874 77400 17848 1000 2000 "clearline"]
Line[77374 20807 77374 17874 1000 2000 "clearline"]
Line[2700 47300 1500 46100 1000 2000 "clearline"]
Line[77374 17874 77400 17848 1000 2000 "clearline"]
Line[77374 20807 77374 17874 1000 2000 "clearline"]
@@
-1280,8
+1273,8
@@
Layer(1 "top")
Line[71034 27800 70748 27514 1000 2000 ""]
Line[74100 27800 71034 27800 1000 2000 ""]
Line[70748 27514 70748 24438 1000 2000 ""]
Line[71034 27800 70748 27514 1000 2000 ""]
Line[74100 27800 71034 27800 1000 2000 ""]
Line[70748 27514 70748 24438 1000 2000 ""]
- Line[
61014 5148 61014 82
86 1000 2000 "clearline"]
- Line[
61014 8286 61000 83
00 1000 2000 "clearline"]
+ Line[
34634 10900 34448 110
86 1000 2000 "clearline"]
+ Line[
46900 10900 34634 109
00 1000 2000 "clearline"]
Line[69300 19700 69300 18181 1000 2000 "clearline"]
Line[31600 1600 35386 1600 1000 2000 "clearline"]
Line[5600 43400 9300 43400 2500 2000 "clearline"]
Line[69300 19700 69300 18181 1000 2000 "clearline"]
Line[31600 1600 35386 1600 1000 2000 "clearline"]
Line[5600 43400 9300 43400 2500 2000 "clearline"]
@@
-1452,8
+1445,6
@@
Layer(1 "top")
Line[33900 10500 34500 11100 1000 2000 "clearline"]
Line[46968 13151 46968 10968 1000 2000 "clearline"]
Line[46968 10968 46900 10900 1000 2000 "clearline"]
Line[33900 10500 34500 11100 1000 2000 "clearline"]
Line[46968 13151 46968 10968 1000 2000 "clearline"]
Line[46968 10968 46900 10900 1000 2000 "clearline"]
- Line[46900 10900 34634 10900 1000 2000 "clearline"]
- Line[34634 10900 34448 11086 1000 2000 "clearline"]
Polygon("")
(
[99100 49500] [80100 49500] [80100 32000] [99100 32000]
Polygon("")
(
[99100 49500] [80100 49500] [80100 32000] [99100 32000]
@@
-1519,7
+1510,6
@@
NetList()
(
Net("+3.3V" "(unknown)")
(
(
Net("+3.3V" "(unknown)")
(
- Connect("C9-1")
Connect("C10-2")
Connect("C12-2")
Connect("C20-2")
Connect("C10-2")
Connect("C12-2")
Connect("C20-2")
@@
-1553,7
+1543,6
@@
NetList()
(
Connect("B1-2")
Connect("C5-1")
(
Connect("B1-2")
Connect("C5-1")
- Connect("C9-2")
Connect("C10-1")
Connect("C11-1")
Connect("C12-1")
Connect("C10-1")
Connect("C11-1")
Connect("C12-1")
diff --git
a/telenano.sch
b/telenano.sch
index 96d1f85738124e507a4755e7502ef04e866540f7..dc6a78e90ec64b6a393f822f400b3c0126d72cab 100644
(file)
--- a/
telenano.sch
+++ b/
telenano.sch
@@
-1,26
+1,26
@@
v 20100214 2
C 40000 40000 0 0 0 EMBEDDEDtitle-C-bdale.sym
[
v 20100214 2
C 40000 40000 0 0 0 EMBEDDEDtitle-C-bdale.sym
[
-T
31100 408
00 5 10 0 0 0 0 1
+T
43200 411
00 5 10 0 0 0 0 1
graphical=1
graphical=1
-B 40000 40000 22000 17000 15 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
-L 54400 41400 62000 41400 15 0 0 0 -1 -1
+T 54500 40400 15 8 1 0 0 0 1
+FILE:
+T 59500 40400 15 8 1 0 0 0 1
+REVISION:
+T 57400 40400 15 8 1 0 0 0 1
+PAGE
+T 58200 40400 15 8 1 0 0 0 1
+OF
+B 54400 40000 7600 2700 15 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
+L 54400 40600 62000 40600 15 0 0 0 -1 -1
+T 54500 40100 15 10 1 0 0 0 1
+Project URL:
T 54900 40800 9 10 1 0 0 0 2
Copyright 2010 by Bdale Garbee <bdale@gag.com>
Licensed under the TAPR Open Hardware License, http://www.tapr.org/OHL
T 54900 40800 9 10 1 0 0 0 2
Copyright 2010 by Bdale Garbee <bdale@gag.com>
Licensed under the TAPR Open Hardware License, http://www.tapr.org/OHL
-T 54500 40100 15 10 1 0 0 0 1
-Project URL:
-L 54400 40600 62000 40600 15 0 0 0 -1 -1
-B 54400 40000 7600 2700 15 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
-T 58200 40400 15 8 1 0 0 0 1
-OF
-T 57400 40400 15 8 1 0 0 0 1
-PAGE
-T 59500 40400 15 8 1 0 0 0 1
-REVISION:
-T 54500 40400 15 8 1 0 0 0 1
-FILE:
-T 43200 41100 5 10 0 0 0 0 1
+L 54400 41400 62000 41400 15 0 0 0 -1 -1
+B 40000 40000 22000 17000 15 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
+T 31100 40800 5 10 0 0 0 0 1
graphical=1
]
C 43600 54400 1 0 0 gnd-1.sym
graphical=1
]
C 43600 54400 1 0 0 gnd-1.sym
@@
-178,25
+178,6
@@
vendor=digikey
T 53400 53900 5 10 0 1 0 0 1
loadstatus=smt
}
T 53400 53900 5 10 0 1 0 0 1
loadstatus=smt
}
-C 54800 54300 1 270 0 capacitor-1.sym
-{
-T 55500 54100 5 10 0 0 270 0 1
-device=CAPACITOR
-T 55100 54100 5 10 1 1 0 0 1
-refdes=C9
-T 55700 54100 5 10 0 0 270 0 1
-symversion=0.1
-T 55100 53500 5 10 1 1 0 0 1
-value=0.1uF
-T 54800 54300 5 10 0 0 0 0 1
-vendor_part_number=399-3027-1-ND
-T 54800 54300 5 10 0 0 0 0 1
-footprint=0402
-T 54800 54300 5 10 0 0 0 0 1
-vendor=digikey
-T 54800 54300 5 10 0 1 0 0 1
-loadstatus=smt
-}
C 55800 54700 1 270 0 capacitor-1.sym
{
T 56500 54500 5 10 0 0 270 0 1
C 55800 54700 1 270 0 capacitor-1.sym
{
T 56500 54500 5 10 0 0 270 0 1
@@
-236,12
+217,10
@@
T 56800 55100 5 10 0 1 0 0 1
loadstatus=smt
}
N 53200 53900 53600 53900 4
loadstatus=smt
}
N 53200 53900 53600 53900 4
-N 53600 54300 55000 54300 4
N 53600 54700 56000 54700 4
N 57000 55100 53600 55100 4
C 56900 53900 1 0 0 gnd-1.sym
C 55900 53500 1 0 0 gnd-1.sym
N 53600 54700 56000 54700 4
N 57000 55100 53600 55100 4
C 56900 53900 1 0 0 gnd-1.sym
C 55900 53500 1 0 0 gnd-1.sym
-C 54900 53100 1 0 0 gnd-1.sym
C 53500 52700 1 0 0 gnd-1.sym
C 53800 50700 1 270 0 capacitor-1.sym
{
C 53500 52700 1 0 0 gnd-1.sym
C 53800 50700 1 270 0 capacitor-1.sym
{