enabling outline layer causes bogus drc errors, so leave it off
authorBdale Garbee <bdale@gag.com>
Fri, 5 Nov 2010 04:48:36 +0000 (22:48 -0600)
committerBdale Garbee <bdale@gag.com>
Fri, 5 Nov 2010 04:48:36 +0000 (22:48 -0600)
commit2d861ce0cb46ce6e514870de3e30d1f799480a0a
treeb5c0072fb02055562408b7d2a0cc9bdfbd3a9c97
parent9dee0fe259b5c25a7bbd7ca51020ec8eece66dac
enabling outline layer causes bogus drc errors, so leave it off
telenano.pcb