From 2d861ce0cb46ce6e514870de3e30d1f799480a0a Mon Sep 17 00:00:00 2001 From: Bdale Garbee Date: Thu, 4 Nov 2010 22:48:36 -0600 Subject: [PATCH] enabling outline layer causes bogus drc errors, so leave it off --- telenano.pcb | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/telenano.pcb b/telenano.pcb index badbf27..dae41ef 100644 --- a/telenano.pcb +++ b/telenano.pcb @@ -1,5 +1,5 @@ # release: pcb 20091103 -# date: Thu Nov 4 16:46:09 2010 +# date: Thu Nov 4 22:48:21 2010 # user: bdale (Bdale Garbee,KB0G) # host: rover @@ -1510,10 +1510,6 @@ Layer(2 "bottom") ) Layer(3 "outline") ( - Line[0 0 100000 0 1000 2000 ""] - Line[100000 0 100000 50000 1000 2000 ""] - Line[100000 50000 0 50000 1000 2000 ""] - Line[0 50000 0 0 1000 2000 ""] ) Layer(4 "silk") ( -- 2.30.2