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hide top silk again
v0.1
fab-v0.1
author
Bdale Garbee
<bdale@gag.com>
Tue, 23 Nov 2010 06:28:28 +0000
(23:28 -0700)
committer
Bdale Garbee
<bdale@gag.com>
Tue, 23 Nov 2010 06:28:28 +0000
(23:28 -0700)
telemini.pcb
patch
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diff --git
a/telemini.pcb
b/telemini.pcb
index fa8d205dc38d49d4632f54a74d7a02a4cd29c6ec..1e52f4f5af7eafc58b195dd5180e79ee80994dbd 100644
(file)
--- a/
telemini.pcb
+++ b/
telemini.pcb
@@
-1,5
+1,5
@@
# release: pcb 20100929
# release: pcb 20100929
-# date: Mon Nov 22 23:
18:13
2010
+# date: Mon Nov 22 23:
28:14
2010
# user: bdale (Bdale Garbee,KB0G)
# host: rover
# user: bdale (Bdale Garbee,KB0G)
# host: rover
@@
-9,11
+9,11
@@
FileVersion[20100606]
PCB["TeleMini" 150000 50000]
Grid[100.000000 0 0 0]
PCB["TeleMini" 150000 50000]
Grid[100.000000 0 0 0]
-Cursor[0
5000
0 0.000000]
+Cursor[0 0 0.000000]
PolyArea[200000000.000000]
Thermal[0.500000]
DRC[600 1000 600 500 1500 700]
PolyArea[200000000.000000]
Thermal[0.500000]
DRC[600 1000 600 500 1500 700]
-Flags("nameonpcb,clearnew,liveroute")
+Flags("nameonpcb,clearnew,liveroute
,hidenames
")
Groups("1,c:2,s:3")
Styles["Signal,1000,2900,1500,1000:Power,2500,6000,3500,1000:Fat,2500,6000,3500,1000:Skinny,600,2402,1181,600"]
Groups("1,c:2,s:3")
Styles["Signal,1000,2900,1500,1000:Power,2500,6000,3500,1000:Fat,2500,6000,3500,1000:Skinny,600,2402,1181,600"]