reduce pcb workspace size to board outline again, make version 2.0

[hw/telemega] / telemega.sch

diff --git a/telemega.sch b/telemega.sch
index ca5c34c0f1c356bb8f42286ed6ef9b5532e8ada6..5f43eae20e9f3b4a004747dde1bf88910e03b133 100644 (file)
--- a/telemega.sch
+++ b/telemega.sch
@@ -42,7 +42,7 @@ T 63600 43500 5 10 0 0 0 0 1
 footprint=B2B-PH
 T 63600 43500 5 10 0 1 0 0 1
 device=CONNECTOR
-T 63600 43500 5 10 1 1 0 0 1
+T 63600 43500 5 10 0 1 0 0 1
 loadstatus=noload
 }
 N 63000 42100 63000 41600 4
@@ -153,7 +153,7 @@ Tolerate up to
 N 68000 43600 67900 43600 4
 N 67900 43600 67900 44000 4
 T 82400 40400 9 10 1 0 0 0 1
-1.1
+2.0
 T 80000 40400 9 10 1 0 0 0 1
 1
 T 80600 40400 9 10 1 0 0 0 1
@@ -3010,7 +3010,7 @@ T 82600 71200 5 10 1 1 0 0 1
 refdes=A1
 T 82000 71700 5 10 1 1 0 0 1
 value=GP.1575.18.4.A.02
-T 82400 71000 5 10 1 1 0 0 1
+T 82400 71000 5 10 0 1 0 0 1
 loadstatus=noload
 }
 C 81600 70000 1 0 1 saw.sym