reduce pcb workspace size to board outline again, make version 2.0

[hw/telemega] / telemega.pcb

diff --git a/telemega.pcb b/telemega.pcb
index 1578bfe1b64fec1720058c1b73811497a2ebaad7..64439940ffcceb3d721c7cbfc44da08b36b3288f 100644 (file)
--- a/telemega.pcb
+++ b/telemega.pcb
@@ -3,7 +3,7 @@
 # To read pcb files, the pcb version (or the git source date) must be >= the file version
 FileVersion[20091103]
 
-PCB["TeleMega" 3250.00mil 1500.00mil]
+PCB["TeleMega" 3250.00mil 1250.00mil]
 
 Grid[100.000000 0.0000 0.0000 0]
 PolyArea[200000000.000000]
@@ -2521,7 +2521,7 @@ Element["hidename" "0402" "R40" "220" 2309.00mil 231.00mil -31.50mil -31.50mil 0
 
        )
 
-Element["onsolder" "0-338068-6" "J21" "Servos" 2362.00mil 75.00mil 0.0000 0.0000 2 100 "auto"]
+Element["hidename,onsolder" "0-338068-6" "J21" "Servos" 2362.00mil 75.00mil 0.0000 0.0000 2 100 "auto"]
 (
        Pin[0.0000 100.00mil 62.99mil 12.00mil 72.99mil 31.50mil "pin1" "1" "square,edge2,thermal(1X,3X)"]
        Pin[-50.00mil 0.0000 62.99mil 12.00mil 72.99mil 31.50mil "pin2" "2" "edge2"]
@@ -4015,7 +4015,7 @@ Layer(6 "silk")
        Line[444.00mil 137.00mil 444.00mil 160.00mil 10.00mil 20.00mil "clearline"]
        Line[344.00mil 137.00mil 444.00mil 137.00mil 10.00mil 20.00mil "clearline"]
        Line[344.00mil 160.00mil 344.00mil 137.00mil 10.00mil 20.00mil "clearline"]
-       Text[2212.00mil 1178.00mil 0 200 "TeleMega v1.1" "clearline,onsolder"]
+       Text[2212.00mil 1178.00mil 0 200 "TeleMega v2.0" "clearline,onsolder"]
        Text[77.0250mm 1005.20mil 3 100 "` 2015 Bdale Garbee KB0G" "onsolder"]
        Text[1415.00mil 297.00mil 0 100 "companion" "clearline,onsolder"]
        Text[396.00mil 1238.00mil 3 150 "switch" "clearline,onsolder"]