snapshot initial work on dedicated teledongle board derived from telemetrum

diff --git a/Datasheets/1551NFL.pdf b/Datasheets/1551NFL.pdf
new file mode 100644 (file)
index 0000000..05e8a7e
Binary files /dev/null and b/Datasheets/1551NFL.pdf differ

diff --git a/License.pdf b/License.pdf
new file mode 100644 (file)
index 0000000..01fceb2
Binary files /dev/null and b/License.pdf differ

diff --git a/Makefile b/Makefile
new file mode 100644 (file)
index 0000000..ca73922
--- /dev/null
+++ b/Makefile
@@ -0,0 +1,38 @@
+# intentionally want to rebuild drc and bom on every invocation
+all:   drc partslist pcb
+
+drc:   teledongle.sch
+       -gnetlist -g drc2 teledongle.sch -o teledongle.drc
+
+partslist:     teledongle.sch
+       gnetlist -g bom -o teledongle.unsorted teledongle.sch
+       head -n1 teledongle.unsorted > partslist
+       tail -n+2 teledongle.unsorted | sort >> partslist
+       rm -f teledongle.unsorted
+
+pcb:   teledongle.sch project
+       gsch2pcb project
+
+# note that 'gschlas -e foo.sch' will embed all symbols in the schematic, this
+# might be a really good idea for publishing designs to the web that others
+# might review?  Like this example from DJ:
+#
+#web :
+#        for i in channel.sch ethernet.sch power.sch mcu.sch; do \
+#          cp $$i tmp.sch ; \
+#          gschlas -e tmp.sch ; \
+#          mv tmp.sch ${WEB}/$$i; \
+#        done
+
+# this shoves local work out to the git.gag.com repository
+push:  
+       git push --mirror
+
+zip:   teledongle.back.gbr teledongle.backmask.gbr teledongle.fab.gbr teledongle.front.gbr teledongle.frontmask.gbr teledongle.frontpaste.gbr teledongle.frontsilk.gbr teledongle.group2.gbr teledongle.group3.gbr teledongle.plated-drill.cnc
+       zip teledongle.zip *.gbr *.cnc
+
+clean:
+       rm -f *.bom *.drc *.log *~ teledongle.ps *.gbr *.cnc *bak* *- *.zip 
+       rm -f *.net *.xy *.cmd *.png partslist
+       rm -f *.partslist *.new.pcb *.unsorted
+

diff --git a/attribs b/attribs
new file mode 100644 (file)
index 0000000..1240aa1
--- /dev/null
+++ b/attribs
@@ -0,0 +1,5 @@
+value
+digikey
+footprint
+loadstatus
+device

diff --git a/gattribrc b/gattribrc
new file mode 120000 (symlink)
index 0000000..441e62e
--- /dev/null
+++ b/gattribrc
@@ -0,0 +1 @@
+gschemrc
\ No newline at end of file

diff --git a/gnetlistrc b/gnetlistrc
new file mode 120000 (symlink)
index 0000000..441e62e
--- /dev/null
+++ b/gnetlistrc
@@ -0,0 +1 @@
+gschemrc
\ No newline at end of file

diff --git a/gschemrc b/gschemrc
new file mode 100644 (file)
index 0000000..55565aa
--- /dev/null
+++ b/gschemrc
@@ -0,0 +1,2 @@
+;; list libraries here.  order matters as this sets the search order
+(component-library "../bdale/sym")

diff --git a/project b/project
new file mode 100644 (file)
index 0000000..b6eb30c
--- /dev/null
+++ b/project
@@ -0,0 +1,13 @@
+# List all the schematics to be netlisted and laid out on the pc board
+schematics     teledongle.sch
+
+# for an output-name of foo, gsch2pcb generates files foo.net, foo.pcb,
+# and foo.new.pcb.  if there is no output name specified, the file names
+# are derived from the first listed schematic...
+output-name    teledongle
+
+elements-dir ../bdale/pkg
+elements-dir /usr/share/pcb
+
+# stick to newlib elements, don't use the older/odder m4 stuff
+skip-m4

diff --git a/teledongle.pcb b/teledongle.pcb
new file mode 100644 (file)
index 0000000..1cd9805
--- /dev/null
+++ b/teledongle.pcb
@@ -0,0 +1,1705 @@
+# release: pcb 20091103
+# date:    Sat Dec 12 11:49:34 2009
+# user:    bdale (Bdale Garbee,KB0G)
+# host:    rover
+
+# To read pcb files, the pcb version (or the cvs source date) must be >= the file version
+FileVersion[20070407]
+
+PCB["" 116100 116100]
+
+Grid[100.000000 0 0 0]
+Cursor[0 0 0.000000]
+PolyArea[200000000.000000]
+Thermal[0.500000]
+DRC[600 1000 600 500 1500 650]
+Flags("nameonpcb,uniquename,clearnew,snappin")
+Groups("1,c:2,s")
+Styles["Signal,1000,3600,2000,1000:Power,2500,6000,3500,1000:Fat,4000,6000,3500,1000:Skinny,600,2402,1181,600"]
+
+Symbol(' ' 18)
+(
+)
+Symbol('!' 12)
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+       SymbolLine(0 45 0 50 8)
+       SymbolLine(0 10 0 35 8)
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+Symbol('"' 12)
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+       SymbolLine(10 10 10 20 8)
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+Symbol('#' 12)
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+       SymbolLine(0 25 20 25 8)
+       SymbolLine(15 20 15 40 8)
+       SymbolLine(5 20 5 40 8)
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+Symbol('j' 10)
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+Symbol('k' 12)
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+Symbol('l' 10)
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+       SymbolLine(0 30 5 35 8)
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+Symbol('o' 12)
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+       Pad[2960 5920 2960 5920 1500 0 2960 "pin37" "37" "square,edge2"]
+       Pad[5920 5920 5920 5920 2960 0 0 "pin37" "37" "square,edge2,nopaste"]
+       Pad[-7873 -11849 -7873 -9999 1102 866 1500 "pin27" "27" ""]
+       Pad[-7873 10000 -7873 11850 1102 866 1500 "pin1" "1" "edge2"]
+       Pad[10000 -7873 11850 -7873 1102 866 1500 "pin18" "18" "edge2"]
+       Pad[-11849 -7873 -9999 -7873 1102 866 1500 "pin28" "28" ""]
+       Pad[-5905 -11849 -5905 -9999 1102 866 1500 "pin26" "26" ""]
+       Pad[-5905 10000 -5905 11850 1102 866 1500 "pin2" "2" "edge2"]
+       Pad[10000 -5905 11850 -5905 1102 866 1500 "pin17" "17" "edge2"]
+       Pad[-11849 -5905 -9999 -5905 1102 866 1500 "pin29" "29" ""]
+       Pad[-3936 -11849 -3936 -9999 1102 866 1500 "pin25" "25" ""]
+       Pad[-3936 10000 -3936 11850 1102 866 1500 "pin3" "3" "edge2"]
+       Pad[10000 -3936 11850 -3936 1102 866 1500 "pin16" "16" "edge2"]
+       Pad[-11849 -3936 -9999 -3936 1102 866 1500 "pin30" "30" ""]
+       Pad[-1968 -11849 -1968 -9999 1102 866 1500 "pin24" "24" ""]
+       Pad[-1968 10000 -1968 11850 1102 866 1500 "pin4" "4" "edge2"]
+       Pad[10000 -1968 11850 -1968 1102 866 1500 "pin15" "15" "edge2"]
+       Pad[-11849 -1968 -9999 -1968 1102 866 1500 "pin31" "31" ""]
+       Pad[0 -11849 0 -9999 1102 866 1500 "pin23" "23" ""]
+       Pad[0 10000 0 11850 1102 866 1500 "pin5" "5" "edge2"]
+       Pad[10000 0 11850 0 1102 866 1500 "pin14" "14" "edge2"]
+       Pad[-11849 0 -9999 0 1102 866 1500 "pin32" "32" ""]
+       Pad[1969 -11849 1969 -9999 1102 866 1500 "pin22" "22" ""]
+       Pad[1969 10000 1969 11850 1102 866 1500 "pin6" "6" "edge2"]
+       Pad[10000 1969 11850 1969 1102 866 1500 "pin13" "13" "edge2"]
+       Pad[-11849 1969 -9999 1969 1102 866 1500 "pin33" "33" ""]
+       Pad[3937 -11849 3937 -9999 1102 866 1500 "pin21" "21" ""]
+       Pad[3937 10000 3937 11850 1102 866 1500 "pin7" "7" "edge2"]
+       Pad[10000 3937 11850 3937 1102 866 1500 "pin12" "12" "edge2"]
+       Pad[-11849 3937 -9999 3937 1102 866 1500 "pin34" "34" ""]
+       Pad[5906 -11849 5906 -9999 1102 866 1500 "pin20" "20" ""]
+       Pad[5906 10000 5906 11850 1102 866 1500 "pin8" "8" "edge2"]
+       Pad[10000 5906 11850 5906 1102 866 1500 "pin11" "11" "edge2"]
+       Pad[-11849 5906 -9999 5906 1102 866 1500 "pin35" "35" ""]
+       Pad[7874 -11849 7874 -9999 1102 866 1500 "pin19" "19" ""]
+       Pad[7874 10000 7874 11850 1102 866 1500 "pin9" "9" "edge2"]
+       Pad[10000 7874 11850 7874 1102 866 1500 "pin10" "10" "edge2"]
+       Pad[-11849 7874 -9999 7874 1102 866 1500 "pin36" "36" ""]
+       ElementArc [-10235 10236 500 500 0 360 1000]
+
+       )
+
+Element["" "0402" "R12" "270" 50868 86254 2758 -14709 3 100 ""]
+(
+       Pad[-393 -1574 393 -1574 1968 2000 2568 "1" "1" "square"]
+       Pad[-393 1574 393 1574 1968 2000 2568 "2" "2" "square"]
+
+       )
+
+Element["" "SOT23-5" "U1" "TC1055-3.3" 99300 84900 -2100 1900 1 89 ""]
+(
+       Attribute("author" "DJ Delorie")
+       Attribute("copyright" "2006 DJ Delorie")
+       Attribute("use-license" "Unlimited")
+       Attribute("dist-license" "GPL")
+       Pad[-800 0 800 0 2400 3000 3000 "4" "4" "square,edge2"]
+       Pad[-800 -7800 800 -7800 2400 3000 3000 "5" "5" "square,edge2"]
+       Pad[-9000 -7800 -7400 -7800 2400 3000 3000 "1" "1" "square"]
+       Pad[-9000 -3900 -7400 -3900 2400 3000 3000 "2" "2" "square"]
+       Pad[-9000 0 -7400 0 2400 3000 3000 "3" "3" "square"]
+       ElementLine [-11000 -9800 -11000 2000 1000]
+       ElementLine [-11000 -9800 2900 -9800 1000]
+       ElementLine [2900 -9800 2900 2000 1000]
+       ElementLine [-11000 2000 2900 2000 1000]
+
+       )
+
+Element["" "0402" "C5" "1uF" 84193 84274 -7142 3243 1 100 ""]
+(
+       Pad[-393 -1574 393 -1574 1968 2000 2568 "1" "1" "square"]
+       Pad[-393 1574 393 1574 1968 2000 2568 "2" "2" "square"]
+
+       )
+
+Element["" "0402" "C37" "1uF" 84193 77526 -7323 2858 1 100 ""]
+(
+       Pad[-393 1574 393 1574 1968 2000 2568 "1" "1" "square"]
+       Pad[-393 -1574 393 -1574 1968 2000 2568 "2" "2" "square"]
+
+       )
+Rat[49600 51748 0 49775 56131 0  ""]
+Rat[49775 56131 0 51744 56131 0  ""]
+Rat[51744 56131 0 57649 56131 0  ""]
+Rat[57649 56131 0 63554 56131 0  ""]
+Rat[49775 56131 0 43831 60107 0  ""]
+Rat[40748 58800 0 30926 66907 0  ""]
+Rat[63554 56131 0 67530 71917 0  ""]
+Rat[43831 62075 0 49775 79830 0  ""]
+Rat[22500 42500 1 43831 75854 0  ""]
+Rat[49900 24300 0 3261 1000 1  "via"]
+Rat[49800 29300 0 3261 1000 1  "via"]
+Rat[44700 41800 0 3261 1000 1  "via"]
+Rat[66300 39600 0 3261 1000 1  "via"]
+Rat[37600 58800 0 3261 1000 1  "via"]
+Rat[30952 62700 0 3261 1000 1  "via"]
+Rat[57307 48926 0 3261 1000 1  "via"]
+Rat[49600 48600 0 3261 1000 1  "via"]
+Rat[30952 74314 0 3261 1000 1  "via"]
+Rat[42800 49400 0 3261 1000 1  "via"]
+Rat[22500 52500 1 43831 73886 0  ""]
+Rat[12500 47500 1 43831 71917 0  ""]
+Rat[103600 42500 1 30926 70607 0  ""]
+Rat[42800 52548 0 47807 56131 0  ""]
+Layer(1 "top")
+(
+       Line[48458 110400 53379 110400 2500 2000 "clearline"]
+       Line[58300 110400 58300 104267 1000 2000 "clearline"]
+       Line[58300 104267 57907 103874 1000 2000 "clearline"]
+       Line[58693 97807 58700 97800 1000 2000 "clearline"]
+       Line[58693 100726 58693 97807 1000 2000 "clearline"]
+       Line[63586 97714 63600 97700 1000 2000 "clearline"]
+       Line[63586 100700 63586 97714 1000 2000 "clearline"]
+       Line[69900 53986 72586 53986 1000 2000 "clearline"]
+       Line[79548 54914 79548 52837 1000 2000 "clearline"]
+       Line[79548 52837 81600 50785 1000 2000 "clearline"]
+       Line[76300 36686 76300 38763 1000 2000 "clearline"]
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+       Line[61586 47914 62800 46700 1000 2000 "clearline"]
+       Line[62800 46700 78500 46700 1000 2000 "clearline"]
+       Line[78500 46700 81600 49800 1000 2000 "clearline"]
+       Line[59617 56131 59617 46883 1000 2000 "clearline"]
+       Line[59617 46883 61400 45100 1000 2000 "clearline"]
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+       Line[66538 54200 66752 53986 1000 2000 "clearline"]
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+       Line[64900 54200 66538 54200 1000 2000 "clearline"]
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+       Line[47786 99048 47786 99886 1000 2000 "clearline"]
+       Line[51744 79830 51744 85297 1000 2000 "clearline"]
+       Line[47786 99886 58300 110400 1000 2000 "clearline"]
+       Line[40800 86500 43407 86500 1000 2000 "clearline"]
+       Line[43407 86500 43927 85980 1000 2000 "clearline"]
+       Line[49775 79830 49775 81266 1000 2000 "clearline"]
+       Line[49775 81266 47061 83980 1000 2000 "clearline"]
+       Line[47061 83980 47061 85394 1000 2000 "clearline"]
+       Line[47061 85394 47447 85780 1000 2000 "clearline"]
+       Line[70948 45100 74317 41731 1000 2000 "clearline"]
+       Line[61400 45100 70948 45100 1000 2000 "clearline"]
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+       Line[73000 89800 76200 86600 2500 2000 "clearline"]
+       Line[76200 86600 88600 86600 2500 2000 "clearline"]
+       Line[88600 86600 90300 84900 2500 2000 "clearline"]
+       Line[67530 64044 92056 64044 1000 2000 "clearline"]
+       Line[92056 64044 103600 52500 1000 2000 "clearline"]
+       Line[67530 66012 92612 66012 1000 2000 "clearline"]
+       Line[92612 66012 93700 67100 1000 2000 "clearline"]
+       Line[67530 71917 80551 71917 1000 2000 "clearline"]
+       Line[80551 71917 84586 75952 1000 2000 "clearline"]
+       Line[59617 79830 59617 83117 1000 2000 "clearline"]
+       Line[59617 83117 59700 83200 1000 2000 "clearline"]
+       Line[6200 63800 12500 57500 1000 2000 "clearline"]
+       Line[8800 83300 6200 80700 1000 2000 "clearline"]
+       Line[6200 80700 6200 63800 1000 2000 "clearline"]
+       Line[37669 66012 37074 66607 1000 2000 "clearline"]
+       Line[12607 67393 12500 67500 1000 2000 "clearline"]
+       Line[36200 83300 8800 83300 1000 2000 "clearline"]
+       Line[43831 66012 34969 66012 1000 2000 "clearline"]
+       Line[34969 66012 34074 66907 1000 2000 "clearline"]
+       Line[34074 66907 34074 74288 1000 2000 "clearline"]
+       Line[34074 74288 34100 74314 1000 2000 "clearline"]
+       Line[43831 64044 35444 64044 1000 2000 "clearline"]
+       Line[35444 64044 34100 62700 1000 2000 "clearline"]
+       Line[43831 62075 43237 62075 1000 2000 "clearline"]
+       Line[43237 62075 40748 59586 1000 2000 "clearline"]
+       Line[43831 60107 42055 60107 1000 2000 "clearline"]
+       Line[42055 60107 40748 58800 1000 2000 "clearline"]
+       Line[66726 51593 66726 54526 1000 2000 "clearline"]
+       Line[66726 54526 66652 54600 1000 2000 "clearline"]
+       Line[69874 51593 69874 54526 1000 2000 "clearline"]
+       Line[69874 54526 69800 54600 1000 2000 "clearline"]
+       Line[12500 67500 30733 67500 1000 2000 "clearline"]
+       Line[30733 67500 30926 67693 1000 2000 "clearline"]
+)
+Layer(2 "bottom")
+(
+       Line[37900 92800 46500 92800 1000 2000 "clearline"]
+       Line[46500 92800 51800 98100 1000 2000 "clearline"]
+       Line[54200 93900 54200 94086 1000 2000 "clearline"]
+       Line[54200 94086 57914 97800 1000 2000 "clearline"]
+       Line[57914 97800 72500 97800 1000 2000 "clearline"]
+       Line[72500 97800 77900 92400 1000 2000 "clearline"]
+       Line[93600 47500 93600 67000 1000 2000 "clearline"]
+       Line[93600 67000 93700 67100 1000 2000 "clearline"]
+       Line[59700 83200 36300 83200 1000 2000 "clearline"]
+       Line[36300 83200 36200 83300 1000 2000 "clearline"]
+       Polygon("clearpoly")
+       (
+               [1000 115100] [115100 115100] [115100 1000] [1000 1000] 
+       )
+)
+Layer(3 "silk")
+(
+)
+Layer(4 "silk")
+(
+)
+NetList()
+(
+       Net("+3.3V" "(unknown)")
+       (
+               Connect("C9-1")
+               Connect("C12-2")
+               Connect("C20-2")
+               Connect("C21-1")
+               Connect("C28-1")
+               Connect("C29-1")
+               Connect("C37-2")
+               Connect("J9-7")
+               Connect("R6-2")
+               Connect("R23-2")
+               Connect("U1-5")
+               Connect("U9-2")
+               Connect("U9-12")
+               Connect("U9-19")
+               Connect("U9-22")
+               Connect("U9-25")
+               Connect("U9-26")
+               Connect("U9-28")
+               Connect("U9-29")
+       )
+       Net("c0" "(unknown)")
+       (
+               Connect("J9-2")
+               Connect("U9-36")
+       )
+       Net("cs0" "(unknown)")
+       (
+               Connect("U9-1")
+       )
+       Net("cs1" "(unknown)")
+       (
+               Connect("J9-6")
+       )
+       Net("debug_clock" "(unknown)")
+       (
+               Connect("J6-4")
+               Connect("U9-16")
+       )
+       Net("debug_data" "(unknown)")
+       (
+               Connect("J6-3")
+               Connect("U9-15")
+       )
+       Net("drogue" "(unknown)")
+       (
+               Connect("U9-17")
+       )
+       Net("GND" "(unknown)")
+       (
+               Connect("C2-1")
+               Connect("C3-1")
+               Connect("C5-1")
+               Connect("C9-2")
+               Connect("C12-1")
+               Connect("C19-1")
+               Connect("C20-1")
+               Connect("C21-2")
+               Connect("C22-2")
+               Connect("C23-2")
+               Connect("C24-2")
+               Connect("C26-2")
+               Connect("C28-2")
+               Connect("C29-2")
+               Connect("C30-2")
+               Connect("C31-2")
+               Connect("C36-1")
+               Connect("C37-1")
+               Connect("D1-2")
+               Connect("D2-2")
+               Connect("H1-1")
+               Connect("H2-1")
+               Connect("J5-4")
+               Connect("J5-5")
+               Connect("J6-1")
+               Connect("J8-2")
+               Connect("J9-1")
+               Connect("R16-2")
+               Connect("U1-2")
+               Connect("U9-37")
+               Connect("X1-2")
+               Connect("X1-4")
+       )
+       Net("irq" "(unknown)")
+       (
+               Connect("J9-5")
+               Connect("U9-7")
+       )
+       Net("led_red" "(unknown)")
+       (
+               Connect("R13-1")
+               Connect("U9-4")
+       )
+       Net("led_yellow" "(unknown)")
+       (
+               Connect("R12-1")
+               Connect("U9-3")
+       )
+       Net("main" "(unknown)")
+       (
+               Connect("U9-18")
+       )
+       Net("mi0" "(unknown)")
+       (
+               Connect("J9-4")
+               Connect("U9-35")
+       )
+       Net("mo0" "(unknown)")
+       (
+               Connect("J9-3")
+               Connect("U9-34")
+       )
+       Net("padm" "(unknown)")
+       (
+               Connect("C3-2")
+               Connect("R8-2")
+               Connect("U9-11")
+       )
+       Net("padp" "(unknown)")
+       (
+               Connect("C2-2")
+               Connect("R7-2")
+               Connect("U9-10")
+       )
+       Net("reset_n" "(unknown)")
+       (
+               Connect("J6-2")
+               Connect("R17-1")
+       )
+       Net("rstn" "(unknown)")
+       (
+               Connect("C36-2")
+               Connect("R17-2")
+               Connect("R23-1")
+               Connect("U9-31")
+       )
+       Net("unnamed_net1" "(unknown)")
+       (
+               Connect("J5-2")
+               Connect("R8-1")
+       )
+       Net("unnamed_net2" "(unknown)")
+       (
+               Connect("J5-3")
+               Connect("R6-1")
+               Connect("R7-1")
+       )
+       Net("unnamed_net3" "(unknown)")
+       (
+               Connect("C30-1")
+               Connect("U9-21")
+               Connect("X1-3")
+       )
+       Net("unnamed_net4" "(unknown)")
+       (
+               Connect("C31-1")
+               Connect("U9-20")
+               Connect("X1-1")
+       )
+       Net("unnamed_net5" "(unknown)")
+       (
+               Connect("R16-1")
+               Connect("U9-27")
+       )
+       Net("unnamed_net6" "(unknown)")
+       (
+               Connect("C22-1")
+               Connect("L4-1")
+               Connect("U9-24")
+       )
+       Net("unnamed_net7" "(unknown)")
+       (
+               Connect("C25-1")
+               Connect("L1-2")
+               Connect("U9-23")
+       )
+       Net("unnamed_net8" "(unknown)")
+       (
+               Connect("C19-2")
+               Connect("U9-30")
+       )
+       Net("unnamed_net9" "(unknown)")
+       (
+               Connect("C25-2")
+               Connect("L2-1")
+               Connect("L4-2")
+       )
+       Net("unnamed_net10" "(unknown)")
+       (
+               Connect("C23-1")
+               Connect("L2-2")
+               Connect("L3-1")
+       )
+       Net("unnamed_net11" "(unknown)")
+       (
+               Connect("C26-1")
+               Connect("L1-1")
+       )
+       Net("unnamed_net12" "(unknown)")
+       (
+               Connect("C24-1")
+               Connect("C27-1")
+               Connect("L3-2")
+       )
+       Net("unnamed_net13" "(unknown)")
+       (
+               Connect("C27-2")
+               Connect("J8-1")
+       )
+       Net("unnamed_net14" "(unknown)")
+       (
+               Connect("D2-1")
+               Connect("R13-2")
+       )
+       Net("unnamed_net15" "(unknown)")
+       (
+               Connect("D1-1")
+               Connect("R12-2")
+       )
+       Net("v_lipo" "(unknown)")
+       (
+               Connect("J9-8")
+       )
+       Net("v_usb" "(unknown)")
+       (
+               Connect("C5-2")
+               Connect("J5-1")
+               Connect("U1-1")
+               Connect("U1-3")
+       )
+)

diff --git a/teledongle.sch b/teledongle.sch
new file mode 100644 (file)
index 0000000..b683f0a
--- /dev/null
+++ b/teledongle.sch
@@ -0,0 +1,975 @@
+v 20081231 1
+C 40000 40000 0 0 0 title-D-bdale.sym
+C 47200 57600 1 0 0 miniUSB.sym
+{
+T 47495 60000 5 10 1 1 0 0 1
+refdes=J5
+T 47555 57995 5 10 0 1 0 0 1
+footprint=530470510
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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