fix Makefile to reflec realities of this board, add outline layer content
authorBdale Garbee <bdale@gag.com>
Mon, 21 Jan 2013 07:59:15 +0000 (00:59 -0700)
committerBdale Garbee <bdale@gag.com>
Mon, 21 Jan 2013 07:59:15 +0000 (00:59 -0700)
Makefile
swdadapter.pcb

index 296f6a22e690d27e12b0b7477042fbf8f578c769..cae4751915f492fa8a32eaaa2553c3b9304dc516 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -30,13 +30,12 @@ swdadapter.xy:      swdadapter.pcb
 swdadapter.bottom.gbr: swdadapter.pcb
        pcb -x gerber swdadapter.pcb
 
-zip:   swdadapter.bottom.gbr swdadapter.bottommask.gbr swdadapter.fab.gbr swdadapter.top.gbr swdadapter.topmask.gbr swdadapter.toppaste.gbr swdadapter.topsilk.gbr swdadapter.plated-drill.cnc
+zip:   swdadapter.bottom.gbr swdadapter.bottommask.gbr swdadapter.fab.gbr swdadapter.top.gbr swdadapter.topmask.gbr swdadapter.topsilk.gbr swdadapter.plated-drill.cnc
        zip swdadapter.zip *.gbr *.cnc
 
 oshpark: swdadapter.bottom.gbr swdadapter.bottommask.gbr swdadapter.top.gbr swdadapter.topmask.gbr swdadapter.topsilk.gbr swdadapter.plated-drill.cnc
        mv swdadapter.bottom.gbr bottom\ layer.ger
        mv swdadapter.bottommask.gbr bottom\ solder\ mask.ger
-       mv swdadapter.bottomsilk.gbr bottom\ silk\ screen.ger
        mv swdadapter.outline.gbr board\ outline.ger
        mv swdadapter.top.gbr top\ layer.ger
        mv swdadapter.topmask.gbr top\ solder\ mask.ger
@@ -44,9 +43,6 @@ oshpark: swdadapter.bottom.gbr swdadapter.bottommask.gbr swdadapter.top.gbr swda
        mv swdadapter.plated-drill.cnc drills.xln
        zip swdadapter-oshpark.zip *.ger *.xln
 
-stencil:       swdadapter.bottom.gbr swdadapter.toppaste.gbr swdadapter.outline.gbr
-       zip swdadapter-stencil.zip swdadapter.toppaste.gbr swdadapter.outline.gbr
-
 clean:
        rm -f *.bom *.drc *.log *~ swdadapter.ps *.gbr *.cnc *bak* *- *.zip 
        rm -f *.net *.xy *.cmd *.png partslist partslist.csv
index 430e0ef665538c209ad9c3eb80c12286f5f9a100..42fefaaf6f9a211b8acd3cf7b6ee9813c3a2a55d 100644 (file)
@@ -938,6 +938,11 @@ Layer(2 "solder")
 )
 Layer(3 "outline")
 (
+       Attribute("PCB::skip-drc" "1")
+       Line[0.0000mil 0.0000mil 850.00mil 0.0000mil 10.00mil 20.00mil "lock"]
+       Line[850.0000mil 0.0000mil 850.00mil 1100.0000mil 10.00mil 20.00mil "lock"]
+       Line[850.0000mil 1100.0000mil 0.00mil 1100.0000mil 10.00mil 20.00mil "lock"]
+       Line[0.0000mil 1100.0000mil 0.00mil 0.0000mil 10.00mil 20.00mil "lock"]
 )
 Layer(4 "GND")
 (