PCB["cncfpga" 510000 200000]
Grid[100.0 0 0 0]
-Cursor[345100 2100 0.000000]
+Cursor[5200 30000 0.000000]
PolyArea[200000000.000000]
Thermal[0.500000]
DRC[600 1000 600 500 1500 700]
)
-Element["" "182-9" "J7" "GPIO" 61100 37900 54700 13300 0 100 ""]
+Element["" "182-9" "J7" "GPIO" 61100 37400 54700 13300 0 100 ""]
(
Pin[-21810 5591 7441 1417 8858 4291 "1" "1" "square,edge2"]
Pin[-16357 -5590 7441 1417 8858 4291 "6" "6" "edge2"]
)
-Element["" "189-15" "J4" "ZA" 214200 37900 -75600 39500 0 100 ""]
+Element["" "189-15" "J4" "ZA" 214200 37400 -75600 39500 0 100 ""]
(
Pin[-38168 5591 7874 1417 9291 4724 "1" "1" "square,edge2"]
Pin[-38168 31496 7874 1417 9291 4724 "16" "16" "square,edge2"]
)
-Element["" "189-15" "J3" "XY" 383400 37900 -73700 39600 0 100 ""]
+Element["" "189-15" "J3" "XY" 383400 37400 -73700 39600 0 100 ""]
(
Pin[-38168 5591 7874 1417 9291 4724 "1" "1" "square,edge2"]
Pin[-38168 31496 7874 1417 9291 4724 "16" "16" "square,edge2"]
)
-Element["" "182-25" "J1" "unknown" 144600 161800 -103491 -18591 0 100 ""]
+Element["" "182-25" "J1" "unknown" 144600 162600 -103491 -18591 0 100 ""]
(
Pin[65432 -5591 7441 1417 8858 4291 "1" "1" "square,edge2"]
Pin[59979 5590 7441 1417 8858 4291 "14" "14" "edge2"]
)
-Element["" "pj-037a" "J8" "unknown" 491800 485 -17115 58515 0 100 ""]
+Element["" "pj-037a" "J8" "unknown" 491800 0 -17115 58515 0 100 ""]
(
Pin[0 30315 15630 1417 17047 12480 "2" "2" "thermal(1X)"]
Pin[0 53937 17520 1417 18937 14370 "1" "1" ""]
Line[358600 150100 359800 151300 1000 2000 ""]
Line[359800 151300 375800 151300 1000 2000 ""]
Line[158900 50000 99800 50000 1000 2000 ""]
- Line[99800 50000 87700 37900 1000 2000 ""]
- Line[87800 37900 61338 37900 1000 2000 ""]
- Line[61238 37900 55648 32310 1000 2000 ""]
+ Line[99800 50000 87200 37400 1000 2000 ""]
Line[66553 32310 66553 32353 1000 2000 ""]
Line[66553 32500 66553 32447 1000 2000 ""]
Line[66553 32447 72500 26500 1000 2000 ""]
Line[343500 21900 406500 21900 1000 2000 ""]
Line[406500 21900 410600 26000 1000 2000 ""]
Line[388853 43491 388691 43491 1000 2000 ""]
- Line[388691 43491 383300 38100 1000 2000 ""]
- Line[383300 38100 340000 38100 1000 2000 ""]
- Line[340000 38100 338800 39300 1000 2000 ""]
Line[356137 43491 356137 43537 1000 2000 ""]
Line[356137 43537 363500 50900 1000 2000 ""]
Line[363500 50900 375400 50900 1000 2000 ""]
Line[185314 105000 185414 104900 1000 2000 ""]
Line[192500 104900 196900 104900 1000 2000 ""]
Line[196900 104900 197000 105000 1000 2000 ""]
+ Line[388409 43491 388409 43409 1000 2000 ""]
+ Line[388409 43409 382300 37300 1000 2000 ""]
+ Line[382300 37300 340100 37300 1000 2000 ""]
+ Line[340100 37300 338800 38600 1000 2000 ""]
+ Line[338800 38600 338800 39300 1000 2000 ""]
+ Line[87250 37450 61288 37450 1000 2000 ""]
+ Line[61288 37450 55648 31810 1000 2000 ""]
)
Layer(2 "GND plane")
(
Line[311800 116900 307000 116900 1000 2000 ""]
Line[307000 116900 289800 99700 1000 2000 ""]
Line[289800 99700 283200 99700 1000 2000 ""]
- Line[314500 103200 296700 103200 1000 2000 ""]
- Line[296700 103200 290000 96500 1000 2000 ""]
+ Line[296100 102600 290000 96500 1000 2000 ""]
Line[290000 96500 278900 96500 1000 2000 ""]
Line[318400 100500 298100 100500 1000 2000 ""]
Line[298100 100500 291300 93700 1000 2000 ""]
Line[225106 32294 239200 18200 1000 2000 ""]
Line[239200 18200 420500 18200 1000 2000 ""]
Line[420500 18200 420700 18000 1000 2000 ""]
+ Line[314500 103200 313300 103200 1000 2000 ""]
+ Line[313300 103200 312700 102600 1000 2000 ""]
+ Line[312700 102600 296100 102600 1000 2000 ""]
+ Line[296100 102600 296000 102500 1000 2000 ""]
)
Layer(5 "outline")
(
)
Layer(7 "silk")
(
- Text[351020 171925 0 200 "FPGA for LinuxCNC v0.1" ""]
- Text[350413 191979 0 100 "License TAPR OHL (http://www.tapr.org/OHL)" ""]
- Text[350413 184379 0 100 "` 2011 Bdale Garbee KB0G" ""]
+ Text[377520 165025 0 200 "CNC FPGA v0.1" ""]
+ Text[377113 191279 0 100 "http://gag.com/homeshop/cncfpga" ""]
+ Text[376913 177479 0 100 "` 2011 Bdale Garbee KB0G" ""]
+ Text[377113 184779 0 100 "License: http://tapr.org/OHL" ""]
)
NetList()
(