/*
- * pic18f4520.h - PIC18F4520 Device Library Header
- *
- * This file is part of the GNU PIC Library.
- *
- * May, 2005
- * The GNU PIC Library is maintained by
- * Raphael Neider <rneider AT web.de>
- *
- * originally designed by
- * Vangelis Rokas <vrokas@otenet.gr>
- *
- * $Id$
- *
+ * pic18f4520.h - device specific declarations
+ *
+ * This file is part of the GNU PIC library for SDCC,
+ * originally devised by Vangelis Rokas <vrokas AT otenet.gr>
+ *
+ * It has been automatically generated by inc2h-pic16.pl,
+ * (c) 2007 by Raphael Neider <rneider AT web.de>
*/
#ifndef __PIC18F4520_H__
#define __PIC18F4520_H__ 1
+
+
+// Configuration Bits
+#define __CONFIG1H 0x300001
+#define __CONFIG2L 0x300002
+#define __CONFIG2H 0x300003
+#define __CONFIG3H 0x300005
+#define __CONFIG4L 0x300006
+#define __CONFIG5L 0x300008
+#define __CONFIG5H 0x300009
+#define __CONFIG6L 0x30000A
+#define __CONFIG6H 0x30000B
+#define __CONFIG7L 0x30000C
+#define __CONFIG7H 0x30000D
+
+// CONFIG1H Options
+#define _OSC_LP_1H 0xF0 // LP oscillator
+#define _OSC_XT_1H 0xF1 // XT oscillator
+#define _OSC_HS_1H 0xF2 // HS oscillator
+#define _OSC_RC_1H 0xF3 // External RC oscillator, CLKO function on RA6
+#define _OSC_EC_1H 0xF4 // EC oscillator, CLKO function on RA6
+#define _OSC_ECIO6_1H 0xF5 // EC oscillator, port function on RA6
+#define _OSC_HSPLL_1H 0xF6 // HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1)
+#define _OSC_RCIO6_1H 0xF7 // External RC oscillator, port function on RA6
+#define _OSC_INTIO67_1H 0xF8 // Internal oscillator block, port function on RA6 and RA7
+#define _OSC_INTIO7_1H 0xF9 // Internal oscillator block, CLKO function on RA6, port function on RA7
+#define _FCMEN_OFF_1H 0xBF // Fail-Safe Clock Monitor disabled
+#define _FCMEN_ON_1H 0xFF // Fail-Safe Clock Monitor enabled
+#define _IESO_OFF_1H 0x7F // Oscillator Switchover mode disabled
+#define _IESO_ON_1H 0xFF // Oscillator Switchover mode enabled
+
+// CONFIG2L Options
+#define _PWRT_ON_2L 0xFE // PWRT enabled
+#define _PWRT_OFF_2L 0xFF // PWRT disabled
+#define _BOREN_OFF_2L 0xF9 // Brown-out Reset disabled in hardware and software
+#define _BOREN_ON_2L 0xFB // Brown-out Reset enabled and controlled by software (SBOREN is enabled)
+#define _BOREN_NOSLP_2L 0xFD // Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled)
+#define _BOREN_SBORDIS_2L 0xFF // Brown-out Reset enabled in hardware only (SBOREN is disabled)
+#define _BORV_0_2L 0xE7 // Maximum setting
+#define _BORV_1_2L 0xEF //
+#define _BORV_2_2L 0xF7 //
+#define _BORV_3_2L 0xFF // Minimum setting
+
+// CONFIG2H Options
+#define _WDT_OFF_2H 0xFE // WDT disabled (control is placed on the SWDTEN bit)
+#define _WDT_ON_2H 0xFF // WDT enabled
+#define _WDTPS_1_2H 0xE1 // 1:1
+#define _WDTPS_2_2H 0xE3 // 1:2
+#define _WDTPS_4_2H 0xE5 // 1:4
+#define _WDTPS_8_2H 0xE7 // 1:8
+#define _WDTPS_16_2H 0xE9 // 1:16
+#define _WDTPS_32_2H 0xEB // 1:32
+#define _WDTPS_64_2H 0xED // 1:64
+#define _WDTPS_128_2H 0xEF // 1:128
+#define _WDTPS_256_2H 0xF1 // 1:256
+#define _WDTPS_512_2H 0xF3 // 1:512
+#define _WDTPS_1024_2H 0xF5 // 1:1024
+#define _WDTPS_2048_2H 0xF7 // 1:2048
+#define _WDTPS_4096_2H 0xF9 // 1:4096
+#define _WDTPS_8192_2H 0xFB // 1:8192
+#define _WDTPS_16384_2H 0xFD // 1:16384
+#define _WDTPS_32768_2H 0xFF // 1:32768
+
+// CONFIG3H Options
+#define _MCLRE_OFF_3H 0x7F // RE3 input pin enabled; MCLR disabled
+#define _MCLRE_ON_3H 0xFF // MCLR pin enabled; RE3 input pin disabled
+#define _LPT1OSC_OFF_3H 0xFB // Timer1 configured for higher power operation
+#define _LPT1OSC_ON_3H 0xFF // Timer1 configured for low-power operation
+#define _PBADEN_OFF_3H 0xFD // PORTB<4:0> pins are configured as digital I/O on Reset
+#define _PBADEN_ON_3H 0xFF // PORTB<4:0> pins are configured as analog input channels on Reset
+#define _CCP2MX_PORTBE_3H 0xFE // CCP2 input/output is multiplexed with RB3
+#define _CCP2MX_PORTC_3H 0xFF // CCP2 input/output is multiplexed with RC1
+
+// CONFIG4L Options
+#define _STVREN_OFF_4L 0xFE // Stack full/underflow will not cause Reset
+#define _STVREN_ON_4L 0xFF // Stack full/underflow will cause Reset
+#define _LVP_OFF_4L 0xFB // Single-Supply ICSP disabled
+#define _LVP_ON_4L 0xFF // Single-Supply ICSP enabled
+#define _XINST_OFF_4L 0xBF // Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
+#define _XINST_ON_4L 0xFF // Instruction set extension and Indexed Addressing mode enabled
+#define _DEBUG_ON_4L 0x7F // Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
+#define _DEBUG_OFF_4L 0xFF // Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins
+
+// CONFIG5L Options
+#define _CP0_ON_5L 0xFE // Block 0 (000800-001FFFh) code-protected
+#define _CP0_OFF_5L 0xFF // Block 0 (000800-001FFFh) not code-protected
+#define _CP1_ON_5L 0xFD // Block 1 (002000-003FFFh) code-protected
+#define _CP1_OFF_5L 0xFF // Block 1 (002000-003FFFh) not code-protected
+#define _CP2_ON_5L 0xFB // Block 2 (004000-005FFFh) code-protected
+#define _CP2_OFF_5L 0xFF // Block 2 (004000-005FFFh) not code-protected
+#define _CP3_ON_5L 0xF7 // Block 3 (006000-007FFFh) code-protected
+#define _CP3_OFF_5L 0xFF // Block 3 (006000-007FFFh) not code-protected
+
+// CONFIG5H Options
+#define _CPB_ON_5H 0xBF // Boot block (000000-0007FFh) code-protected
+#define _CPB_OFF_5H 0xFF // Boot block (000000-0007FFh) not code-protected
+#define _CPD_ON_5H 0x7F // Data EEPROM code-protected
+#define _CPD_OFF_5H 0xFF // Data EEPROM not code-protected
+
+// CONFIG6L Options
+#define _WRT0_ON_6L 0xFE // Block 0 (000800-001FFFh) write-protected
+#define _WRT0_OFF_6L 0xFF // Block 0 (000800-001FFFh) not write-protected
+#define _WRT1_ON_6L 0xFD // Block 1 (002000-003FFFh) write-protected
+#define _WRT1_OFF_6L 0xFF // Block 1 (002000-003FFFh) not write-protected
+#define _WRT2_ON_6L 0xFB // Block 2 (004000-005FFFh) write-protected
+#define _WRT2_OFF_6L 0xFF // Block 2 (004000-005FFFh) not write-protected
+#define _WRT3_ON_6L 0xF7 // Block 3 (006000-007FFFh) write-protected
+#define _WRT3_OFF_6L 0xFF // Block 3 (006000-007FFFh) not write-protected
+
+// CONFIG6H Options
+#define _WRTB_ON_6H 0xBF // Boot block (000000-0007FFh) write-protected
+#define _WRTB_OFF_6H 0xFF // Boot block (000000-0007FFh) not write-protected
+#define _WRTC_ON_6H 0xDF // Configuration registers (300000-3000FFh) write-protected
+#define _WRTC_OFF_6H 0xFF // Configuration registers (300000-3000FFh) not write-protected
+#define _WRTD_ON_6H 0x7F // Data EEPROM write-protected
+#define _WRTD_OFF_6H 0xFF // Data EEPROM not write-protected
+
+// CONFIG7L Options
+#define _EBTR0_ON_7L 0xFE // Block 0 (000800-001FFFh) protected from table reads executed in other blocks
+#define _EBTR0_OFF_7L 0xFF // Block 0 (000800-001FFFh) not protected from table reads executed in other blocks
+#define _EBTR1_ON_7L 0xFD // Block 1 (002000-003FFFh) protected from table reads executed in other blocks
+#define _EBTR1_OFF_7L 0xFF // Block 1 (002000-003FFFh) not protected from table reads executed in other blocks
+#define _EBTR2_ON_7L 0xFB // Block 2 (004000-005FFFh) protected from table reads executed in other blocks
+#define _EBTR2_OFF_7L 0xFF // Block 2 (004000-005FFFh) not protected from table reads executed in other blocks
+#define _EBTR3_ON_7L 0xF7 // Block 3 (006000-007FFFh) protected from table reads executed in other blocks
+#define _EBTR3_OFF_7L 0xFF // Block 3 (006000-007FFFh) not protected from table reads executed in other blocks
+
+// CONFIG7H Options
+#define _EBTRB_ON_7H 0xBF // Boot block (000000-0007FFh) protected from table reads executed in other blocks
+#define _EBTRB_OFF_7H 0xFF // Boot block (000000-0007FFh) not protected from table reads executed in other blocks
+#define _DEVID1 0x3FFFFE
+#define _DEVID2 0x3FFFFF
+#define _IDLOC0 0x200000
+#define _IDLOC1 0x200001
+#define _IDLOC2 0x200002
+#define _IDLOC3 0x200003
+#define _IDLOC4 0x200004
+#define _IDLOC5 0x200005
+#define _IDLOC6 0x200006
+#define _IDLOC7 0x200007
+
extern __sfr __at (0xF80) PORTA;
typedef union {
struct {
unsigned RA7 : 1;
};
struct {
- unsigned RA : 8;
+ unsigned AN0 : 1;
+ unsigned AN1 : 1;
+ unsigned AN2 : 1;
+ unsigned AN3 : 1;
+ unsigned T0CKI : 1;
+ unsigned AN4 : 1;
+ unsigned OSC2 : 1;
+ unsigned OSC1 : 1;
};
- /* aliases */
struct {
- unsigned C1INN :1;
- unsigned C2INN :1;
- unsigned C2INP :1;
- unsigned C1INP :1;
- unsigned C1OUT :1;
- unsigned C2OUT :1;
- unsigned OSC2 :1;
- unsigned OSC1 :1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned VREFN : 1;
+ unsigned VREFP : 1;
+ unsigned : 1;
+ unsigned SS : 1;
+ unsigned CLKO : 1;
+ unsigned CLKI : 1;
};
struct {
- unsigned AN0 :1;
- unsigned AN1 :1;
- unsigned AN2 :1;
- unsigned AN3 :1;
- unsigned T0CKI :1;
- unsigned AN4 :1;
- unsigned :1;
- unsigned :1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned CVREF : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned NOT_SS : 1;
+ unsigned : 1;
+ unsigned : 1;
+ };
+ struct {
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned C1OUT : 1;
+ unsigned C2OUT : 1;
+ unsigned : 1;
+ unsigned : 1;
+ };
+ struct {
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned LVDIN : 1;
+ unsigned : 1;
+ unsigned : 1;
};
-} __PORTA_t;
-extern volatile __PORTA_t __at (0xF80) PORTAbits;
+} __PORTAbits_t;
+extern volatile __PORTAbits_t __at (0xF80) PORTAbits;
extern __sfr __at (0xF81) PORTB;
typedef union {
unsigned RB7 : 1;
};
struct {
- unsigned RB : 8;
+ unsigned INT0 : 1;
+ unsigned INT1 : 1;
+ unsigned INT2 : 1;
+ unsigned CCP2_PORTB : 1;
+ unsigned KBI0 : 1;
+ unsigned KBI1 : 1;
+ unsigned KBI2 : 1;
+ unsigned KBI3 : 1;
};
- /* aliases */
struct {
- unsigned AN12 :1;
- unsigned AN10 :1;
- unsigned AN8 :1;
- unsigned AN9 :1;
- unsigned AN11 :1;
- unsigned :1;
- unsigned :1;
- unsigned :1;
+ unsigned AN12 : 1;
+ unsigned AN10 : 1;
+ unsigned AN8 : 1;
+ unsigned AN9 : 1;
+ unsigned AN11 : 1;
+ unsigned PGM : 1;
+ unsigned PGC : 1;
+ unsigned PGD : 1;
};
-} __PORTB_t;
-extern volatile __PORTB_t __at (0xF81) PORTBbits;
+} __PORTBbits_t;
+extern volatile __PORTBbits_t __at (0xF81) PORTBbits;
extern __sfr __at (0xF82) PORTC;
typedef union {
unsigned RC7 : 1;
};
struct {
- unsigned RC : 8;
- };
- /* aliases */
- struct {
- unsigned T1CKI :1;
- unsigned T1OSCI :1;
- unsigned ECCPA :1;
- unsigned :1;
- unsigned :1;
- unsigned :1;
- unsigned U1TX :1;
- unsigned U1RX :1;
+ unsigned T1OSO : 1;
+ unsigned T1OSI : 1;
+ unsigned CCP1 : 1;
+ unsigned SCK : 1;
+ unsigned SDI : 1;
+ unsigned SDO : 1;
+ unsigned TX : 1;
+ unsigned RX : 1;
};
struct {
- unsigned T3CKI :1;
- unsigned :1;
- unsigned :1;
- unsigned :1;
- unsigned :1;
- unsigned :1;
- unsigned :1;
- unsigned :1;
+ unsigned T13CKI : 1;
+ unsigned CCP2_PORTC : 1;
+ unsigned P1A : 1;
+ unsigned SCL : 1;
+ unsigned SDA : 1;
+ unsigned : 1;
+ unsigned CK : 1;
+ unsigned DT : 1;
};
struct {
- unsigned T1OSCO :1;
- unsigned :1;
- unsigned :1;
- unsigned :1;
- unsigned :1;
- unsigned :1;
- unsigned :1;
- unsigned :1;
+ unsigned T1CKI : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
};
-} __PORTC_t;
-extern volatile __PORTC_t __at (0xF82) PORTCbits;
+} __PORTCbits_t;
+extern volatile __PORTCbits_t __at (0xF82) PORTCbits;
extern __sfr __at (0xF83) PORTD;
typedef union {
unsigned RD7 : 1;
};
struct {
- unsigned RD : 8;
+ unsigned PSP0 : 1;
+ unsigned PSP1 : 1;
+ unsigned PSP2 : 1;
+ unsigned PSP3 : 1;
+ unsigned PSP4 : 1;
+ unsigned PSP5 : 1;
+ unsigned PSP6 : 1;
+ unsigned PSP7 : 1;
};
- /* aliases */
struct {
- unsigned :1;
- unsigned :1;
- unsigned :1;
- unsigned :1;
- unsigned :1;
- unsigned ECCPB :1;
- unsigned ECCPC :1;
- unsigned ECCPD :1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned P1B : 1;
+ unsigned P1C : 1;
+ unsigned P1D : 1;
};
-} __PORTD_t;
-extern volatile __PORTD_t __at (0xF83) PORTDbits;
+} __PORTDbits_t;
+extern volatile __PORTDbits_t __at (0xF83) PORTDbits;
extern __sfr __at (0xF84) PORTE;
typedef union {
unsigned : 1;
};
struct {
- unsigned RE : 8;
+ unsigned RD : 1;
+ unsigned WR : 1;
+ unsigned CS : 1;
+ unsigned MCLR : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
};
- /* aliases */
struct {
- unsigned AN5 :1;
- unsigned AN6 :1;
- unsigned AN7 :1;
- unsigned MCLR :1;
- unsigned :1;
- unsigned :1;
- unsigned :1;
- unsigned :1;
+ unsigned NOT_RD : 1;
+ unsigned NOT_WR : 1;
+ unsigned NOT_CS : 1;
+ unsigned NOT_MCLR : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
};
-} __PORTE_t;
-extern volatile __PORTE_t __at (0xF84) PORTEbits;
+ struct {
+ unsigned AN5 : 1;
+ unsigned AN6 : 1;
+ unsigned AN7 : 1;
+ unsigned VPP : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
+ };
+} __PORTEbits_t;
+extern volatile __PORTEbits_t __at (0xF84) PORTEbits;
extern __sfr __at (0xF89) LATA;
typedef union {
unsigned LATA6 : 1;
unsigned LATA7 : 1;
};
-} __LATA_t;
-extern volatile __LATA_t __at (0xF89) LATAbits;
+} __LATAbits_t;
+extern volatile __LATAbits_t __at (0xF89) LATAbits;
extern __sfr __at (0xF8A) LATB;
typedef union {
unsigned LATB6 : 1;
unsigned LATB7 : 1;
};
-} __LATB_t;
-extern volatile __LATB_t __at (0xF8A) LATBbits;
+} __LATBbits_t;
+extern volatile __LATBbits_t __at (0xF8A) LATBbits;
extern __sfr __at (0xF8B) LATC;
typedef union {
unsigned LATC6 : 1;
unsigned LATC7 : 1;
};
-} __LATC_t;
-extern volatile __LATC_t __at (0xF8B) LATCbits;
+} __LATCbits_t;
+extern volatile __LATCbits_t __at (0xF8B) LATCbits;
extern __sfr __at (0xF8C) LATD;
typedef union {
unsigned LATD6 : 1;
unsigned LATD7 : 1;
};
-} __LATD_t;
-extern volatile __LATD_t __at (0xF8C) LATDbits;
+} __LATDbits_t;
+extern volatile __LATDbits_t __at (0xF8C) LATDbits;
extern __sfr __at (0xF8D) LATE;
typedef union {
unsigned : 1;
unsigned : 1;
};
-} __LATE_t;
-extern volatile __LATE_t __at (0xF8D) LATEbits;
+} __LATEbits_t;
+extern volatile __LATEbits_t __at (0xF8D) LATEbits;
+
+extern __sfr __at (0xF92) DDRA;
+typedef union {
+ struct {
+ unsigned RA0 : 1;
+ unsigned RA1 : 1;
+ unsigned RA2 : 1;
+ unsigned RA3 : 1;
+ unsigned RA4 : 1;
+ unsigned RA5 : 1;
+ unsigned RA6 : 1;
+ unsigned RA7 : 1;
+ };
+} __DDRAbits_t;
+extern volatile __DDRAbits_t __at (0xF92) DDRAbits;
extern __sfr __at (0xF92) TRISA;
typedef union {
unsigned TRISA6 : 1;
unsigned TRISA7 : 1;
};
-} __TRISA_t;
-extern volatile __TRISA_t __at (0xF92) TRISAbits;
+} __TRISAbits_t;
+extern volatile __TRISAbits_t __at (0xF92) TRISAbits;
+
+extern __sfr __at (0xF93) DDRB;
+typedef union {
+ struct {
+ unsigned RB0 : 1;
+ unsigned RB1 : 1;
+ unsigned RB2 : 1;
+ unsigned RB3 : 1;
+ unsigned RB4 : 1;
+ unsigned RB5 : 1;
+ unsigned RB6 : 1;
+ unsigned RB7 : 1;
+ };
+} __DDRBbits_t;
+extern volatile __DDRBbits_t __at (0xF93) DDRBbits;
extern __sfr __at (0xF93) TRISB;
typedef union {
unsigned TRISB6 : 1;
unsigned TRISB7 : 1;
};
-} __TRISB_t;
-extern volatile __TRISB_t __at (0xF93) TRISBbits;
+} __TRISBbits_t;
+extern volatile __TRISBbits_t __at (0xF93) TRISBbits;
+
+extern __sfr __at (0xF94) DDRC;
+typedef union {
+ struct {
+ unsigned RC0 : 1;
+ unsigned RC1 : 1;
+ unsigned RC2 : 1;
+ unsigned RC3 : 1;
+ unsigned RC4 : 1;
+ unsigned RC5 : 1;
+ unsigned RC6 : 1;
+ unsigned RC7 : 1;
+ };
+} __DDRCbits_t;
+extern volatile __DDRCbits_t __at (0xF94) DDRCbits;
extern __sfr __at (0xF94) TRISC;
typedef union {
unsigned TRISC6 : 1;
unsigned TRISC7 : 1;
};
-} __TRISC_t;
-extern volatile __TRISC_t __at (0xF94) TRISCbits;
+} __TRISCbits_t;
+extern volatile __TRISCbits_t __at (0xF94) TRISCbits;
+
+extern __sfr __at (0xF95) DDRD;
+typedef union {
+ struct {
+ unsigned RD0 : 1;
+ unsigned RD1 : 1;
+ unsigned RD2 : 1;
+ unsigned RD3 : 1;
+ unsigned RD4 : 1;
+ unsigned RD5 : 1;
+ unsigned RD6 : 1;
+ unsigned RD7 : 1;
+ };
+} __DDRDbits_t;
+extern volatile __DDRDbits_t __at (0xF95) DDRDbits;
extern __sfr __at (0xF95) TRISD;
typedef union {
unsigned TRISD6 : 1;
unsigned TRISD7 : 1;
};
-} __TRISD_t;
-extern volatile __TRISD_t __at (0xF95) TRISDbits;
+} __TRISDbits_t;
+extern volatile __TRISDbits_t __at (0xF95) TRISDbits;
+
+extern __sfr __at (0xF96) DDRE;
+typedef union {
+ struct {
+ unsigned RE0 : 1;
+ unsigned RE1 : 1;
+ unsigned RE2 : 1;
+ unsigned RE3 : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
+ };
+} __DDREbits_t;
+extern volatile __DDREbits_t __at (0xF96) DDREbits;
extern __sfr __at (0xF96) TRISE;
typedef union {
unsigned OBF : 1;
unsigned IBF : 1;
};
-} __TRISE_t;
-extern volatile __TRISE_t __at (0xF96) TRISEbits;
+} __TRISEbits_t;
+extern volatile __TRISEbits_t __at (0xF96) TRISEbits;
extern __sfr __at (0xF9B) OSCTUNE;
typedef union {
struct {
- unsigned TUN : 5;
+ unsigned TUN0 : 1;
+ unsigned TUN1 : 1;
+ unsigned TUN2 : 1;
+ unsigned TUN3 : 1;
+ unsigned TUN4 : 1;
unsigned : 1;
unsigned PLLEN : 1;
- unsigned HF256DIV : 1;
+ unsigned INTSRC : 1;
};
-} __OSCTUNE_t;
-extern volatile __OSCTUNE_t __at (0xF9B) OSCTUNEbits;
+} __OSCTUNEbits_t;
+extern volatile __OSCTUNEbits_t __at (0xF9B) OSCTUNEbits;
extern __sfr __at (0xF9D) PIE1;
typedef union {
unsigned ADIE : 1;
unsigned PSPIE : 1;
};
-} __PIE1_t;
-extern volatile __PIE1_t __at (0xF9D) PIE1bits;
+} __PIE1bits_t;
+extern volatile __PIE1bits_t __at (0xF9D) PIE1bits;
extern __sfr __at (0xF9E) PIR1;
typedef union {
unsigned ADIF : 1;
unsigned PSPIF : 1;
};
-} __PIR1_t;
-extern volatile __PIR1_t __at (0xF9E) PIR1bits;
+} __PIR1bits_t;
+extern volatile __PIR1bits_t __at (0xF9E) PIR1bits;
extern __sfr __at (0xF9F) IPR1;
typedef union {
unsigned ADIP : 1;
unsigned PSPIP : 1;
};
-} __IPR1_t;
-extern volatile __IPR1_t __at (0xF9F) IPR1bits;
+} __IPR1bits_t;
+extern volatile __IPR1bits_t __at (0xF9F) IPR1bits;
extern __sfr __at (0xFA0) PIE2;
typedef union {
struct {
unsigned CCP2IE : 1;
unsigned TMR3IE : 1;
- unsigned LVDIE : 1;
+ unsigned HLVDIE : 1;
unsigned BCLIE : 1;
unsigned EEIE : 1;
unsigned : 1;
unsigned CMIE : 1;
unsigned OSCFIE : 1;
};
-} __PIE2_t;
-extern volatile __PIE2_t __at (0xFA0) PIE2bits;
+ struct {
+ unsigned : 1;
+ unsigned : 1;
+ unsigned LVDIE : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
+ };
+} __PIE2bits_t;
+extern volatile __PIE2bits_t __at (0xFA0) PIE2bits;
extern __sfr __at (0xFA1) PIR2;
typedef union {
struct {
unsigned CCP2IF : 1;
unsigned TMR3IF : 1;
- unsigned LVDIF : 1;
+ unsigned HLVDIF : 1;
unsigned BCLIF : 1;
unsigned EEIF : 1;
unsigned : 1;
unsigned CMIF : 1;
unsigned OSCFIF : 1;
};
-} __PIR2_t;
-extern volatile __PIR2_t __at (0xFA1) PIR2bits;
+ struct {
+ unsigned : 1;
+ unsigned : 1;
+ unsigned LVDIF : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
+ };
+} __PIR2bits_t;
+extern volatile __PIR2bits_t __at (0xFA1) PIR2bits;
extern __sfr __at (0xFA2) IPR2;
typedef union {
struct {
unsigned CCP2IP : 1;
unsigned TMR3IP : 1;
- unsigned LVDIP : 1;
+ unsigned HLVDIP : 1;
unsigned BCLIP : 1;
unsigned EEIP : 1;
unsigned : 1;
unsigned CMIP : 1;
unsigned OSCFIP : 1;
};
-} __IPR2_t;
-extern volatile __IPR2_t __at (0xFA2) IPR2bits;
+ struct {
+ unsigned : 1;
+ unsigned : 1;
+ unsigned LVDIP : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
+ };
+} __IPR2bits_t;
+extern volatile __IPR2bits_t __at (0xFA2) IPR2bits;
extern __sfr __at (0xFA6) EECON1;
typedef union {
unsigned CFGS : 1;
unsigned EEPGD : 1;
};
-} __EECON1_t;
-extern volatile __EECON1_t __at (0xFA6) EECON1bits;
+} __EECON1bits_t;
+extern volatile __EECON1bits_t __at (0xFA6) EECON1bits;
extern __sfr __at (0xFA7) EECON2;
unsigned RX9D : 1;
unsigned OERR : 1;
unsigned FERR : 1;
- unsigned ADDEN : 1;
+ unsigned ADEN : 1;
unsigned CREN : 1;
unsigned SREN : 1;
unsigned RX9 : 1;
unsigned SPEN : 1;
};
-} __RCSTA_t;
-extern volatile __RCSTA_t __at (0xFAB) RCSTAbits;
+ struct {
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned ADDEN : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
+ };
+} __RCSTAbits_t;
+extern volatile __RCSTAbits_t __at (0xFAB) RCSTAbits;
extern __sfr __at (0xFAC) TXSTA;
typedef union {
unsigned TX9 : 1;
unsigned CSRC : 1;
};
-} __TXSTA_t;
-extern volatile __TXSTA_t __at (0xFAC) TXSTAbits;
+} __TXSTAbits_t;
+extern volatile __TXSTAbits_t __at (0xFAC) TXSTAbits;
extern __sfr __at (0xFAD) TXREG;
struct {
unsigned TMR3ON : 1;
unsigned TMR3CS : 1;
- unsigned NOT_T3SYNC : 1;
+ unsigned T3SYNC : 1;
unsigned T3CCP1 : 1;
- unsigned T3CKPS0 : 1;
- unsigned T3CKPS1 : 1;
+ unsigned T3CKPS0 : 1;
+ unsigned T3CKPS1 : 1;
unsigned T3CCP2 : 1;
unsigned RD16 : 1;
};
-} __T3CON_t;
-extern volatile __T3CON_t __at (0xFB1) T3CONbits;
+ struct {
+ unsigned : 1;
+ unsigned : 1;
+ unsigned NOT_T3SYNC : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
+ };
+} __T3CONbits_t;
+extern volatile __T3CONbits_t __at (0xFB1) T3CONbits;
extern __sfr __at (0xFB2) TMR3L;
unsigned C1OUT : 1;
unsigned C2OUT : 1;
};
-} __CMCON_t;
-extern volatile __CMCON_t __at (0xFB4) CMCONbits;
+} __CMCONbits_t;
+extern volatile __CMCONbits_t __at (0xFB4) CMCONbits;
extern __sfr __at (0xFB5) CVRCON;
typedef union {
unsigned CVROE : 1;
unsigned CVREN : 1;
};
-} __CVRCON_t;
-extern volatile __CVRCON_t __at (0xFB5) CVRCONbits;
+} __CVRCONbits_t;
+extern volatile __CVRCONbits_t __at (0xFB5) CVRCONbits;
-extern __sfr __at (0xFB6) ECCPAS1;
+extern __sfr __at (0xFB6) ECCP1AS;
typedef union {
struct {
unsigned PSSBD0 : 1;
unsigned ECCPAS2 : 1;
unsigned ECCPASE : 1;
};
-} __ECCPAS1_t;
-extern volatile __ECCPAS1_t __at (0xFB6) ECCPAS1bits;
+} __ECCP1ASbits_t;
+extern volatile __ECCP1ASbits_t __at (0xFB6) ECCP1ASbits;
extern __sfr __at (0xFB7) PWM1CON;
typedef union {
struct {
- unsigned PDC : 7;
+ unsigned PDC0 : 1;
+ unsigned PDC1 : 1;
+ unsigned PDC2 : 1;
+ unsigned PDC3 : 1;
+ unsigned PDC4 : 1;
+ unsigned PDC5 : 1;
+ unsigned PDC6 : 1;
unsigned PRSEN : 1;
};
-} __PWM1CON_t;
-extern volatile __PWM1CON_t __at (0xFB7) PWM1CONbits;
+} __PWM1CONbits_t;
+extern volatile __PWM1CONbits_t __at (0xFB7) PWM1CONbits;
extern __sfr __at (0xFB8) BAUDCON;
typedef union {
unsigned BRG16 : 1;
unsigned SCKP : 1;
unsigned : 1;
+ unsigned RCIDL : 1;
+ unsigned ABDOVF : 1;
+ };
+ struct {
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
unsigned RCMT : 1;
+ unsigned : 1;
+ };
+} __BAUDCONbits_t;
+extern volatile __BAUDCONbits_t __at (0xFB8) BAUDCONbits;
+
+extern __sfr __at (0xFB8) BAUDCTL;
+typedef union {
+ struct {
+ unsigned ABDEN : 1;
+ unsigned WUE : 1;
+ unsigned : 1;
+ unsigned BRG16 : 1;
+ unsigned SCKP : 1;
+ unsigned : 1;
+ unsigned RCIDL : 1;
unsigned ABDOVF : 1;
};
-} __BAUDCON_t;
-extern volatile __BAUDCON_t __at (0xFB8) BAUDCONbits;
+ struct {
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned RCMT : 1;
+ unsigned : 1;
+ };
+} __BAUDCTLbits_t;
+extern volatile __BAUDCTLbits_t __at (0xFB8) BAUDCTLbits;
extern __sfr __at (0xFBA) CCP2CON;
typedef union {
unsigned : 1;
unsigned : 1;
};
-} __CCP2CON_t;
-extern volatile __CCP2CON_t __at (0xFBA) CCP2CONbits;
+ struct {
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned CCP2Y : 1;
+ unsigned CCP2X : 1;
+ unsigned : 1;
+ unsigned : 1;
+ };
+} __CCP2CONbits_t;
+extern volatile __CCP2CONbits_t __at (0xFBA) CCP2CONbits;
+
+extern __sfr __at (0xFBB) CCPR2;
extern __sfr __at (0xFBB) CCPR2L;
extern __sfr __at (0xFBC) CCPR2H;
-extern __sfr __at (0xFBD) ECCP1CON;
+extern __sfr __at (0xFBD) CCP1CON;
typedef union {
struct {
unsigned CCP1M0 : 1;
unsigned P1M0 : 1;
unsigned P1M1 : 1;
};
-} __ECCP1CON_t;
-extern volatile __ECCP1CON_t __at (0xFBD) ECCP1CONbits;
+ struct {
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned CCP1Y : 1;
+ unsigned CCP1X : 1;
+ unsigned : 1;
+ unsigned : 1;
+ };
+} __CCP1CONbits_t;
+extern volatile __CCP1CONbits_t __at (0xFBD) CCP1CONbits;
+
+extern __sfr __at (0xFBE) CCPR1;
extern __sfr __at (0xFBE) CCPR1L;
unsigned : 1;
unsigned ADFM : 1;
};
-} __ADCON2_t;
-extern volatile __ADCON2_t __at (0xFC0) ADCON2bits;
+} __ADCON2bits_t;
+extern volatile __ADCON2bits_t __at (0xFC0) ADCON2bits;
extern __sfr __at (0xFC1) ADCON1;
typedef union {
unsigned : 1;
unsigned : 1;
};
-} __ADCON1_t;
-extern volatile __ADCON1_t __at (0xFC1) ADCON1bits;
+} __ADCON1bits_t;
+extern volatile __ADCON1bits_t __at (0xFC1) ADCON1bits;
extern __sfr __at (0xFC2) ADCON0;
typedef union {
struct {
unsigned ADON : 1;
- unsigned GO : 1;
- unsigned CHS0 : 1;
- unsigned CHS1 : 1;
- unsigned CHS2 : 1;
- unsigned CHS3 : 1;
+ unsigned GO : 1;
+ unsigned CHS0 : 1;
+ unsigned CHS1 : 1;
+ unsigned CHS2 : 1;
+ unsigned CHS3 : 1;
+ unsigned : 1;
+ unsigned : 1;
+ };
+ struct {
+ unsigned : 1;
+ unsigned DONE : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
unsigned : 1;
unsigned : 1;
};
-} __ADCON0_t;
-extern volatile __ADCON0_t __at (0xFC2) ADCON0bits;
+ struct {
+ unsigned : 1;
+ unsigned NOT_DONE : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
+ };
+ struct {
+ unsigned : 1;
+ unsigned GO_DONE : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
+ };
+} __ADCON0bits_t;
+extern volatile __ADCON0bits_t __at (0xFC2) ADCON0bits;
+
+extern __sfr __at (0xFC3) ADRES;
extern __sfr __at (0xFC3) ADRESL;
unsigned ACKSTAT : 1;
unsigned GCEN : 1;
};
-} __SSPCON2_t;
-extern volatile __SSPCON2_t __at (0xFC5) SSPCON2bits;
+} __SSPCON2bits_t;
+extern volatile __SSPCON2bits_t __at (0xFC5) SSPCON2bits;
extern __sfr __at (0xFC6) SSPCON1;
typedef union {
struct {
- unsigned SSPM0 : 1;
- unsigned SSPM1 : 1;
- unsigned SSPM2 : 1;
- unsigned SSPM3 : 1;
+ unsigned SSPM0 : 1;
+ unsigned SSPM1 : 1;
+ unsigned SSPM2 : 1;
+ unsigned SSPM3 : 1;
unsigned CKP : 1;
unsigned SSPEN : 1;
unsigned SSPOV : 1;
unsigned WCOL : 1;
};
-} __SSPCON1_t;
-extern volatile __SSPCON1_t __at (0xFC6) SSPCON1bits;
+} __SSPCON1bits_t;
+extern volatile __SSPCON1bits_t __at (0xFC6) SSPCON1bits;
extern __sfr __at (0xFC7) SSPSTAT;
typedef union {
struct {
unsigned BF : 1;
unsigned UA : 1;
- unsigned R_W : 1;
+ unsigned R : 1;
unsigned S : 1;
unsigned P : 1;
- unsigned D_A : 1;
+ unsigned D : 1;
unsigned CKE : 1;
unsigned SMP : 1;
};
-} __SSPSTAT_t;
-extern volatile __SSPSTAT_t __at (0xFC7) SSPSTATbits;
+ struct {
+ unsigned : 1;
+ unsigned : 1;
+ unsigned NOT_W : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned NOT_A : 1;
+ unsigned : 1;
+ unsigned : 1;
+ };
+ struct {
+ unsigned : 1;
+ unsigned : 1;
+ unsigned R_W : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned D_A : 1;
+ unsigned : 1;
+ unsigned : 1;
+ };
+ struct {
+ unsigned : 1;
+ unsigned : 1;
+ unsigned NOT_WRITE : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned NOT_ADDRESS : 1;
+ unsigned : 1;
+ unsigned : 1;
+ };
+} __SSPSTATbits_t;
+extern volatile __SSPSTATbits_t __at (0xFC7) SSPSTATbits;
extern __sfr __at (0xFC8) SSPADD;
unsigned T2CKPS0 : 1;
unsigned T2CKPS1 : 1;
unsigned TMR2ON : 1;
- unsigned TOUTPS0 : 1;
- unsigned TOUTPS1 : 1;
- unsigned TOUTPS2 : 1;
- unsigned TOUTPS3 : 1;
+ unsigned T2OUTPS0 : 1;
+ unsigned T2OUTPS1 : 1;
+ unsigned T2OUTPS2 : 1;
+ unsigned T2OUTPS3 : 1;
unsigned : 1;
};
-} __T2CON_t;
-extern volatile __T2CON_t __at (0xFCA) T2CONbits;
+} __T2CONbits_t;
+extern volatile __T2CONbits_t __at (0xFCA) T2CONbits;
extern __sfr __at (0xFCB) PR2;
struct {
unsigned TMR1ON : 1;
unsigned TMR1CS : 1;
- unsigned NOT_T1SYNC : 1;
+ unsigned T1SYNC : 1;
unsigned T1OSCEN : 1;
unsigned T1CKPS0 : 1;
unsigned T1CKPS1 : 1;
unsigned T1RUN : 1;
unsigned RD16 : 1;
};
-} __T1CON_t;
-extern volatile __T1CON_t __at (0xFCD) T1CONbits;
+ struct {
+ unsigned : 1;
+ unsigned : 1;
+ unsigned NOT_T1SYNC : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
+ };
+} __T1CONbits_t;
+extern volatile __T1CONbits_t __at (0xFCD) T1CONbits;
extern __sfr __at (0xFCE) TMR1L;
extern __sfr __at (0xFD0) RCON;
typedef union {
struct {
- unsigned BOR : 1;
- unsigned POR : 1;
- unsigned PD : 1;
- unsigned TO : 1;
- unsigned RI : 1;
+ unsigned BOR : 1;
+ unsigned POR : 1;
+ unsigned PD : 1;
+ unsigned TO : 1;
+ unsigned RI : 1;
unsigned : 1;
unsigned SBOREN : 1;
unsigned IPEN : 1;
};
-} __RCON_t;
-extern volatile __RCON_t __at (0xFD0) RCONbits;
+ struct {
+ unsigned NOT_BOR : 1;
+ unsigned NOT_POR : 1;
+ unsigned NOT_PD : 1;
+ unsigned NOT_TO : 1;
+ unsigned NOT_RI : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
+ };
+} __RCONbits_t;
+extern volatile __RCONbits_t __at (0xFD0) RCONbits;
extern __sfr __at (0xFD1) WDTCON;
typedef union {
unsigned : 1;
unsigned : 1;
};
-} __WDTCON_t;
-extern volatile __WDTCON_t __at (0xFD1) WDTCONbits;
+ struct {
+ unsigned SWDTE : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
+ };
+} __WDTCONbits_t;
+extern volatile __WDTCONbits_t __at (0xFD1) WDTCONbits;
+
+extern __sfr __at (0xFD2) HLVDCON;
+typedef union {
+ struct {
+ unsigned LVDL0 : 1;
+ unsigned LVDL1 : 1;
+ unsigned LVDL2 : 1;
+ unsigned LVDL3 : 1;
+ unsigned LVDEN : 1;
+ unsigned IRVST : 1;
+ unsigned : 1;
+ unsigned VDIRMAG : 1;
+ };
+ struct {
+ unsigned LVV0 : 1;
+ unsigned LVV1 : 1;
+ unsigned LVV2 : 1;
+ unsigned LVV3 : 1;
+ unsigned HLVDEN : 1;
+ unsigned BGST : 1;
+ unsigned : 1;
+ unsigned : 1;
+ };
+ struct {
+ unsigned HLVDL0 : 1;
+ unsigned HLVDL1 : 1;
+ unsigned HLVDL2 : 1;
+ unsigned HLVDL3 : 1;
+ unsigned : 1;
+ unsigned IVRST : 1;
+ unsigned : 1;
+ unsigned : 1;
+ };
+} __HLVDCONbits_t;
+extern volatile __HLVDCONbits_t __at (0xFD2) HLVDCONbits;
extern __sfr __at (0xFD2) LVDCON;
typedef union {
unsigned LVDEN : 1;
unsigned IRVST : 1;
unsigned : 1;
+ unsigned VDIRMAG : 1;
+ };
+ struct {
+ unsigned LVV0 : 1;
+ unsigned LVV1 : 1;
+ unsigned LVV2 : 1;
+ unsigned LVV3 : 1;
+ unsigned HLVDEN : 1;
+ unsigned BGST : 1;
+ unsigned : 1;
unsigned : 1;
};
-} __LVDCON_t;
-extern volatile __LVDCON_t __at (0xFD2) LVDCONbits;
+ struct {
+ unsigned HLVDL0 : 1;
+ unsigned HLVDL1 : 1;
+ unsigned HLVDL2 : 1;
+ unsigned HLVDL3 : 1;
+ unsigned : 1;
+ unsigned IVRST : 1;
+ unsigned : 1;
+ unsigned : 1;
+ };
+} __LVDCONbits_t;
+extern volatile __LVDCONbits_t __at (0xFD2) LVDCONbits;
extern __sfr __at (0xFD3) OSCCON;
typedef union {
struct {
- unsigned SCS : 2;
- unsigned FLTS : 1;
+ unsigned SCS0 : 1;
+ unsigned SCS1 : 1;
+ unsigned IOFS : 1;
unsigned OSTS : 1;
- unsigned IRCF : 3;
+ unsigned IRCF0 : 1;
+ unsigned IRCF1 : 1;
+ unsigned IRCF2 : 1;
unsigned IDLEN : 1;
};
-} __OSCCON_t;
-extern volatile __OSCCON_t __at (0xFD3) OSCCONbits;
+ struct {
+ unsigned : 1;
+ unsigned : 1;
+ unsigned FLTS : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
+ };
+} __OSCCONbits_t;
+extern volatile __OSCCONbits_t __at (0xFD3) OSCCONbits;
extern __sfr __at (0xFD5) T0CON;
typedef union {
unsigned T08BIT : 1;
unsigned TMR0ON : 1;
};
-} __T0CON_t;
-extern volatile __T0CON_t __at (0xFD5) T0CONbits;
+} __T0CONbits_t;
+extern volatile __T0CONbits_t __at (0xFD5) T0CONbits;
extern __sfr __at (0xFD6) TMR0L;
unsigned : 1;
unsigned : 1;
};
-} __STATUS_t;
-extern volatile __STATUS_t __at (0xFD8) STATUSbits;
+} __STATUSbits_t;
+extern volatile __STATUSbits_t __at (0xFD8) STATUSbits;
extern __sfr __at (0xFD9) FSR2L;
extern __sfr __at (0xFDA) FSR2H;
-typedef union {
- struct {
- unsigned FSR2H : 4;
- unsigned : 1;
- unsigned : 1;
- unsigned : 1;
- unsigned : 1;
- };
-} __FSR2H_t;
-extern volatile __FSR2H_t __at (0xFDA) FSR2Hbits;
extern __sfr __at (0xFDB) PLUSW2;
extern __sfr __at (0xFDF) INDF2;
extern __sfr __at (0xFE0) BSR;
-typedef union {
- struct {
- unsigned BSR : 4;
- unsigned : 1;
- unsigned : 1;
- unsigned : 1;
- unsigned : 1;
- };
-} __BSR_t;
-extern volatile __BSR_t __at (0xFE0) BSRbits;
extern __sfr __at (0xFE1) FSR1L;
extern __sfr __at (0xFE2) FSR1H;
-typedef union {
- struct {
- unsigned FSR1H : 4;
- unsigned : 1;
- unsigned : 1;
- unsigned : 1;
- unsigned : 1;
- };
-} __FSR1H_t;
-extern volatile __FSR1H_t __at (0xFE2) FSR1Hbits;
extern __sfr __at (0xFE3) PLUSW1;
extern __sfr __at (0xFE9) FSR0L;
extern __sfr __at (0xFEA) FSR0H;
-typedef union {
- struct {
- unsigned FSR0H : 4;
- unsigned : 1;
- unsigned : 1;
- unsigned : 1;
- unsigned : 1;
- };
-} __FSR0H_t;
-extern volatile __FSR0H_t __at (0xFEA) FSR0Hbits;
extern __sfr __at (0xFEB) PLUSW0;
extern __sfr __at (0xFF0) INTCON3;
typedef union {
+ struct {
+ unsigned INT1F : 1;
+ unsigned INT2F : 1;
+ unsigned : 1;
+ unsigned INT1E : 1;
+ unsigned INT2E : 1;
+ unsigned : 1;
+ unsigned INT1P : 1;
+ unsigned INT2P : 1;
+ };
struct {
unsigned INT1IF : 1;
unsigned INT2IF : 1;
unsigned INT1IP : 1;
unsigned INT2IP : 1;
};
-} __INTCON3_t;
-extern volatile __INTCON3_t __at (0xFF0) INTCON3bits;
+} __INTCON3bits_t;
+extern volatile __INTCON3bits_t __at (0xFF0) INTCON3bits;
extern __sfr __at (0xFF1) INTCON2;
typedef union {
unsigned INTEDG2 : 1;
unsigned INTEDG1 : 1;
unsigned INTEDG0 : 1;
+ unsigned RBPU : 1;
+ };
+ struct {
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned NOT_RBPU : 1;
};
-} __INTCON2_t;
-extern volatile __INTCON2_t __at (0xFF1) INTCON2bits;
+} __INTCON2bits_t;
+extern volatile __INTCON2bits_t __at (0xFF1) INTCON2bits;
extern __sfr __at (0xFF2) INTCON;
typedef union {
struct {
unsigned RBIF : 1;
- unsigned INT0IF : 1;
+ unsigned INT0F : 1;
unsigned TMR0IF : 1;
unsigned RBIE : 1;
- unsigned INT0IE : 1;
+ unsigned INT0E : 1;
unsigned TMR0IE : 1;
unsigned PEIE : 1;
unsigned GIE : 1;
};
struct {
unsigned : 1;
+ unsigned INT0IF : 1;
+ unsigned T0IF : 1;
unsigned : 1;
- unsigned : 1;
- unsigned : 1;
- unsigned : 1;
- unsigned : 1;
+ unsigned INT0IE : 1;
+ unsigned T0IE : 1;
unsigned GIEL : 1;
unsigned GIEH : 1;
};
-} __INTCON_t;
-extern volatile __INTCON_t __at (0xFF2) INTCONbits;
+} __INTCONbits_t;
+extern volatile __INTCONbits_t __at (0xFF2) INTCONbits;
+
+extern __sfr __at (0xFF3) PROD;
extern __sfr __at (0xFF3) PRODL;
extern __sfr __at (0xFF5) TABLAT;
+extern __sfr __at (0xFF6) TBLPTR;
+
extern __sfr __at (0xFF6) TBLPTRL;
extern __sfr __at (0xFF7) TBLPTRH;
extern __sfr __at (0xFF8) TBLPTRU;
-typedef union {
- struct {
- unsigned TBLPTRU : 5;
- unsigned ACSS : 1;
- unsigned : 1;
- unsigned : 1;
- };
-} __TBLPTRU_t;
-extern volatile __TBLPTRU_t __at (0xFF8) TBLPTRUbits;
+
+extern __sfr __at (0xFF9) PC;
extern __sfr __at (0xFF9) PCL;
extern __sfr __at (0xFFA) PCLATH;
-typedef union {
- struct {
- unsigned PCH : 8;
- };
-} __PCLATH_t;
-extern volatile __PCLATH_t __at (0xFFA) PCLATHbits;
extern __sfr __at (0xFFB) PCLATU;
-typedef union {
- struct {
- unsigned PCU : 5;
- unsigned : 1;
- unsigned : 1;
- unsigned : 1;
- };
-} __PCLATU_t;
-extern volatile __PCLATU_t __at (0xFFB) PCLATUbits;
extern __sfr __at (0xFFC) STKPTR;
typedef union {
struct {
- unsigned STKPTR : 5;
+ unsigned SP0 : 1;
+ unsigned SP1 : 1;
+ unsigned SP2 : 1;
+ unsigned SP3 : 1;
+ unsigned SP4 : 1;
unsigned : 1;
unsigned STKUNF : 1;
unsigned STKFUL : 1;
};
-} __STKPTR_t;
-extern volatile __STKPTR_t __at (0xFFC) STKPTRbits;
+ struct {
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned : 1;
+ unsigned STKOVF : 1;
+ };
+} __STKPTRbits_t;
+extern volatile __STKPTRbits_t __at (0xFFC) STKPTRbits;
+
+extern __sfr __at (0xFFD) TOS;
extern __sfr __at (0xFFD) TOSL;
extern __sfr __at (0xFFE) TOSH;
extern __sfr __at (0xFFF) TOSU;
-typedef union {
- struct {
- unsigned TOSU : 5;
- unsigned : 1;
- unsigned : 1;
- unsigned : 1;
- };
-} __TOSU_t;
-extern volatile __TOSU_t __at (0xFFF) TOSUbits;
-
-/* Configuration register locations */
-#define __CONFIG1H 0x300001
-#define __CONFIG2L 0x300002
-#define __CONFIG2H 0x300003
-#define __CONFIG3H 0x300005
-#define __CONFIG4L 0x300006
-#define __CONFIG5L 0x300008
-#define __CONFIG5H 0x300009
-#define __CONFIG6L 0x30000A
-#define __CONFIG6H 0x30000B
-#define __CONFIG7L 0x30000C
-#define __CONFIG7H 0x30000D
-
-
-/* Oscillator 1H options */
-#define _OSC_11XX_EXT_RC_CLKOUT_ON_RA6_1H 0xFC /* 11XX EXT RC-CLKOUT on RA6 */
-#define _OSC_101X_EXT_RC_CLKOUT_ON_RA6_1H 0xFA /* 101X EXT RC-CLKOUT on RA6 */
-#define _OSC_INT_RC_CLKOUT_ON_RA6_PORT_ON_RA7_1H 0xF9 /* INT RC-CLKOUT on RA6,Port on RA7 */
-#define _OSC_INT_RC_PORT_ON_RA6_PORT_ON_RA7_1H 0xF8 /* INT RC-Port on RA6,Port on RA7 */
-#define _OSC_EXT_RC_PORT_ON_RA6_1H 0xF7 /* EXT RC-Port on RA6 */
-#define _OSC_HS_PLL_ON_FREQ_4XFOSC1_1H 0xF6 /* HS-PLL enabled freq=4xFosc1 */
-#define _OSC_EC_PORT_ON_RA6_1H 0xF5 /* EC-Port on RA6 */
-#define _OSC_EC_CLKOUT_ON_RA6_1H 0xF4 /* EC-CLKOUT on RA6 */
-#define _OSC_0011_EXT_RC_CLKOUT_ON_RA6_1H 0xF3 /* 0011 EXT RC-CLKOUT on RA6 */
-#define _OSC_HS_1H 0xF2 /* HS */
-#define _OSC_XT_1H 0xF1 /* XT */
-#define _OSC_LP_1H 0xF0 /* LP */
-
-/* Fail-Safe Clock Monitor Enable 1H options */
-#define _FCMEN_OFF_1H 0xBF /* Disabled */
-#define _FCMEN_ON_1H 0xFF /* Enabled */
-
-/* Internal External Switch Over Mode 1H options */
-#define _IESO_OFF_1H 0x7F /* Disabled */
-#define _IESO_ON_1H 0xFF /* Enabled */
-
-
-/* Power Up Timer 2L options */
-#define _PUT_OFF_2L 0xFF /* Disabled */
-#define _PUT_ON_2L 0xFE /* Enabled */
-
-/* Brown Out Detect 2L options */
-#define _BODEN_ON_2L 0xFF /* Enabled in hardware, SBOREN disabled */
-#define _BODEN_ON_WHILE_ACTIVE_2L 0xFD /* Enabled while active,disabled in SLEEP,SBOREN disabled */
-#define _BODEN_CONTROLLED_WITH_SBOREN_BIT_2L 0xFB /* Controlled with SBOREN bit */
-#define _BODEN_OFF_2L 0xF9 /* Disabled in hardware, SBOREN disabled */
-
-/* Brown Out Voltage 2L options */
-#define _BODENV_2_0V_2L 0xFF /* 2.0V */
-#define _BODENV_2_7V_2L 0xF7 /* 2.7V */
-#define _BODENV_4_2V_2L 0xEF /* 4.2V */
-#define _BODENV_4_5V_2L 0xE7 /* 4.5V */
-
-
-/* Watchdog Timer 2H options */
-#define _WDT_ON_2H 0xFF /* Enabled */
-#define _WDT_DISABLED_CONTROLLED_2H 0xFE /* Disabled-Controlled by SWDTEN bit */
-
-/* Watchdog Postscaler 2H options */
-#define _WDTPS_1_32768_2H 0xFF /* 1:32768 */
-#define _WDTPS_1_16384_2H 0xFD /* 1:16384 */
-#define _WDTPS_1_8192_2H 0xFB /* 1:8192 */
-#define _WDTPS_1_4096_2H 0xF9 /* 1:4096 */
-#define _WDTPS_1_2048_2H 0xF7 /* 1:2048 */
-#define _WDTPS_1_1024_2H 0xF5 /* 1:1024 */
-#define _WDTPS_1_512_2H 0xF3 /* 1:512 */
-#define _WDTPS_1_256_2H 0xF1 /* 1:256 */
-#define _WDTPS_1_128_2H 0xEF /* 1:128 */
-#define _WDTPS_1_64_2H 0xED /* 1:64 */
-#define _WDTPS_1_32_2H 0xEB /* 1:32 */
-#define _WDTPS_1_16_2H 0xE9 /* 1:16 */
-#define _WDTPS_1_8_2H 0xE7 /* 1:8 */
-#define _WDTPS_1_4_2H 0xE5 /* 1:4 */
-#define _WDTPS_1_2_2H 0xE3 /* 1:2 */
-#define _WDTPS_1_1_2H 0xE1 /* 1:1 */
-
-
-/* CCP2 Mux 3H options */
-#define _CCP2MUX_RC1_3H 0xFF /* RC1 */
-#define _CCP2MUX_RB3_3H 0xFE /* RB3 */
-
-/* PortB A/D Enable 3H options */
-#define _PBADEN_PORTB_4_0__CONFIGURED_AS_ANALOG_INPUTS_ON_RESET_3H 0xFF /* PORTB<4:0> configured as analog inputs on RESET */
-#define _PBADEN_PORTB_4_0__CONFIGURED_AS_DIGITAL_I_O_ON_RESET_3H 0xFD /* PORTB<4:0> configured as digital I/O on RESET */
-
-/* Low Power Timer1 Osc enable 3H options */
-#define _LPT1OSC_ON_3H 0xFF /* Enabled */
-#define _LPT1OSC_OFF_3H 0xFB /* Disabled */
-
-/* Master Clear Enable 3H options */
-#define _MCLRE_MCLR_ON_RE3_OFF_3H 0xFF /* MCLR Enabled,RE3 Disabled */
-#define _MCLRE_MCLR_OFF_RE3_ON_3H 0x7F /* MCLR Disabled,RE3 Enabled */
-
-
-/* Stack Overflow Reset 4L options */
-#define _STVR_ON_4L 0xFF /* Enabled */
-#define _STVR_OFF_4L 0xFE /* Disabled */
-
-/* Low Voltage Program 4L options */
-#define _LVP_ON_4L 0xFF /* Enabled */
-#define _LVP_OFF_4L 0xFB /* Disabled */
-
-/* Extended CPU Enable 4L options */
-#define _ENHCPU_ON_4L 0xFF /* Enabled */
-#define _ENHCPU_OFF_4L 0xBF /* Disabled */
-
-/* Background Debug 4L options */
-#define _BACKBUG_OFF_4L 0xFF /* Disabled */
-#define _BACKBUG_ON_4L 0x7F /* Enabled */
-
-
-/* Code Protect 00800-01FFF 5L options */
-#define _CP_0_OFF_5L 0xFF /* Disabled */
-#define _CP_0_ON_5L 0xFE /* Enabled */
-
-/* Code Protect 02000-03FFF 5L options */
-#define _CP_1_OFF_5L 0xFF /* Disabled */
-#define _CP_1_ON_5L 0xFD /* Enabled */
-
-/* Code Protect 04000-05FFF 5L options */
-#define _CP_2_OFF_5L 0xFF /* Disabled */
-#define _CP_2_ON_5L 0xFB /* Enabled */
-
-/* Code Protect 06000-07FFF 5L options */
-#define _CP_3_OFF_5L 0xFF /* Disabled */
-#define _CP_3_ON_5L 0xF7 /* Enabled */
-
-
-/* Data EEPROM Code Protect 5H options */
-#define _CPD_OFF_5H 0xFF /* Disabled */
-#define _CPD_ON_5H 0x7F /* Enabled */
-
-/* Code Protect Boot 5H options */
-#define _CPB_OFF_5H 0xFF /* Disabled */
-#define _CPB_ON_5H 0xBF /* Enabled */
-
-
-/* Table Write Protect 00800-01FFF 6L options */
-#define _WRT_0_OFF_6L 0xFF /* Disabled */
-#define _WRT_0_ON_6L 0xFE /* Enabled */
-
-/* Table Write Protect 02000-03FFF 6L options */
-#define _WRT_1_OFF_6L 0xFF /* Disabled */
-#define _WRT_1_ON_6L 0xFD /* Enabled */
-
-/* Table Write Protect 04000-05FFF 6L options */
-#define _WRT_2_OFF_6L 0xFF /* Disabled */
-#define _WRT_2_ON_6L 0xFB /* Enabled */
-
-/* Table Write Protect 06000-07FFF 6L options */
-#define _WRT_3_OFF_6L 0xFF /* Disabled */
-#define _WRT_3_ON_6L 0xF7 /* Enabled */
-
-
-/* Data EEPROM Write Protect 6H options */
-#define _WRTD_OFF_6H 0xFF /* Disabled */
-#define _WRTD_ON_6H 0x7F /* Enabled */
-
-/* Table Write Protect Boot 6H options */
-#define _WRTB_OFF_6H 0xFF /* Disabled */
-#define _WRTB_ON_6H 0xBF /* Enabled */
-
-/* Config. Write Protect 6H options */
-#define _WRTC_OFF_6H 0xFF /* Disabled */
-#define _WRTC_ON_6H 0xDF /* Enabled */
-
-
-/* Table Read Protect 00800-01FFF 7L options */
-#define _EBTR_0_OFF_7L 0xFF /* Disabled */
-#define _EBTR_0_ON_7L 0xFE /* Enabled */
-
-/* Table Read Protect 02000-03FFF 7L options */
-#define _EBTR_1_OFF_7L 0xFF /* Disabled */
-#define _EBTR_1_ON_7L 0xFD /* Enabled */
-
-/* Table Read Protect 04000-05FFF 7L options */
-#define _EBTR_2_OFF_7L 0xFF /* Disabled */
-#define _EBTR_2_ON_7L 0xFB /* Enabled */
-
-/* Table Read Protect 06000-07FFF 7L options */
-#define _EBTR_3_OFF_7L 0xFF /* Disabled */
-#define _EBTR_3_ON_7L 0xF7 /* Enabled */
-
-
-/* Table Read Protect Boot 7H options */
-#define _EBTRB_OFF_7H 0xFF /* Disabled */
-#define _EBTRB_ON_7H 0xBF /* Enabled */
-
-/* Location of User ID words */
-#define __IDLOC0 0x200000
-#define __IDLOC1 0x200001
-#define __IDLOC2 0x200002
-#define __IDLOC3 0x200003
-#define __IDLOC4 0x200004
-#define __IDLOC5 0x200005
-#define __IDLOC6 0x200006
-#define __IDLOC7 0x200007
+#endif
-#endif // __PIC18F4520__
-/*
- * pic18f4520.h - PIC18F4520 Device Library Sources
- *
- * This file is part of the GNU PIC Library.
- *
- * May, 2005
- * The GNU PIC Library is maintained by
- * Raphael Neider <rneider AT web.de>
- *
- * originally designed by
- * Vangelis Rokas <vrokas@otenet.gr>
- *
- * $Id$
- *
+/*
+ * pic18f4520.c - device specific definitions
+ *
+ * This file is part of the GNU PIC library for SDCC,
+ * originally devised by Vangelis Rokas <vrokas AT otenet.gr>
+ *
+ * It has been automatically generated by inc2h-pic16.pl,
+ * (c) 2007 by Raphael Neider <rneider AT web.de>
*/
#include <pic18f4520.h>
+
__sfr __at (0xF80) PORTA;
-volatile __PORTA_t __at (0xF80) PORTAbits;
+volatile __PORTAbits_t __at (0xF80) PORTAbits;
__sfr __at (0xF81) PORTB;
-volatile __PORTB_t __at (0xF81) PORTBbits;
+volatile __PORTBbits_t __at (0xF81) PORTBbits;
__sfr __at (0xF82) PORTC;
-volatile __PORTC_t __at (0xF82) PORTCbits;
+volatile __PORTCbits_t __at (0xF82) PORTCbits;
__sfr __at (0xF83) PORTD;
-volatile __PORTD_t __at (0xF83) PORTDbits;
+volatile __PORTDbits_t __at (0xF83) PORTDbits;
__sfr __at (0xF84) PORTE;
-volatile __PORTE_t __at (0xF84) PORTEbits;
+volatile __PORTEbits_t __at (0xF84) PORTEbits;
__sfr __at (0xF89) LATA;
-volatile __LATA_t __at (0xF89) LATAbits;
+volatile __LATAbits_t __at (0xF89) LATAbits;
__sfr __at (0xF8A) LATB;
-volatile __LATB_t __at (0xF8A) LATBbits;
+volatile __LATBbits_t __at (0xF8A) LATBbits;
__sfr __at (0xF8B) LATC;
-volatile __LATC_t __at (0xF8B) LATCbits;
+volatile __LATCbits_t __at (0xF8B) LATCbits;
__sfr __at (0xF8C) LATD;
-volatile __LATD_t __at (0xF8C) LATDbits;
+volatile __LATDbits_t __at (0xF8C) LATDbits;
__sfr __at (0xF8D) LATE;
-volatile __LATE_t __at (0xF8D) LATEbits;
+volatile __LATEbits_t __at (0xF8D) LATEbits;
+
+__sfr __at (0xF92) DDRA;
+volatile __DDRAbits_t __at (0xF92) DDRAbits;
__sfr __at (0xF92) TRISA;
-volatile __TRISA_t __at (0xF92) TRISAbits;
+volatile __TRISAbits_t __at (0xF92) TRISAbits;
+
+__sfr __at (0xF93) DDRB;
+volatile __DDRBbits_t __at (0xF93) DDRBbits;
__sfr __at (0xF93) TRISB;
-volatile __TRISB_t __at (0xF93) TRISBbits;
+volatile __TRISBbits_t __at (0xF93) TRISBbits;
+
+__sfr __at (0xF94) DDRC;
+volatile __DDRCbits_t __at (0xF94) DDRCbits;
__sfr __at (0xF94) TRISC;
-volatile __TRISC_t __at (0xF94) TRISCbits;
+volatile __TRISCbits_t __at (0xF94) TRISCbits;
+
+__sfr __at (0xF95) DDRD;
+volatile __DDRDbits_t __at (0xF95) DDRDbits;
__sfr __at (0xF95) TRISD;
-volatile __TRISD_t __at (0xF95) TRISDbits;
+volatile __TRISDbits_t __at (0xF95) TRISDbits;
+
+__sfr __at (0xF96) DDRE;
+volatile __DDREbits_t __at (0xF96) DDREbits;
__sfr __at (0xF96) TRISE;
-volatile __TRISE_t __at (0xF96) TRISEbits;
+volatile __TRISEbits_t __at (0xF96) TRISEbits;
__sfr __at (0xF9B) OSCTUNE;
-volatile __OSCTUNE_t __at (0xF9B) OSCTUNEbits;
+volatile __OSCTUNEbits_t __at (0xF9B) OSCTUNEbits;
__sfr __at (0xF9D) PIE1;
-volatile __PIE1_t __at (0xF9D) PIE1bits;
+volatile __PIE1bits_t __at (0xF9D) PIE1bits;
__sfr __at (0xF9E) PIR1;
-volatile __PIR1_t __at (0xF9E) PIR1bits;
+volatile __PIR1bits_t __at (0xF9E) PIR1bits;
__sfr __at (0xF9F) IPR1;
-volatile __IPR1_t __at (0xF9F) IPR1bits;
+volatile __IPR1bits_t __at (0xF9F) IPR1bits;
__sfr __at (0xFA0) PIE2;
-volatile __PIE2_t __at (0xFA0) PIE2bits;
+volatile __PIE2bits_t __at (0xFA0) PIE2bits;
__sfr __at (0xFA1) PIR2;
-volatile __PIR2_t __at (0xFA1) PIR2bits;
+volatile __PIR2bits_t __at (0xFA1) PIR2bits;
__sfr __at (0xFA2) IPR2;
-volatile __IPR2_t __at (0xFA2) IPR2bits;
+volatile __IPR2bits_t __at (0xFA2) IPR2bits;
__sfr __at (0xFA6) EECON1;
-volatile __EECON1_t __at (0xFA6) EECON1bits;
+volatile __EECON1bits_t __at (0xFA6) EECON1bits;
__sfr __at (0xFA7) EECON2;
__sfr __at (0xFA9) EEADR;
__sfr __at (0xFAB) RCSTA;
-volatile __RCSTA_t __at (0xFAB) RCSTAbits;
+volatile __RCSTAbits_t __at (0xFAB) RCSTAbits;
__sfr __at (0xFAC) TXSTA;
-volatile __TXSTA_t __at (0xFAC) TXSTAbits;
+volatile __TXSTAbits_t __at (0xFAC) TXSTAbits;
__sfr __at (0xFAD) TXREG;
__sfr __at (0xFB0) SPBRGH;
__sfr __at (0xFB1) T3CON;
-volatile __T3CON_t __at (0xFB1) T3CONbits;
+volatile __T3CONbits_t __at (0xFB1) T3CONbits;
__sfr __at (0xFB2) TMR3L;
__sfr __at (0xFB3) TMR3H;
__sfr __at (0xFB4) CMCON;
-volatile __CMCON_t __at (0xFB4) CMCONbits;
+volatile __CMCONbits_t __at (0xFB4) CMCONbits;
__sfr __at (0xFB5) CVRCON;
-volatile __CVRCON_t __at (0xFB5) CVRCONbits;
+volatile __CVRCONbits_t __at (0xFB5) CVRCONbits;
-__sfr __at (0xFB6) ECCPAS1;
-volatile __ECCPAS1_t __at (0xFB6) ECCPAS1bits;
+__sfr __at (0xFB6) ECCP1AS;
+volatile __ECCP1ASbits_t __at (0xFB6) ECCP1ASbits;
__sfr __at (0xFB7) PWM1CON;
-volatile __PWM1CON_t __at (0xFB7) PWM1CONbits;
+volatile __PWM1CONbits_t __at (0xFB7) PWM1CONbits;
__sfr __at (0xFB8) BAUDCON;
-volatile __BAUDCON_t __at (0xFB8) BAUDCONbits;
+volatile __BAUDCONbits_t __at (0xFB8) BAUDCONbits;
+
+__sfr __at (0xFB8) BAUDCTL;
+volatile __BAUDCTLbits_t __at (0xFB8) BAUDCTLbits;
__sfr __at (0xFBA) CCP2CON;
-volatile __CCP2CON_t __at (0xFBA) CCP2CONbits;
+volatile __CCP2CONbits_t __at (0xFBA) CCP2CONbits;
+
+__sfr __at (0xFBB) CCPR2;
__sfr __at (0xFBB) CCPR2L;
__sfr __at (0xFBC) CCPR2H;
-__sfr __at (0xFBD) ECCP1CON;
-volatile __ECCP1CON_t __at (0xFBD) ECCP1CONbits;
+__sfr __at (0xFBD) CCP1CON;
+volatile __CCP1CONbits_t __at (0xFBD) CCP1CONbits;
+
+__sfr __at (0xFBE) CCPR1;
__sfr __at (0xFBE) CCPR1L;
__sfr __at (0xFBF) CCPR1H;
__sfr __at (0xFC0) ADCON2;
-volatile __ADCON2_t __at (0xFC0) ADCON2bits;
+volatile __ADCON2bits_t __at (0xFC0) ADCON2bits;
__sfr __at (0xFC1) ADCON1;
-volatile __ADCON1_t __at (0xFC1) ADCON1bits;
+volatile __ADCON1bits_t __at (0xFC1) ADCON1bits;
__sfr __at (0xFC2) ADCON0;
-volatile __ADCON0_t __at (0xFC2) ADCON0bits;
+volatile __ADCON0bits_t __at (0xFC2) ADCON0bits;
+
+__sfr __at (0xFC3) ADRES;
__sfr __at (0xFC3) ADRESL;
__sfr __at (0xFC4) ADRESH;
__sfr __at (0xFC5) SSPCON2;
-volatile __SSPCON2_t __at (0xFC5) SSPCON2bits;
+volatile __SSPCON2bits_t __at (0xFC5) SSPCON2bits;
__sfr __at (0xFC6) SSPCON1;
-volatile __SSPCON1_t __at (0xFC6) SSPCON1bits;
+volatile __SSPCON1bits_t __at (0xFC6) SSPCON1bits;
__sfr __at (0xFC7) SSPSTAT;
-volatile __SSPSTAT_t __at (0xFC7) SSPSTATbits;
+volatile __SSPSTATbits_t __at (0xFC7) SSPSTATbits;
__sfr __at (0xFC8) SSPADD;
__sfr __at (0xFC9) SSPBUF;
__sfr __at (0xFCA) T2CON;
-volatile __T2CON_t __at (0xFCA) T2CONbits;
+volatile __T2CONbits_t __at (0xFCA) T2CONbits;
__sfr __at (0xFCB) PR2;
__sfr __at (0xFCC) TMR2;
__sfr __at (0xFCD) T1CON;
-volatile __T1CON_t __at (0xFCD) T1CONbits;
+volatile __T1CONbits_t __at (0xFCD) T1CONbits;
__sfr __at (0xFCE) TMR1L;
__sfr __at (0xFCF) TMR1H;
__sfr __at (0xFD0) RCON;
-volatile __RCON_t __at (0xFD0) RCONbits;
+volatile __RCONbits_t __at (0xFD0) RCONbits;
__sfr __at (0xFD1) WDTCON;
-volatile __WDTCON_t __at (0xFD1) WDTCONbits;
+volatile __WDTCONbits_t __at (0xFD1) WDTCONbits;
+
+__sfr __at (0xFD2) HLVDCON;
+volatile __HLVDCONbits_t __at (0xFD2) HLVDCONbits;
__sfr __at (0xFD2) LVDCON;
-volatile __LVDCON_t __at (0xFD2) LVDCONbits;
+volatile __LVDCONbits_t __at (0xFD2) LVDCONbits;
__sfr __at (0xFD3) OSCCON;
-volatile __OSCCON_t __at (0xFD3) OSCCONbits;
+volatile __OSCCONbits_t __at (0xFD3) OSCCONbits;
__sfr __at (0xFD5) T0CON;
-volatile __T0CON_t __at (0xFD5) T0CONbits;
+volatile __T0CONbits_t __at (0xFD5) T0CONbits;
__sfr __at (0xFD6) TMR0L;
__sfr __at (0xFD7) TMR0H;
__sfr __at (0xFD8) STATUS;
-volatile __STATUS_t __at (0xFD8) STATUSbits;
+volatile __STATUSbits_t __at (0xFD8) STATUSbits;
__sfr __at (0xFD9) FSR2L;
__sfr __at (0xFDA) FSR2H;
-volatile __FSR2H_t __at (0xFDA) FSR2Hbits;
__sfr __at (0xFDB) PLUSW2;
__sfr __at (0xFDF) INDF2;
__sfr __at (0xFE0) BSR;
-volatile __BSR_t __at (0xFE0) BSRbits;
__sfr __at (0xFE1) FSR1L;
__sfr __at (0xFE2) FSR1H;
-volatile __FSR1H_t __at (0xFE2) FSR1Hbits;
__sfr __at (0xFE3) PLUSW1;
__sfr __at (0xFE9) FSR0L;
__sfr __at (0xFEA) FSR0H;
-volatile __FSR0H_t __at (0xFEA) FSR0Hbits;
__sfr __at (0xFEB) PLUSW0;
__sfr __at (0xFEF) INDF0;
__sfr __at (0xFF0) INTCON3;
-volatile __INTCON3_t __at (0xFF0) INTCON3bits;
+volatile __INTCON3bits_t __at (0xFF0) INTCON3bits;
__sfr __at (0xFF1) INTCON2;
-volatile __INTCON2_t __at (0xFF1) INTCON2bits;
+volatile __INTCON2bits_t __at (0xFF1) INTCON2bits;
__sfr __at (0xFF2) INTCON;
-volatile __INTCON_t __at (0xFF2) INTCONbits;
+volatile __INTCONbits_t __at (0xFF2) INTCONbits;
+
+__sfr __at (0xFF3) PROD;
__sfr __at (0xFF3) PRODL;
__sfr __at (0xFF5) TABLAT;
+__sfr __at (0xFF6) TBLPTR;
+
__sfr __at (0xFF6) TBLPTRL;
__sfr __at (0xFF7) TBLPTRH;
__sfr __at (0xFF8) TBLPTRU;
-volatile __TBLPTRU_t __at (0xFF8) TBLPTRUbits;
+
+__sfr __at (0xFF9) PC;
__sfr __at (0xFF9) PCL;
__sfr __at (0xFFA) PCLATH;
-volatile __PCLATH_t __at (0xFFA) PCLATHbits;
__sfr __at (0xFFB) PCLATU;
-volatile __PCLATU_t __at (0xFFB) PCLATUbits;
__sfr __at (0xFFC) STKPTR;
-volatile __STKPTR_t __at (0xFFC) STKPTRbits;
+volatile __STKPTRbits_t __at (0xFFC) STKPTRbits;
+
+__sfr __at (0xFFD) TOS;
__sfr __at (0xFFD) TOSL;
__sfr __at (0xFFE) TOSH;
__sfr __at (0xFFF) TOSU;
-volatile __TOSU_t __at (0xFFF) TOSUbits;
+
{ 0, 0 }, { 0, 0 }, { 0, 0 } }
}
},
+ {
+ {"p18f2420", "18f2420", "pic18f2420", "f2420"}, // also: 18f[24][45]20
+ 0,
+ 0x300, /* 768 */
+ 0x80,
+ 0,
+ { 0xf80, 0xfff }, /* PIC18F2420 range of SFR's */
+ {
+ /* PIC18F2420 configuration words */
+ 0x300000,
+ 0x30000d,
+ { { 0x3f, 0, 0xff } /* 0 */ , { 0xcf, 0, 0xff } /* 1 */ , { 0x1f, 0, 0xff } /* 2 */ ,
+ { 0x1f, 0, 0xff } /* 3 */ , { -1, 0, 0xff } /* 4 */ , { 0x87, 0, 0xff } /* 5 */ ,
+ { 0xc5, 0, 0xff } /* 6 */ , { -1, 0, 0xff } /* 7 */ , { 0x0f, 0, 0xff } /* 8 */ ,
+ { 0xc0, 0, 0xff } /* 9 */ , { 0x0f, 0, 0xff } /* a */ , { 0xe0, 0, 0xff } /* b */ ,
+ { 0x0f, 0, 0xff } /* c */ , { 0x40, 0, 0xff } /* d */ }
+ },
+ { 0x200000, 0x200007,
+ { { 0, 0 }, { 0, 0 }, { 0, 0 }, { 0, 0 }, { 0, 0 },
+ { 0, 0 }, { 0, 0 }, { 0, 0 } }
+ }
+ },
{
{"p18f2431", "18f2431", "pic18f2431", "f2431"}, // also: 18f[24][34]31
0, /* always 0 */
{ 0, 0 }, { 0, 0 }, { 0, 0 } }
}
},
+ {
+ {"p18f2520", "18f2520", "pic18f2520", "f2520"}, // also: 18f[24][45]20
+ 0,
+ 0x600, /* 1536 */
+ 0x80,
+ 0,
+ { 0xf80, 0xfff }, /* PIC18F2520 range of SFR's */
+ {
+ /* PIC18F2520 configuration words */
+ 0x300000,
+ 0x30000d,
+ { { 0x3f, 0, 0xff } /* 0 */ , { 0xcf, 0, 0xff } /* 1 */ , { 0x1f, 0, 0xff } /* 2 */ ,
+ { 0x1f, 0, 0xff } /* 3 */ , { -1, 0, 0xff } /* 4 */ , { 0x87, 0, 0xff } /* 5 */ ,
+ { 0xc5, 0, 0xff } /* 6 */ , { -1, 0, 0xff } /* 7 */ , { 0x0f, 0, 0xff } /* 8 */ ,
+ { 0xc0, 0, 0xff } /* 9 */ , { 0x0f, 0, 0xff } /* a */ , { 0xe0, 0, 0xff } /* b */ ,
+ { 0x0f, 0, 0xff } /* c */ , { 0x40, 0, 0xff } /* d */ }
+ },
+ { 0x200000, 0x200007,
+ { { 0, 0 }, { 0, 0 }, { 0, 0 }, { 0, 0 }, { 0, 0 },
+ { 0, 0 }, { 0, 0 }, { 0, 0 } }
+ }
+ },
{
{"p18f2525", "18f2525", "pic18f2525", "f2525"},
0,
{ 0, 0 }, { 0, 0 }, { 0, 0 } }
}
},
+ {
+ {"p18f4420", "18f4420", "pic18f4420", "f4420"}, // also: 18f[24][45]20
+ 0,
+ 0x300, /* 4096 */
+ 0x80,
+ 0,
+ { 0xf80, 0xfff }, /* PIC18F4420 range of SFR's */
+ {
+ /* PIC18F4420 configuration words */
+ 0x300000,
+ 0x30000d,
+ { { 0x3f, 0, 0xff } /* 0 */ , { 0xcf, 0, 0xff } /* 1 */ , { 0x1f, 0, 0xff } /* 2 */ ,
+ { 0x1f, 0, 0xff } /* 3 */ , { -1, 0, 0xff } /* 4 */ , { 0x87, 0, 0xff } /* 5 */ ,
+ { 0xc5, 0, 0xff } /* 6 */ , { -1, 0, 0xff } /* 7 */ , { 0x0f, 0, 0xff } /* 8 */ ,
+ { 0xc0, 0, 0xff } /* 9 */ , { 0x0f, 0, 0xff } /* a */ , { 0xe0, 0, 0xff } /* b */ ,
+ { 0x0f, 0, 0xff } /* c */ , { 0x40, 0, 0xff } /* d */ }
+ },
+ { 0x200000, 0x200007,
+ { { 0, 0 }, { 0, 0 }, { 0, 0 }, { 0, 0 }, { 0, 0 },
+ { 0, 0 }, { 0, 0 }, { 0, 0 } }
+ }
+ },
{
{"p18f4431", "18f4431", "pic18f4431", "f4431"}, // also: 18f[24][34]31
0, /* always 0 */
{
{"p18f4520", "18f4520", "pic18f4520", "f4520"},
0,
- 0x1000, /* 4096 */
+ 0x600, /* 1536 */
0x80,
0,
{ 0xf80, 0xfff }, /* PIC18F4520 range of SFR's */
projects / fw / sdcc / commitdiff