2 // Register Declarations for Microchip 16F874A Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PORTD_ADDR 0x0008
37 #define PORTE_ADDR 0x0009
38 #define PCLATH_ADDR 0x000A
39 #define INTCON_ADDR 0x000B
40 #define PIR1_ADDR 0x000C
41 #define PIR2_ADDR 0x000D
42 #define TMR1L_ADDR 0x000E
43 #define TMR1H_ADDR 0x000F
44 #define T1CON_ADDR 0x0010
45 #define TMR2_ADDR 0x0011
46 #define T2CON_ADDR 0x0012
47 #define SSPBUF_ADDR 0x0013
48 #define SSPCON_ADDR 0x0014
49 #define CCPR1L_ADDR 0x0015
50 #define CCPR1H_ADDR 0x0016
51 #define CCP1CON_ADDR 0x0017
52 #define RCSTA_ADDR 0x0018
53 #define TXREG_ADDR 0x0019
54 #define RCREG_ADDR 0x001A
55 #define CCPR2L_ADDR 0x001B
56 #define CCPR2H_ADDR 0x001C
57 #define CCP2CON_ADDR 0x001D
58 #define ADRESH_ADDR 0x001E
59 #define ADCON0_ADDR 0x001F
60 #define OPTION_REG_ADDR 0x0081
61 #define TRISA_ADDR 0x0085
62 #define TRISB_ADDR 0x0086
63 #define TRISC_ADDR 0x0087
64 #define TRISD_ADDR 0x0088
65 #define TRISE_ADDR 0x0089
66 #define PIE1_ADDR 0x008C
67 #define PIE2_ADDR 0x008D
68 #define PCON_ADDR 0x008E
69 #define SSPCON2_ADDR 0x0091
70 #define PR2_ADDR 0x0092
71 #define SSPADD_ADDR 0x0093
72 #define SSPSTAT_ADDR 0x0094
73 #define TXSTA_ADDR 0x0098
74 #define SPBRG_ADDR 0x0099
75 #define CMCON_ADDR 0x009C
76 #define CVRCON_ADDR 0x009D
77 #define ADRESL_ADDR 0x009E
78 #define ADCON1_ADDR 0x009F
79 #define EEDATA_ADDR 0x010C
80 #define EEADR_ADDR 0x010D
81 #define EEDATH_ADDR 0x010E
82 #define EEADRH_ADDR 0x010F
83 #define EECON1_ADDR 0x018C
84 #define EECON2_ADDR 0x018D
87 // Memory organization.
93 // P16F874A.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
96 // This header file defines configurations, registers, and other useful bits of
97 // information for the PIC16F877A microcontroller. These names are taken to match
98 // the data sheets as closely as possible.
100 // Note that the processor must be selected before this file is
101 // included. The processor may be selected the following ways:
103 // 1. Command line switch:
104 // C:\ MPASM MYFILE.ASM /PIC16F874A
105 // 2. LIST directive in the source file
107 // 3. Processor Type entry in the MPASM full-screen interface
109 //==========================================================================
113 //==========================================================================
116 //1.03 11/17/05 Added the INTCON bits TMR0IE and TMR0IF and the ADCON1 bit ADCS2.
117 //1.02 05/28/02 Corrected values for _CP_ALL and _CP_OFF in Configuration Bits section.
118 //1.01 10/03/01 Added the PIR2 bit CMIF and the PIE2 bit CMIE
119 //1.00 04/19/01 Initial Release (BD - generated from PIC16F877A.inc)
121 //==========================================================================
125 //==========================================================================
128 // MESSG "Processor-header file mismatch. Verify selected processor."
131 //==========================================================================
133 // Register Definitions
135 //==========================================================================
140 //----- Register Files------------------------------------------------------
142 extern __sfr __at (INDF_ADDR) INDF;
143 extern __sfr __at (TMR0_ADDR) TMR0;
144 extern __sfr __at (PCL_ADDR) PCL;
145 extern __sfr __at (STATUS_ADDR) STATUS;
146 extern __sfr __at (FSR_ADDR) FSR;
147 extern __sfr __at (PORTA_ADDR) PORTA;
148 extern __sfr __at (PORTB_ADDR) PORTB;
149 extern __sfr __at (PORTC_ADDR) PORTC;
150 extern __sfr __at (PORTD_ADDR) PORTD;
151 extern __sfr __at (PORTE_ADDR) PORTE;
152 extern __sfr __at (PCLATH_ADDR) PCLATH;
153 extern __sfr __at (INTCON_ADDR) INTCON;
154 extern __sfr __at (PIR1_ADDR) PIR1;
155 extern __sfr __at (PIR2_ADDR) PIR2;
156 extern __sfr __at (TMR1L_ADDR) TMR1L;
157 extern __sfr __at (TMR1H_ADDR) TMR1H;
158 extern __sfr __at (T1CON_ADDR) T1CON;
159 extern __sfr __at (TMR2_ADDR) TMR2;
160 extern __sfr __at (T2CON_ADDR) T2CON;
161 extern __sfr __at (SSPBUF_ADDR) SSPBUF;
162 extern __sfr __at (SSPCON_ADDR) SSPCON;
163 extern __sfr __at (CCPR1L_ADDR) CCPR1L;
164 extern __sfr __at (CCPR1H_ADDR) CCPR1H;
165 extern __sfr __at (CCP1CON_ADDR) CCP1CON;
166 extern __sfr __at (RCSTA_ADDR) RCSTA;
167 extern __sfr __at (TXREG_ADDR) TXREG;
168 extern __sfr __at (RCREG_ADDR) RCREG;
169 extern __sfr __at (CCPR2L_ADDR) CCPR2L;
170 extern __sfr __at (CCPR2H_ADDR) CCPR2H;
171 extern __sfr __at (CCP2CON_ADDR) CCP2CON;
172 extern __sfr __at (ADRESH_ADDR) ADRESH;
173 extern __sfr __at (ADCON0_ADDR) ADCON0;
175 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
176 extern __sfr __at (TRISA_ADDR) TRISA;
177 extern __sfr __at (TRISB_ADDR) TRISB;
178 extern __sfr __at (TRISC_ADDR) TRISC;
179 extern __sfr __at (TRISD_ADDR) TRISD;
180 extern __sfr __at (TRISE_ADDR) TRISE;
181 extern __sfr __at (PIE1_ADDR) PIE1;
182 extern __sfr __at (PIE2_ADDR) PIE2;
183 extern __sfr __at (PCON_ADDR) PCON;
184 extern __sfr __at (SSPCON2_ADDR) SSPCON2;
185 extern __sfr __at (PR2_ADDR) PR2;
186 extern __sfr __at (SSPADD_ADDR) SSPADD;
187 extern __sfr __at (SSPSTAT_ADDR) SSPSTAT;
188 extern __sfr __at (TXSTA_ADDR) TXSTA;
189 extern __sfr __at (SPBRG_ADDR) SPBRG;
190 extern __sfr __at (CMCON_ADDR) CMCON;
191 extern __sfr __at (CVRCON_ADDR) CVRCON;
192 extern __sfr __at (ADRESL_ADDR) ADRESL;
193 extern __sfr __at (ADCON1_ADDR) ADCON1;
195 extern __sfr __at (EEDATA_ADDR) EEDATA;
196 extern __sfr __at (EEADR_ADDR) EEADR;
197 extern __sfr __at (EEDATH_ADDR) EEDATH;
198 extern __sfr __at (EEADRH_ADDR) EEADRH;
200 extern __sfr __at (EECON1_ADDR) EECON1;
201 extern __sfr __at (EECON2_ADDR) EECON2;
203 //----- STATUS Bits --------------------------------------------------------
206 //----- INTCON Bits --------------------------------------------------------
209 //----- PIR1 Bits ----------------------------------------------------------
212 //----- PIR2 Bits ----------------------------------------------------------
215 //----- T1CON Bits ---------------------------------------------------------
218 //----- T2CON Bits ---------------------------------------------------------
221 //----- SSPCON Bits --------------------------------------------------------
224 //----- CCP1CON Bits -------------------------------------------------------
227 //----- RCSTA Bits ---------------------------------------------------------
230 //----- CCP2CON Bits -------------------------------------------------------
233 //----- ADCON0 Bits --------------------------------------------------------
236 //----- OPTION_REG Bits -----------------------------------------------------
239 //----- TRISE Bits ---------------------------------------------------------
242 //----- PIE1 Bits ----------------------------------------------------------
245 //----- PIE2 Bits ----------------------------------------------------------
248 //----- PCON Bits ----------------------------------------------------------
251 //----- SSPCON2 Bits --------------------------------------------------------
254 //----- SSPSTAT Bits -------------------------------------------------------
257 //----- TXSTA Bits ---------------------------------------------------------
261 //----- CMCON Bits ---------------------------------------------------------
263 //----- CVRCON Bits --------------------------------------------------------
265 //----- ADCON1 Bits --------------------------------------------------------
268 //----- EECON1 Bits --------------------------------------------------------
271 //==========================================================================
275 //==========================================================================
278 // __BADRAM H'8F'-H'90', H'95'-H'97', H'9A'-H'9B'
279 // __BADRAM H'105', H'107'-H'109', H'110'-H'11F'
280 // __BADRAM H'185', H'187'-H'189', H'18E'-H'19F'
282 //==========================================================================
284 // Configuration Bits
286 //==========================================================================
288 #define _CP_ALL 0x1FFF
289 #define _CP_OFF 0x3FFF
290 #define _DEBUG_OFF 0x3FFF
291 #define _DEBUG_ON 0x37FF
292 #define _WRT_OFF 0x3FFF // No prog memmory write protection
293 #define _WRT_256 0x3DFF // First 256 prog memmory write protected
294 #define _WRT_1FOURTH 0x3BFF // First quarter prog memmory write protected
295 #define _WRT_HALF 0x39FF // First half memmory write protected
296 #define _CPD_OFF 0x3FFF
297 #define _CPD_ON 0x3EFF
298 #define _LVP_ON 0x3FFF
299 #define _LVP_OFF 0x3F7F
300 #define _BODEN_ON 0x3FFF
301 #define _BODEN_OFF 0x3FBF
302 #define _PWRTE_OFF 0x3FFF
303 #define _PWRTE_ON 0x3FF7
304 #define _WDT_ON 0x3FFF
305 #define _WDT_OFF 0x3FFB
306 #define _RC_OSC 0x3FFF
307 #define _HS_OSC 0x3FFE
308 #define _XT_OSC 0x3FFD
309 #define _LP_OSC 0x3FFC
313 // ----- ADCON0 bits --------------------
316 unsigned char ADON:1;
319 unsigned char CHS0:1;
320 unsigned char CHS1:1;
321 unsigned char CHS2:1;
322 unsigned char ADCS0:1;
323 unsigned char ADCS1:1;
328 unsigned char NOT_DONE:1;
338 unsigned char GO_DONE:1;
346 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
348 #define ADON ADCON0_bits.ADON
349 #define GO ADCON0_bits.GO
350 #define NOT_DONE ADCON0_bits.NOT_DONE
351 #define GO_DONE ADCON0_bits.GO_DONE
352 #define CHS0 ADCON0_bits.CHS0
353 #define CHS1 ADCON0_bits.CHS1
354 #define CHS2 ADCON0_bits.CHS2
355 #define ADCS0 ADCON0_bits.ADCS0
356 #define ADCS1 ADCON0_bits.ADCS1
358 // ----- ADCON1 bits --------------------
361 unsigned char PCFG0:1;
362 unsigned char PCFG1:1;
363 unsigned char PCFG2:1;
364 unsigned char PCFG3:1;
367 unsigned char ADCS2:1;
368 unsigned char ADFM:1;
371 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
373 #define PCFG0 ADCON1_bits.PCFG0
374 #define PCFG1 ADCON1_bits.PCFG1
375 #define PCFG2 ADCON1_bits.PCFG2
376 #define PCFG3 ADCON1_bits.PCFG3
377 #define ADCS2 ADCON1_bits.ADCS2
378 #define ADFM ADCON1_bits.ADFM
380 // ----- CCP1CON bits --------------------
383 unsigned char CCP1M0:1;
384 unsigned char CCP1M1:1;
385 unsigned char CCP1M2:1;
386 unsigned char CCP1M3:1;
387 unsigned char CCP1Y:1;
388 unsigned char CCP1X:1;
393 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
395 #define CCP1M0 CCP1CON_bits.CCP1M0
396 #define CCP1M1 CCP1CON_bits.CCP1M1
397 #define CCP1M2 CCP1CON_bits.CCP1M2
398 #define CCP1M3 CCP1CON_bits.CCP1M3
399 #define CCP1Y CCP1CON_bits.CCP1Y
400 #define CCP1X CCP1CON_bits.CCP1X
402 // ----- CCP2CON bits --------------------
405 unsigned char CCP2M0:1;
406 unsigned char CCP2M1:1;
407 unsigned char CCP2M2:1;
408 unsigned char CCP2M3:1;
409 unsigned char CCP2Y:1;
410 unsigned char CCP2X:1;
415 extern volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits;
417 #define CCP2M0 CCP2CON_bits.CCP2M0
418 #define CCP2M1 CCP2CON_bits.CCP2M1
419 #define CCP2M2 CCP2CON_bits.CCP2M2
420 #define CCP2M3 CCP2CON_bits.CCP2M3
421 #define CCP2Y CCP2CON_bits.CCP2Y
422 #define CCP2X CCP2CON_bits.CCP2X
424 // ----- CMCON bits --------------------
431 unsigned char C1INV:1;
432 unsigned char C2INV:1;
433 unsigned char C1OUT:1;
434 unsigned char C2OUT:1;
437 extern volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits;
439 #define CM0 CMCON_bits.CM0
440 #define CM1 CMCON_bits.CM1
441 #define CM2 CMCON_bits.CM2
442 #define CIS CMCON_bits.CIS
443 #define C1INV CMCON_bits.C1INV
444 #define C2INV CMCON_bits.C2INV
445 #define C1OUT CMCON_bits.C1OUT
446 #define C2OUT CMCON_bits.C2OUT
448 // ----- CVRCON bits --------------------
451 unsigned char CVR0:1;
452 unsigned char CVR1:1;
453 unsigned char CVR2:1;
454 unsigned char CVR3:1;
456 unsigned char CVRR:1;
457 unsigned char CVROE:1;
458 unsigned char CVREN:1;
461 extern volatile __CVRCON_bits_t __at(CVRCON_ADDR) CVRCON_bits;
463 #define CVR0 CVRCON_bits.CVR0
464 #define CVR1 CVRCON_bits.CVR1
465 #define CVR2 CVRCON_bits.CVR2
466 #define CVR3 CVRCON_bits.CVR3
467 #define CVRR CVRCON_bits.CVRR
468 #define CVROE CVRCON_bits.CVROE
469 #define CVREN CVRCON_bits.CVREN
471 // ----- EECON1 bits --------------------
476 unsigned char WREN:1;
477 unsigned char WRERR:1;
481 unsigned char EEPGD:1;
484 extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits;
486 #define RD EECON1_bits.RD
487 #define WR EECON1_bits.WR
488 #define WREN EECON1_bits.WREN
489 #define WRERR EECON1_bits.WRERR
490 #define EEPGD EECON1_bits.EEPGD
492 // ----- INTCON bits --------------------
495 unsigned char RBIF:1;
496 unsigned char INTF:1;
497 unsigned char T0IF:1;
498 unsigned char RBIE:1;
499 unsigned char INTE:1;
500 unsigned char T0IE:1;
501 unsigned char PEIE:1;
507 unsigned char TMR0IF:1;
510 unsigned char TMR0IE:1;
515 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
517 #define RBIF INTCON_bits.RBIF
518 #define INTF INTCON_bits.INTF
519 #define T0IF INTCON_bits.T0IF
520 #define TMR0IF INTCON_bits.TMR0IF
521 #define RBIE INTCON_bits.RBIE
522 #define INTE INTCON_bits.INTE
523 #define T0IE INTCON_bits.T0IE
524 #define TMR0IE INTCON_bits.TMR0IE
525 #define PEIE INTCON_bits.PEIE
526 #define GIE INTCON_bits.GIE
528 // ----- OPTION_REG bits --------------------
535 unsigned char T0SE:1;
536 unsigned char T0CS:1;
537 unsigned char INTEDG:1;
538 unsigned char NOT_RBPU:1;
540 } __OPTION_REG_bits_t;
541 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
543 #define PS0 OPTION_REG_bits.PS0
544 #define PS1 OPTION_REG_bits.PS1
545 #define PS2 OPTION_REG_bits.PS2
546 #define PSA OPTION_REG_bits.PSA
547 #define T0SE OPTION_REG_bits.T0SE
548 #define T0CS OPTION_REG_bits.T0CS
549 #define INTEDG OPTION_REG_bits.INTEDG
550 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
552 // ----- PCON bits --------------------
555 unsigned char NOT_BO:1;
556 unsigned char NOT_POR:1;
565 unsigned char NOT_BOR:1;
575 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
577 #define NOT_BO PCON_bits.NOT_BO
578 #define NOT_BOR PCON_bits.NOT_BOR
579 #define NOT_POR PCON_bits.NOT_POR
581 // ----- PIE1 bits --------------------
584 unsigned char TMR1IE:1;
585 unsigned char TMR2IE:1;
586 unsigned char CCP1IE:1;
587 unsigned char SSPIE:1;
588 unsigned char TXIE:1;
589 unsigned char RCIE:1;
590 unsigned char ADIE:1;
591 unsigned char PSPIE:1;
594 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
596 #define TMR1IE PIE1_bits.TMR1IE
597 #define TMR2IE PIE1_bits.TMR2IE
598 #define CCP1IE PIE1_bits.CCP1IE
599 #define SSPIE PIE1_bits.SSPIE
600 #define TXIE PIE1_bits.TXIE
601 #define RCIE PIE1_bits.RCIE
602 #define ADIE PIE1_bits.ADIE
603 #define PSPIE PIE1_bits.PSPIE
605 // ----- PIE2 bits --------------------
608 unsigned char CCP2IE:1;
611 unsigned char BCLIE:1;
612 unsigned char EEIE:1;
614 unsigned char CMIE:1;
618 extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits;
620 #define CCP2IE PIE2_bits.CCP2IE
621 #define BCLIE PIE2_bits.BCLIE
622 #define EEIE PIE2_bits.EEIE
623 #define CMIE PIE2_bits.CMIE
625 // ----- PIR1 bits --------------------
628 unsigned char TMR1IF:1;
629 unsigned char TMR2IF:1;
630 unsigned char CCP1IF:1;
631 unsigned char SSPIF:1;
632 unsigned char TXIF:1;
633 unsigned char RCIF:1;
634 unsigned char ADIF:1;
635 unsigned char PSPIF:1;
638 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
640 #define TMR1IF PIR1_bits.TMR1IF
641 #define TMR2IF PIR1_bits.TMR2IF
642 #define CCP1IF PIR1_bits.CCP1IF
643 #define SSPIF PIR1_bits.SSPIF
644 #define TXIF PIR1_bits.TXIF
645 #define RCIF PIR1_bits.RCIF
646 #define ADIF PIR1_bits.ADIF
647 #define PSPIF PIR1_bits.PSPIF
649 // ----- PIR2 bits --------------------
652 unsigned char CCP2IF:1;
655 unsigned char BCLIF:1;
656 unsigned char EEIF:1;
658 unsigned char CMIF:1;
662 extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits;
664 #define CCP2IF PIR2_bits.CCP2IF
665 #define BCLIF PIR2_bits.BCLIF
666 #define EEIF PIR2_bits.EEIF
667 #define CMIF PIR2_bits.CMIF
669 // ----- PORTA bits --------------------
682 extern volatile __PORTA_bits_t __at(PORTA_ADDR) PORTA_bits;
684 #define RA0 PORTA_bits.RA0
685 #define RA1 PORTA_bits.RA1
686 #define RA2 PORTA_bits.RA2
687 #define RA3 PORTA_bits.RA3
688 #define RA4 PORTA_bits.RA4
689 #define RA5 PORTA_bits.RA5
691 // ----- PORTB bits --------------------
704 extern volatile __PORTB_bits_t __at(PORTB_ADDR) PORTB_bits;
706 #define RB0 PORTB_bits.RB0
707 #define RB1 PORTB_bits.RB1
708 #define RB2 PORTB_bits.RB2
709 #define RB3 PORTB_bits.RB3
710 #define RB4 PORTB_bits.RB4
711 #define RB5 PORTB_bits.RB5
712 #define RB6 PORTB_bits.RB6
713 #define RB7 PORTB_bits.RB7
715 // ----- PORTC bits --------------------
728 extern volatile __PORTC_bits_t __at(PORTC_ADDR) PORTC_bits;
730 #define RC0 PORTC_bits.RC0
731 #define RC1 PORTC_bits.RC1
732 #define RC2 PORTC_bits.RC2
733 #define RC3 PORTC_bits.RC3
734 #define RC4 PORTC_bits.RC4
735 #define RC5 PORTC_bits.RC5
736 #define RC6 PORTC_bits.RC6
737 #define RC7 PORTC_bits.RC7
739 // ----- PORTD bits --------------------
752 extern volatile __PORTD_bits_t __at(PORTD_ADDR) PORTD_bits;
754 #define RD0 PORTD_bits.RD0
755 #define RD1 PORTD_bits.RD1
756 #define RD2 PORTD_bits.RD2
757 #define RD3 PORTD_bits.RD3
758 #define RD4 PORTD_bits.RD4
759 #define RD5 PORTD_bits.RD5
760 #define RD6 PORTD_bits.RD6
761 #define RD7 PORTD_bits.RD7
763 // ----- PORTE bits --------------------
776 extern volatile __PORTE_bits_t __at(PORTE_ADDR) PORTE_bits;
778 #define RE0 PORTE_bits.RE0
779 #define RE1 PORTE_bits.RE1
780 #define RE2 PORTE_bits.RE2
782 // ----- RCSTA bits --------------------
785 unsigned char RX9D:1;
786 unsigned char OERR:1;
787 unsigned char FERR:1;
788 unsigned char ADDEN:1;
789 unsigned char CREN:1;
790 unsigned char SREN:1;
792 unsigned char SPEN:1;
795 unsigned char RCD8:1;
811 unsigned char NOT_RC8:1;
821 unsigned char RC8_9:1;
825 extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits;
827 #define RX9D RCSTA_bits.RX9D
828 #define RCD8 RCSTA_bits.RCD8
829 #define OERR RCSTA_bits.OERR
830 #define FERR RCSTA_bits.FERR
831 #define ADDEN RCSTA_bits.ADDEN
832 #define CREN RCSTA_bits.CREN
833 #define SREN RCSTA_bits.SREN
834 #define RX9 RCSTA_bits.RX9
835 #define RC9 RCSTA_bits.RC9
836 #define NOT_RC8 RCSTA_bits.NOT_RC8
837 #define RC8_9 RCSTA_bits.RC8_9
838 #define SPEN RCSTA_bits.SPEN
840 // ----- SSPCON bits --------------------
843 unsigned char SSPM0:1;
844 unsigned char SSPM1:1;
845 unsigned char SSPM2:1;
846 unsigned char SSPM3:1;
848 unsigned char SSPEN:1;
849 unsigned char SSPOV:1;
850 unsigned char WCOL:1;
853 extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits;
855 #define SSPM0 SSPCON_bits.SSPM0
856 #define SSPM1 SSPCON_bits.SSPM1
857 #define SSPM2 SSPCON_bits.SSPM2
858 #define SSPM3 SSPCON_bits.SSPM3
859 #define CKP SSPCON_bits.CKP
860 #define SSPEN SSPCON_bits.SSPEN
861 #define SSPOV SSPCON_bits.SSPOV
862 #define WCOL SSPCON_bits.WCOL
864 // ----- SSPCON2 bits --------------------
868 unsigned char RSEN:1;
870 unsigned char RCEN:1;
871 unsigned char ACKEN:1;
872 unsigned char ACKDT:1;
873 unsigned char ACKSTAT:1;
874 unsigned char GCEN:1;
877 extern volatile __SSPCON2_bits_t __at(SSPCON2_ADDR) SSPCON2_bits;
879 #define SEN SSPCON2_bits.SEN
880 #define RSEN SSPCON2_bits.RSEN
881 #define PEN SSPCON2_bits.PEN
882 #define RCEN SSPCON2_bits.RCEN
883 #define ACKEN SSPCON2_bits.ACKEN
884 #define ACKDT SSPCON2_bits.ACKDT
885 #define ACKSTAT SSPCON2_bits.ACKSTAT
886 #define GCEN SSPCON2_bits.GCEN
888 // ----- SSPSTAT bits --------------------
903 unsigned char I2C_READ:1;
904 unsigned char I2C_START:1;
905 unsigned char I2C_STOP:1;
906 unsigned char I2C_DATA:1;
913 unsigned char NOT_W:1;
916 unsigned char NOT_A:1;
923 unsigned char NOT_WRITE:1;
926 unsigned char NOT_ADDRESS:1;
943 unsigned char READ_WRITE:1;
946 unsigned char DATA_ADDRESS:1;
951 extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits;
953 #define BF SSPSTAT_bits.BF
954 #define UA SSPSTAT_bits.UA
955 #define R SSPSTAT_bits.R
956 #define I2C_READ SSPSTAT_bits.I2C_READ
957 #define NOT_W SSPSTAT_bits.NOT_W
958 #define NOT_WRITE SSPSTAT_bits.NOT_WRITE
959 #define R_W SSPSTAT_bits.R_W
960 #define READ_WRITE SSPSTAT_bits.READ_WRITE
961 #define S SSPSTAT_bits.S
962 #define I2C_START SSPSTAT_bits.I2C_START
963 #define P SSPSTAT_bits.P
964 #define I2C_STOP SSPSTAT_bits.I2C_STOP
965 #define D SSPSTAT_bits.D
966 #define I2C_DATA SSPSTAT_bits.I2C_DATA
967 #define NOT_A SSPSTAT_bits.NOT_A
968 #define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS
969 #define D_A SSPSTAT_bits.D_A
970 #define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS
971 #define CKE SSPSTAT_bits.CKE
972 #define SMP SSPSTAT_bits.SMP
974 // ----- STATUS bits --------------------
980 unsigned char NOT_PD:1;
981 unsigned char NOT_TO:1;
987 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
989 #define C STATUS_bits.C
990 #define DC STATUS_bits.DC
991 #define Z STATUS_bits.Z
992 #define NOT_PD STATUS_bits.NOT_PD
993 #define NOT_TO STATUS_bits.NOT_TO
994 #define RP0 STATUS_bits.RP0
995 #define RP1 STATUS_bits.RP1
996 #define IRP STATUS_bits.IRP
998 // ----- T1CON bits --------------------
1001 unsigned char TMR1ON:1;
1002 unsigned char TMR1CS:1;
1003 unsigned char NOT_T1SYNC:1;
1004 unsigned char T1OSCEN:1;
1005 unsigned char T1CKPS0:1;
1006 unsigned char T1CKPS1:1;
1013 unsigned char T1INSYNC:1;
1023 unsigned char T1SYNC:1;
1031 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
1033 #define TMR1ON T1CON_bits.TMR1ON
1034 #define TMR1CS T1CON_bits.TMR1CS
1035 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
1036 #define T1INSYNC T1CON_bits.T1INSYNC
1037 #define T1SYNC T1CON_bits.T1SYNC
1038 #define T1OSCEN T1CON_bits.T1OSCEN
1039 #define T1CKPS0 T1CON_bits.T1CKPS0
1040 #define T1CKPS1 T1CON_bits.T1CKPS1
1042 // ----- T2CON bits --------------------
1045 unsigned char T2CKPS0:1;
1046 unsigned char T2CKPS1:1;
1047 unsigned char TMR2ON:1;
1048 unsigned char TOUTPS0:1;
1049 unsigned char TOUTPS1:1;
1050 unsigned char TOUTPS2:1;
1051 unsigned char TOUTPS3:1;
1055 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
1057 #define T2CKPS0 T2CON_bits.T2CKPS0
1058 #define T2CKPS1 T2CON_bits.T2CKPS1
1059 #define TMR2ON T2CON_bits.TMR2ON
1060 #define TOUTPS0 T2CON_bits.TOUTPS0
1061 #define TOUTPS1 T2CON_bits.TOUTPS1
1062 #define TOUTPS2 T2CON_bits.TOUTPS2
1063 #define TOUTPS3 T2CON_bits.TOUTPS3
1065 // ----- TRISA bits --------------------
1068 unsigned char TRISA0:1;
1069 unsigned char TRISA1:1;
1070 unsigned char TRISA2:1;
1071 unsigned char TRISA3:1;
1072 unsigned char TRISA4:1;
1073 unsigned char TRISA5:1;
1078 extern volatile __TRISA_bits_t __at(TRISA_ADDR) TRISA_bits;
1080 #define TRISA0 TRISA_bits.TRISA0
1081 #define TRISA1 TRISA_bits.TRISA1
1082 #define TRISA2 TRISA_bits.TRISA2
1083 #define TRISA3 TRISA_bits.TRISA3
1084 #define TRISA4 TRISA_bits.TRISA4
1085 #define TRISA5 TRISA_bits.TRISA5
1087 // ----- TRISB bits --------------------
1090 unsigned char TRISB0:1;
1091 unsigned char TRISB1:1;
1092 unsigned char TRISB2:1;
1093 unsigned char TRISB3:1;
1094 unsigned char TRISB4:1;
1095 unsigned char TRISB5:1;
1096 unsigned char TRISB6:1;
1097 unsigned char TRISB7:1;
1100 extern volatile __TRISB_bits_t __at(TRISB_ADDR) TRISB_bits;
1102 #define TRISB0 TRISB_bits.TRISB0
1103 #define TRISB1 TRISB_bits.TRISB1
1104 #define TRISB2 TRISB_bits.TRISB2
1105 #define TRISB3 TRISB_bits.TRISB3
1106 #define TRISB4 TRISB_bits.TRISB4
1107 #define TRISB5 TRISB_bits.TRISB5
1108 #define TRISB6 TRISB_bits.TRISB6
1109 #define TRISB7 TRISB_bits.TRISB7
1111 // ----- TRISC bits --------------------
1114 unsigned char TRISC0:1;
1115 unsigned char TRISC1:1;
1116 unsigned char TRISC2:1;
1117 unsigned char TRISC3:1;
1118 unsigned char TRISC4:1;
1119 unsigned char TRISC5:1;
1120 unsigned char TRISC6:1;
1121 unsigned char TRISC7:1;
1124 extern volatile __TRISC_bits_t __at(TRISC_ADDR) TRISC_bits;
1126 #define TRISC0 TRISC_bits.TRISC0
1127 #define TRISC1 TRISC_bits.TRISC1
1128 #define TRISC2 TRISC_bits.TRISC2
1129 #define TRISC3 TRISC_bits.TRISC3
1130 #define TRISC4 TRISC_bits.TRISC4
1131 #define TRISC5 TRISC_bits.TRISC5
1132 #define TRISC6 TRISC_bits.TRISC6
1133 #define TRISC7 TRISC_bits.TRISC7
1135 // ----- TRISD bits --------------------
1138 unsigned char TRISD0:1;
1139 unsigned char TRISD1:1;
1140 unsigned char TRISD2:1;
1141 unsigned char TRISD3:1;
1142 unsigned char TRISD4:1;
1143 unsigned char TRISD5:1;
1144 unsigned char TRISD6:1;
1145 unsigned char TRISD7:1;
1148 extern volatile __TRISD_bits_t __at(TRISD_ADDR) TRISD_bits;
1150 #define TRISD0 TRISD_bits.TRISD0
1151 #define TRISD1 TRISD_bits.TRISD1
1152 #define TRISD2 TRISD_bits.TRISD2
1153 #define TRISD3 TRISD_bits.TRISD3
1154 #define TRISD4 TRISD_bits.TRISD4
1155 #define TRISD5 TRISD_bits.TRISD5
1156 #define TRISD6 TRISD_bits.TRISD6
1157 #define TRISD7 TRISD_bits.TRISD7
1159 // ----- TRISE bits --------------------
1162 unsigned char TRISE0:1;
1163 unsigned char TRISE1:1;
1164 unsigned char TRISE2:1;
1166 unsigned char PSPMODE:1;
1167 unsigned char IBOV:1;
1168 unsigned char OBF:1;
1169 unsigned char IBF:1;
1172 extern volatile __TRISE_bits_t __at(TRISE_ADDR) TRISE_bits;
1174 #define TRISE0 TRISE_bits.TRISE0
1175 #define TRISE1 TRISE_bits.TRISE1
1176 #define TRISE2 TRISE_bits.TRISE2
1177 #define PSPMODE TRISE_bits.PSPMODE
1178 #define IBOV TRISE_bits.IBOV
1179 #define OBF TRISE_bits.OBF
1180 #define IBF TRISE_bits.IBF
1182 // ----- TXSTA bits --------------------
1185 unsigned char TX9D:1;
1186 unsigned char TRMT:1;
1187 unsigned char BRGH:1;
1189 unsigned char SYNC:1;
1190 unsigned char TXEN:1;
1191 unsigned char TX9:1;
1192 unsigned char CSRC:1;
1195 unsigned char TXD8:1;
1201 unsigned char NOT_TX8:1;
1211 unsigned char TX8_9:1;
1215 extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits;
1217 #define TX9D TXSTA_bits.TX9D
1218 #define TXD8 TXSTA_bits.TXD8
1219 #define TRMT TXSTA_bits.TRMT
1220 #define BRGH TXSTA_bits.BRGH
1221 #define SYNC TXSTA_bits.SYNC
1222 #define TXEN TXSTA_bits.TXEN
1223 #define TX9 TXSTA_bits.TX9
1224 #define NOT_TX8 TXSTA_bits.NOT_TX8
1225 #define TX8_9 TXSTA_bits.TX8_9
1226 #define CSRC TXSTA_bits.CSRC