Merge branch 'new_wb_intercon' into new_eth

Functionality should not change at all

Conflicts:
	usrp2/fpga/top/u2_core/u2_core.v

diff --cc usrp2/fpga/top/u2_core/u2_core.v
index 363f7340e702d7b9db041b01ab3537caf27a712a,5718366d5fce4749a35cb88e67327522e817f345..1f78f6d3d5eb49477dd05f9d229fe7aa2fcda76c
--- 1/usrp2/fpga/top/u2_core/u2_core.v
--- 2/usrp2/fpga/top/u2_core/u2_core.v
+++ b/usrp2/fpga/top/u2_core/u2_core.v
@@@ -307,24 -315,22 +315,24 @@@ module u2_cor
                                         .in(set_data),.out(),.changed(flush_icache));
  
     // Buffer Pool, slave #1
 -   wire        rd0_read, rd0_sop, rd0_error, rd0_done, rd0_eop;
 -   wire        rd1_read, rd1_sop, rd1_error, rd1_done, rd1_eop;
 -   wire        rd2_read, rd2_sop, rd2_error, rd2_done, rd2_eop;
 -   wire        rd3_read, rd3_sop, rd3_error, rd3_done, rd3_eop;
 +   wire        rd0_ready_i, rd0_ready_o;
 +   wire        rd1_ready_i, rd1_ready_o;
 +   wire        rd2_ready_i, rd2_ready_o;
 +   wire        rd3_ready_i, rd3_ready_o;
 +   wire [3:0]          rd0_flags, rd1_flags, rd2_flags, rd3_flags;
     wire [31:0]         rd0_dat, rd1_dat, rd2_dat, rd3_dat;
  
 -   wire        wr0_write, wr0_done, wr0_error, wr0_ready, wr0_full;
 -   wire        wr1_write, wr1_done, wr1_error, wr1_ready, wr1_full;
 -   wire        wr2_write, wr2_done, wr2_error, wr2_ready, wr2_full;
 -   wire        wr3_write, wr3_done, wr3_error, wr3_ready, wr3_full;
 +   wire        wr0_ready_i, wr0_ready_o;
 +   wire        wr1_ready_i, wr1_ready_o;
 +   wire        wr2_ready_i, wr2_ready_o;
 +   wire        wr3_ready_i, wr3_ready_o;
 +   wire [3:0]          wr0_flags, wr1_flags, wr2_flags, wr3_flags;
     wire [31:0]         wr0_dat, wr1_dat, wr2_dat, wr3_dat;
     
 -   buffer_pool buffer_pool
 +   buffer_pool #(.BUF_SIZE(9), .SET_ADDR(64)) buffer_pool
       (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),
        .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o),   
-       .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(s1_err),.wb_rty_o(s1_rty),
+       .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(),.wb_rty_o(),
     
        .stream_clk(dsp_clk), .stream_rst(dsp_rst),
        .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
@@@ -392,30 -400,8 +394,24 @@@
        .word11(32'b0),.word12(32'b0),.word13(32'b0),.word14(32'b0),.word15(32'b0)
        );
  
-    assign      s5_err  = 1'b0;
-    assign      s5_rty  = 1'b0;
- 
 -   // Slave, #6 Ethernet MAC, see below
 +   // /////////////////////////////////////////////////////////////////////////
 +   // Ethernet MAC  Slave #6
 +
 +   simple_gemac_wrapper #(.RXFIFOSIZE(11), .TXFIFOSIZE(6)) simple_gemac_wrapper
 +     (.clk125(clk_to_mac),  .reset(wb_rst),
 +      .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN),  
 +      .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD),
 +      .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV),  
 +      .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD),
 +      .sys_clk(dsp_clk),
 +      .rx_f36_data({wr2_flags,wr2_dat}), .rx_f36_src_rdy(wr2_ready_i), .rx_f36_dst_rdy(wr2_ready_o),
 +      .tx_f36_data({rd2_flags,rd2_dat}), .tx_f36_src_rdy(rd2_ready_o), .tx_f36_dst_rdy(rd2_ready_i),
 +      .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(s6_stb), .wb_cyc(s6_cyc), .wb_ack(s6_ack),
 +      .wb_we(s6_we), .wb_adr(s6_adr), .wb_dat_i(s6_dat_o), .wb_dat_o(s6_dat_i),
 +      .mdio(MDIO), .mdc(MDC),
 +      .debug(debug_mac));
     
-    assign      s6_err  = 1'b0;
-    assign      s6_rty  = 1'b0;
-    
 +   // /////////////////////////////////////////////////////////////////////////
     // Settings Bus -- Slave #7
     settings_bus settings_bus
       (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s7_adr),.wb_dat_i(s7_dat_o),