wbxng_base::~wbxng_base()
{
- if (d_common)
- delete d_common;
}
int
freq_t int_freq = freq_t(std::max(freq_min(), std::min(freq, freq_max())));
bool ok = d_common->_set_freq(int_freq*2, _refclk_freq());
+
+ _write_spi(d_common->compute_register(5));
+ _write_spi(d_common->compute_register(4));
+ _write_spi(d_common->compute_register(3));
+ /* load involved registers */
+ _write_spi(d_common->compute_register(2));
+ _write_spi(d_common->compute_register(1));
+ _write_spi(d_common->compute_register(0));
+
double freq_result = (double) d_common->_get_freq(_refclk_freq())/2.0;
+
+ //ok &= _get_locked();
struct freq_result_t args = {ok, freq_result};
/* Wait before reading Lock Detect*/
return (double) d_common->_get_max_freq()/2.0;
}
+bool
+wbxng_base::_get_locked(void)
+{
+ return usrp()->read_io(d_which) & PLL_LOCK_DETECT;
+}
+
+void
+wbxng_base::_write_spi(std::string data)
+{
+ usrp()->_write_spi(0, d_spi_enable, d_spi_format, data);
+}
+
// ----------------------------------------------------------------
db_wbxng_tx::db_wbxng_tx(usrp_basic_sptr _usrp, int which)
d_spi_enable = SPI_ENABLE_TX_B;
}
- d_common = new adf4350(_usrp, d_which, d_spi_enable);
+ d_common = boost::shared_ptr<adf4350> (new adf4350());
+
+ /* Initialize the registers. */
+ _write_spi(d_common->compute_register(5));
+ _write_spi(d_common->compute_register(4));
+ _write_spi(d_common->compute_register(3));
+ _write_spi(d_common->compute_register(2));
+ _write_spi(d_common->compute_register(1));
+ _write_spi(d_common->compute_register(0));
// power up the transmit side, but don't enable the mixer
- usrp()->_write_oe(d_which,(RX_TXN|TXMOD_EN|ENABLE_33|ENABLE_5), (RX_TXN|TXMOD_EN|ENABLE_33|ENABLE_5));
- usrp()->write_io(d_which, (RX_TXN|ENABLE_33|ENABLE_5), (RX_TXN|ENABLE_33|ENABLE_5));
+ usrp()->_write_oe(d_which,(PLL_CE|PLL_PDBRF|RX_TXN|TXMOD_EN|ENABLE_33|ENABLE_5), (PLL_CE|PLL_PDBRF|RX_TXN|TXMOD_EN|ENABLE_33|ENABLE_5));
+ usrp()->write_io(d_which, (PLL_CE|RX_TXN|ENABLE_33|ENABLE_5), (PLL_CE|PLL_PDBRF|RX_TXN|ENABLE_33|ENABLE_5));
//set_lo_offset(4e6);
// Disable VCO/PLL
- d_common->_enable(true);
+ //d_common->_enable(true);
+ usrp()->write_io(d_which, (PLL_PDBRF), (PLL_PDBRF));
set_gain((gain_min() + gain_max()) / 2.0); // initialize gain
}
shutdown();
}
-
void
db_wbxng_tx::shutdown()
{
// do whatever there is to do to shutdown
// Disable VCO/PLL
- d_common->_enable(false);
+ //d_common->_enable(false);
+ usrp()->write_io(d_which, 0, (PLL_PDBRF));
// Power down and leave the T/R switch in the R position
- usrp()->write_io(d_which, (RX_TXN), (RX_TXN|ENABLE_33|ENABLE_5));
-
+ usrp()->write_io(d_which, (RX_TXN), (PLL_CE|PLL_PDBRF|RX_TXN|ENABLE_33|ENABLE_5));
/*
_write_control(_compute_control_reg());
d_spi_enable = SPI_ENABLE_RX_B;
}
- d_common = new adf4350(_usrp, d_which, d_spi_enable);
+ d_common = boost::shared_ptr<adf4350> (new adf4350());
+
+ /* Initialize the registers. */
+ _write_spi(d_common->compute_register(5));
+ _write_spi(d_common->compute_register(4));
+ _write_spi(d_common->compute_register(3));
+ _write_spi(d_common->compute_register(2));
+ _write_spi(d_common->compute_register(1));
+ _write_spi(d_common->compute_register(0));
// Disable VCO/PLL
- d_common->_enable(true);
+ //d_common->_enable(true);
+ usrp()->write_io(d_which, (PLL_PDBRF), (PLL_PDBRF));
- usrp()->_write_oe(d_which, (RX2_RX1N|RXBB_EN|ATTN_MASK|ENABLE_33|ENABLE_5), (RX2_RX1N|RXBB_EN|ATTN_MASK|ENABLE_33|ENABLE_5));
- usrp()->write_io(d_which, (RX2_RX1N|RXBB_EN|ENABLE_33|ENABLE_5), (RX2_RX1N|RXBB_EN|ATTN_MASK|ENABLE_33|ENABLE_5));
+ usrp()->_write_oe(d_which, (PLL_CE|PLL_PDBRF|RX2_RX1N|RXBB_EN|ATTN_MASK|ENABLE_33|ENABLE_5), (PLL_CE|PLL_PDBRF|RX2_RX1N|RXBB_EN|ATTN_MASK|ENABLE_33|ENABLE_5));
+ usrp()->write_io(d_which, (PLL_CE|RX2_RX1N|RXBB_EN|ENABLE_33|ENABLE_5), (PLL_CE|PLL_PDBRF|RX2_RX1N|RXBB_EN|ATTN_MASK|ENABLE_33|ENABLE_5));
//fprintf(stderr,"Setting WBXNG RXBB on");
// set up for RX on TX/RX port
// do whatever there is to do to shutdown
// Power down VCO/PLL
- d_common->_enable(false);
+ //d_common->_enable(false);
+ usrp()->write_io(d_which, 0, (PLL_PDBRF));
// fprintf(stderr, "db_wbxng_rx::shutdown before _write_control\n");
//_write_control(_compute_control_reg());
set_auto_tr(false);
// Power down
- usrp()->write_io(d_which, 0, (RX2_RX1N|RXBB_EN|ATTN_MASK|ENABLE_33|ENABLE_5));
+ usrp()->write_io(d_which, 0, (PLL_CE|PLL_PDBRF|RX2_RX1N|RXBB_EN|ATTN_MASK|ENABLE_33|ENABLE_5));
// fprintf(stderr, "db_wbxng_rx::shutdown after set_auto_tr\n");
}
float pga_gain, agc_gain;
float maxgain = gain_max() - usrp()->pga_max();
- float mingain = gain_min();
if(gain > maxgain) {
pga_gain = gain-maxgain;
assert(pga_gain <= usrp()->pga_max());
#define MUX_PIN (1 << 1)
#define LD_PIN (1 << 0)
-adf4350::adf4350(usrp_basic_sptr _usrp, int _which, int _spi_enable)
+adf4350::adf4350()
{
- /* Initialize the pin directions. */
-
- d_usrp = _usrp;
- d_which = _which;
- d_spi_enable = _spi_enable;
- d_spi_format = SPI_FMT_MSB | SPI_FMT_HDR_0;
-
- d_regs = new adf4350_regs(this);
-
- /* Outputs */
- d_usrp->_write_oe(d_which, (CE_PIN | PDB_RF_PIN), (CE_PIN | PDB_RF_PIN));
- d_usrp->write_io(d_which, (CE_PIN), (CE_PIN | PDB_RF_PIN));
-
- /* Initialize the pin levels. */
- _enable(true);
- /* Initialize the registers. */
- d_regs->_load_register(5);
- d_regs->_load_register(4);
- d_regs->_load_register(3);
- d_regs->_load_register(2);
- d_regs->_load_register(1);
- d_regs->_load_register(0);
+ d_regs = new adf4350_regs();
}
adf4350::~adf4350()
{
- d_usrp->write_io(d_which, (0), (CE_PIN | PDB_RF_PIN));
delete d_regs;
}
-freq_t
-adf4350::_get_max_freq(void)
-{
- return MAX_FREQ;
-}
-
-freq_t
-adf4350::_get_min_freq(void)
-{
- return MIN_FREQ;
-}
-
-bool
-adf4350::_get_locked(void)
-{
- return d_usrp->read_io(d_which) & LD_PIN;
-}
-
-void
-adf4350::_enable(bool enable)
+std::string
+adf4350::compute_register(uint8_t addr)
{
- if (enable){ /* chip enable */
- d_usrp->write_io(d_which, (PDB_RF_PIN), (PDB_RF_PIN));
- }else{
- d_usrp->write_io(d_which, 0, (PDB_RF_PIN));
- }
-}
+ uint32_t data = d_regs->compute_register(addr);
-void
-adf4350::_write(uint8_t addr, uint32_t data)
-{
data |= addr;
- // create str from data here
+ // create std::string from data here
char s[4];
s[0] = (char)((data >> 24) & 0xff);
s[1] = (char)((data >> 16) & 0xff);
s[2] = (char)((data >> 8) & 0xff);
s[3] = (char)(data & 0xff);
- std::string str(s, 4);
-
- timespec t;
- t.tv_sec = 0;
- t.tv_nsec = 5e6;
+ return std::string(s, 4);
+}
- nanosleep(&t, NULL);
- d_usrp->_write_spi(0, d_spi_enable, d_spi_format, str);
- nanosleep(&t, NULL);
+freq_t
+adf4350::_get_max_freq(void)
+{
+ return MAX_FREQ;
+}
- //fprintf(stderr, "Wrote to WBXNG SPI address %d with data %8x\n", addr, data);
- /* pulse latch */
- //d_usrp->write_io(d_which, 1, LE_PIN);
- //d_usrp->write_io(d_which, 0, LE_PIN);
+freq_t
+adf4350::_get_min_freq(void)
+{
+ return MIN_FREQ;
}
bool
refclock_freq/(d_regs->d_8_bit_band_select_clock_divider_value * d_regs->d_10_bit_r_counter) + 1
);
*/
- d_regs->_load_register(5);
- d_regs->_load_register(3);
- d_regs->_load_register(1);
- /* load involved registers */
- d_regs->_load_register(2);
- d_regs->_load_register(4);
- d_regs->_load_register(0); /* register 0 must be last */
return true;
}
* Keep precision by doing multiplies first:
* freq = (((((((int)*mod) + frac)*ref)/mod)/r)/div)
*/
- uint64_t temp;
- temp = d_regs->d_int;
- temp *= d_regs->d_mod;
- temp += d_regs->d_frac;
- temp *= refclock_freq;
- temp /= d_regs->d_mod;
- temp /= d_regs->d_10_bit_r_counter;
- temp /= (1 << d_regs->d_divider_select);
- return temp;
+ uint64_t freq;
+ freq = d_regs->d_int;
+ freq *= d_regs->d_mod;
+ freq += d_regs->d_frac;
+ freq *= refclock_freq;
+ freq /= d_regs->d_mod;
+ freq /= d_regs->d_10_bit_r_counter;
+ freq /= (1 << d_regs->d_divider_select);
+ return freq;
}