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   1 /* -*- c++ -*- */
   2 /*
   3  * Copyright 2004 Free Software Foundation, Inc.
   4  *
   5  * This file is part of GNU Radio
   6  *
   7  * GNU Radio is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 3, or (at your option)
  10  * any later version.
  11  *
  12  * GNU Radio is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with GNU Radio; see the file COPYING.  If not, write to
  19  * the Free Software Foundation, Inc., 51 Franklin Street,
  20  * Boston, MA 02110-1301, USA.
  21  */
  22
  23 #ifndef INCLUDED_AD9862_H
  24 #define INCLUDED_AD9862_H
  25
  26 /*
  27  * Analog Devices AD9862 registers and some fields
  28  */
  29
  30 #define BEGIN_AD9862    namespace ad9862 {
  31 #define END_AD962       }
  32 #define DEF static const int
  33
  34 BEGIN_AD9862;
  35
  36 DEF REG_GENERAL         =  0;
  37 DEF REG_RX_PWR_DN       =  1;
  38 DEF     RX_PWR_DN_VREF_DIFF             = (1 << 7);
  39 DEF     RX_PWR_DN_VREF                  = (1 << 6);
  40 DEF     RX_PWR_DN_RX_DIGIGAL            = (1 << 5);
  41 DEF     RX_PWR_DN_RX_B                  = (1 << 4);
  42 DEF     RX_PWR_DN_RX_A                  = (1 << 3);
  43 DEF     RX_PWR_DN_BUF_B                 = (1 << 2);
  44 DEF     RX_PWR_DN_BUF_A                 = (1 << 1);
  45 DEF     RX_PWR_DN_ALL                   = (1 << 0);
  46
  47 DEF REG_RX_A            =  2;   // bypass input buffer / RxPGA
  48 DEF REG_RX_B            =  3;   // pypass input buffer / RxPGA
  49 DEF     RX_X_BYPASS_INPUT_BUFFER        = (1 << 7);
  50
  51 DEF REG_RX_MISC         =  4;
  52 DEF     RX_MISC_HS_DUTY_CYCLE           = (1 << 2);
  53 DEF     RX_MISC_SHARED_REF              = (1 << 1);
  54 DEF     RX_MISC_CLK_DUTY                = (1 << 0);
  55
  56 DEF REG_RX_IF           =  5;
  57 DEF     RX_IF_THREE_STATE               = (1 << 4);
  58 DEF     RX_IF_USE_CLKOUT1               = (0 << 3);
  59 DEF     RX_IF_USE_CLKOUT2               = (1 << 3);     // aka Rx Retime
  60 DEF     RX_IF_2S_COMP                   = (1 << 2);
  61 DEF     RX_IF_INV_RX_SYNC               = (1 << 1);
  62 DEF     RX_IF_MUX_OUT                   = (1 << 0);
  63
  64 DEF REG_RX_DIGITAL      =  6;
  65 DEF     RX_DIGITAL_2_CHAN               = (1 << 3);
  66 DEF     RX_DIGITAL_KEEP_MINUS_VE        = (1 << 2);
  67 DEF     RX_DIGITAL_HILBERT              = (1 << 1);
  68 DEF     RX_DIGITAL_DECIMATE             = (1 << 0);
  69
  70 DEF REG_RESERVED_7      =  7;
  71
  72 DEF REG_TX_PWR_DN       =  8;
  73 DEF     TX_PWR_DN_ALT_TIMING_MODE       = (1 << 5);
  74 DEF     TX_PWR_DN_TX_OFF_ENABLE         = (1 << 4);
  75 DEF     TX_PWR_DN_TX_DIGITAL            = (1 << 3);
  76 DEF     TX_PWR_DN_TX_ANALOG_B           = 0x4;
  77 DEF     TX_PWR_DN_TX_ANALOG_A           = 0x2;
  78 DEF     TX_PWR_DN_TX_ANALOG_BOTH        = 0x7;
  79
  80 DEF REG_RESERVED_9      =  9;
  81
  82 DEF REG_TX_A_OFFSET_LO  = 10;
  83 DEF REG_TX_A_OFFSET_HI  = 11;
  84 DEF REG_TX_B_OFFSET_LO  = 12;
  85 DEF REG_TX_B_OFFSET_HI  = 13;
  86
  87 DEF REG_TX_A_GAIN       = 14;   // fine trim for matching
  88 DEF REG_TX_B_GAIN       = 15;   // fine trim for matching
  89 DEF     TX_X_GAIN_COARSE_FULL           = (3 << 6);
  90 DEF     TX_X_GAIN_COARSE_1_HALF         = (1 << 6);
  91 DEF     TX_X_GAIN_COARSE_1_ELEVENTH     = (0 << 6);
  92
  93 DEF REG_TX_PGA          = 16;   // 20 dB continuous gain in 0.1 dB steps
  94                                 // 0x00 = min gain (-20 dB)
  95                                 // 0xff = max gain (  0 dB)
  96
  97 DEF REG_TX_MISC         = 17;
  98 DEF     TX_MISC_SLAVE_ENABLE            = (1 << 1);
  99 DEF     TX_MISC_TX_PGA_FAST             = (1 << 0);
 100
 101 DEF REG_TX_IF           = 18;
 102 DEF     TX_IF_USE_CLKOUT2               = (0 << 6);
 103 DEF     TX_IF_USE_CLKOUT1               = (1 << 6);     // aka Tx Retime
 104 DEF     TX_IF_I_FIRST                   = (0 << 5);
 105 DEF     TX_IF_Q_FIRST                   = (1 << 5);
 106 DEF     TX_IF_INV_TX_SYNC               = (1 << 4);
 107 DEF     TX_IF_2S_COMP                   = (1 << 3);
 108 DEF     TX_IF_INVERSE_SAMPLE            = (1 << 2);
 109 DEF     TX_IF_TWO_EDGES                 = (1 << 1);
 110 DEF     TX_IF_INTERLEAVED               = (1 << 0);
 111
 112 DEF REG_TX_DIGITAL      = 19;
 113 DEF     TX_DIGITAL_2_DATA_PATHS         = (1 << 4);
 114 DEF     TX_DIGITAL_KEEP_NEGATIVE        = (1 << 3);
 115 DEF     TX_DIGITAL_HILBERT              = (1 << 2);
 116 DEF     TX_DIGITAL_INTERPOLATE_NONE     = 0x0;
 117 DEF     TX_DIGITAL_INTERPOLATE_2X       = 0x1;
 118 DEF     TX_DIGITAL_INTERPOLATE_4X       = 0x2;
 119
 120 DEF REG_TX_MODULATOR    = 20;
 121 DEF     TX_MODULATOR_NEG_FINE_TUNE      = (1 << 5);
 122 DEF     TX_MODULATOR_DISABLE_NCO        = (0 << 4);
 123 DEF     TX_MODULATOR_ENABLE_NCO         = (1 << 4);     // aka Fine Mode
 124 DEF     TX_MODULATOR_REAL_MIX_MODE      = (1 << 3);
 125 DEF     TX_MODULATOR_NEG_COARSE_TUNE    = (1 << 2);
 126 DEF     TX_MODULATOR_COARSE_MODULATION_NONE     = 0x0;
 127 DEF     TX_MODULATOR_COARSE_MODULATION_F_OVER_4 = 0x1;
 128 DEF     TX_MODULATOR_COARSE_MODULATION_F_OVER_8 = 0x2;
 129 DEF     TX_MODULATOR_CM_MASK                    = 0x7;
 130
 131
 132 DEF REG_TX_NCO_FTW_7_0  = 21;
 133 DEF REG_TX_NCO_FTW_15_8 = 22;
 134 DEF REG_TX_NCO_FTW_23_16= 23;
 135
 136 DEF REG_DLL             = 24;
 137 DEF     DLL_DISABLE_INTERNAL_XTAL_OSC   = (1 << 6);     // aka Input Clock Ctrl
 138 DEF     DLL_ADC_DIV2                    = (1 << 5);
 139 DEF     DLL_MULT_1X                     = (0 << 3);
 140 DEF     DLL_MULT_2X                     = (1 << 3);
 141 DEF     DLL_MULT_4X                     = (2 << 3);
 142 DEF     DLL_PWR_DN                      = (1 << 2);
 143 // undefined bit                        = (1 << 1);
 144 DEF     DLL_FAST                        = (1 << 0);
 145
 146 DEF REG_CLKOUT          = 25;
 147 DEF     CLKOUT2_EQ_DLL                  = (0 << 6);
 148 DEF     CLKOUT2_EQ_DLL_OVER_2           = (1 << 6);
 149 DEF     CLKOUT2_EQ_DLL_OVER_4           = (2 << 6);
 150 DEF     CLKOUT2_EQ_DLL_OVER_8           = (3 << 6);
 151 DEF     CLKOUT_INVERT_CLKOUT2           = (1 << 5);
 152 DEF     CLKOUT_DISABLE_CLKOUT2          = (1 << 4);
 153 // undefined bit                        = (1 << 3);
 154 // undefined bit                        = (1 << 2);
 155 DEF     CLKOUT_INVERT_CLKOUT1           = (1 << 1);
 156 DEF     CLKOUT_DISABLE_CLKOUT1          = (1 << 0);
 157
 158 DEF REG_AUX_ADC_A2_LO   = 26;
 159 DEF REG_AUX_ADC_A2_HI   = 27;
 160 DEF REG_AUX_ADC_A1_LO   = 28;
 161 DEF REG_AUX_ADC_A1_HI   = 29;
 162 DEF REG_AUX_ADC_B2_LO   = 30;
 163 DEF REG_AUX_ADC_B2_HI   = 31;
 164 DEF REG_AUX_ADC_B1_LO   = 32;
 165 DEF REG_AUX_ADC_B1_HI   = 33;
 166
 167 DEF REG_AUX_ADC_CTRL    = 34;
 168 DEF     AUX_ADC_CTRL_AUX_SPI            = (1 << 7);
 169 DEF     AUX_ADC_CTRL_SELBNOTA           = (1 << 6);
 170 DEF     AUX_ADC_CTRL_REFSEL_B           = (1 << 5);
 171 DEF     AUX_ADC_CTRL_SELECT_B2          = (0 << 4);
 172 DEF     AUX_ADC_CTRL_SELECT_B1          = (1 << 4);
 173 DEF     AUX_ADC_CTRL_START_B            = (1 << 3);
 174 DEF     AUX_ADC_CTRL_REFSEL_A           = (1 << 2);
 175 DEF     AUX_ADC_CTRL_SELECT_A2          = (0 << 1);
 176 DEF     AUX_ADC_CTRL_SELECT_A1          = (1 << 1);
 177 DEF     AUX_ADC_CTRL_START_A            = (1 << 0);
 178
 179 DEF REG_AUX_ADC_CLK     = 35;
 180 DEF     AUX_ADC_CLK_CLK_OVER_4          = (1 << 0);
 181
 182 DEF REG_AUX_DAC_A       = 36;
 183 DEF REG_AUX_DAC_B       = 37;
 184 DEF REG_AUX_DAC_C       = 38;
 185
 186 DEF REG_AUX_DAC_UPDATE  = 39;
 187 DEF     AUX_DAC_UPDATE_SLAVE_ENABLE     = (1 << 7);
 188 DEF     AUX_DAC_UPDATE_C                = (1 << 2);
 189 DEF     AUX_DAC_UPDATE_B                = (1 << 1);
 190 DEF     AUX_DAC_UPDATE_A                = (1 << 0);
 191
 192 DEF REG_AUX_DAC_PWR_DN  = 40;
 193 DEF     AUX_DAC_PWR_DN_C                = (1 << 2);
 194 DEF     AUX_DAC_PWR_DN_B                = (1 << 1);
 195 DEF     AUX_DAC_PWR_DN_A                = (1 << 0);
 196
 197 DEF REG_AUX_DAC_CTRL    = 41;
 198 DEF     AUX_DAC_CTRL_INV_C              = (1 << 4);
 199 DEF     AUX_DAC_CTRL_INV_B              = (1 << 2);
 200 DEF     AUX_DAC_CTRL_INV_A              = (1 << 0);
 201
 202 DEF REG_SIGDELT_LO      = 42;
 203 DEF REG_SIGDELT_HI      = 43;
 204
 205 // 44 to 48 reserved
 206
 207 DEF REG_ADC_LOW_PWR_LO  = 49;
 208 DEF REG_ADC_LOW_PWR_HI  = 50;
 209
 210 // 51 to 62 reserved
 211
 212 DEF REG_CHIP_ID         = 63;
 213
 214
 215 END_AD962;
 216
 217 #undef DEF
 218 #undef BEGIN_AD9862
 219 #undef END_AD962
 220
 221 #endif /* INCLUDED_AD9862_H */