git.gag.com Git - debian/gnuradio/blob - usrp/fpga/toplevel/sizetest/sizetest.psf

   1 DEFAULT_DESIGN_ASSISTANT_SETTINGS
   2 {
   3         HCPY_ALOAD_SIGNALS = OFF;
   4         HCPY_VREF_PINS = OFF;
   5         HCPY_CAT = OFF;
   6         HCPY_ILLEGAL_HC_DEV_PKG = OFF;
   7         ACLK_RULE_IMSZER_ADOMAIN = OFF;
   8         ACLK_RULE_SZER_BTW_ACLK_DOMAIN = OFF;
   9         ACLK_RULE_NO_SZER_ACLK_DOMAIN = OFF;
  10         ACLK_CAT = OFF;
  11         SIGNALRACE_RULE_ASYNCHPIN_SYNCH_CLKPIN = OFF;
  12         SIGNALRACE_CAT = OFF;
  13         NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED = OFF;
  14         NONSYNCHSTRUCT_RULE_SRLATCH = OFF;
  15         NONSYNCHSTRUCT_RULE_DLATCH = OFF;
  16         NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR = OFF;
  17         NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN = OFF;
  18         NONSYNCHSTRUCT_RULE_RIPPLE_CLK = OFF;
  19         NONSYNCHSTRUCT_RULE_DELAY_CHAIN = OFF;
  20         NONSYNCHSTRUCT_RULE_REG_LOOP = OFF;
  21         NONSYNCHSTRUCT_RULE_COMBLOOP = OFF;
  22         NONSYNCHSTRUCT_CAT = OFF;
  23         NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE = OFF;
  24         TIMING_RULE_COIN_CLKEDGE = OFF;
  25         TIMING_RULE_SHIFT_REG = OFF;
  26         TIMING_RULE_HIGH_FANOUTS = OFF;
  27         TIMING_CAT = OFF;
  28         RESET_RULE_ALL = OFF;
  29         RESET_RULE_IMSYNCH_ASYNCH_DOMAIN = OFF;
  30         RESET_RULE_UNSYNCH_ASYNCH_DOMAIN = OFF;
  31         RESET_RULE_REG_ASNYCH = OFF;
  32         RESET_RULE_COMB_ASYNCH_RESET = OFF;
  33         RESET_RULE_IMSYNCH_EXRESET = OFF;
  34         RESET_RULE_UNSYNCH_EXRESET = OFF;
  35         RESET_RULE_INPINS_RESETNET = OFF;
  36         RESET_CAT = OFF;
  37         CLK_RULE_ALL = OFF;
  38         CLK_RULE_MIX_EDGES = OFF;
  39         CLK_RULE_CLKNET_CLKSPINES = OFF;
  40         CLK_RULE_INPINS_CLKNET = OFF;
  41         CLK_RULE_GATING_SCHEME = OFF;
  42         CLK_RULE_INV_CLOCK = OFF;
  43         CLK_RULE_COMB_CLOCK = OFF;
  44         CLK_CAT = OFF;
  45         HCPY_EXCEED_USER_IO_USAGE = OFF;
  46         HCPY_EXCEED_RAM_USAGE = OFF;
  47         NONSYNCHSTRUCT_RULE_ASYN_RAM = OFF;
  48         SIGNALRACE_RULE_TRISTATE = OFF;
  49         ASSG_RULE_MISSING_TIMING = OFF;
  50         ASSG_RULE_MISSING_FMAX = OFF;
  51         ASSG_CAT = OFF;
  52 }
  53 SYNTHESIS_FITTING_SETTINGS
  54 {
  55         AUTO_SHIFT_REGISTER_RECOGNITION = ON;
  56         AUTO_RAM_RECOGNITION = ON;
  57         REMOVE_DUPLICATE_LOGIC = ON;
  58         AUTO_MERGE_PLLS = ON;
  59         AUTO_OPEN_DRAIN_PINS = ON;
  60         AUTO_CARRY_CHAINS = ON;
  61         AUTO_DELAY_CHAINS = ON;
  62         STRATIX_CARRY_CHAIN_LENGTH = 70;
  63         AUTO_PACKED_REG_CYCLONE = "MINIMIZE AREA WITH CHAINS";
  64         CYCLONE_OPTIMIZATION_TECHNIQUE = SPEED;
  65         AUTO_GLOBAL_MEMORY_CONTROLS = OFF;
  66         AUTO_GLOBAL_REGISTER_CONTROLS = ON;
  67         AUTO_GLOBAL_CLOCK = ON;
  68         LIMIT_AHDL_INTEGERS_TO_32_BITS = OFF;
  69         ENABLE_BUS_HOLD_CIRCUITRY = OFF;
  70         WEAK_PULL_UP_RESISTOR = OFF;
  71         IGNORE_SOFT_BUFFERS = ON;
  72         IGNORE_LCELL_BUFFERS = OFF;
  73         IGNORE_ROW_GLOBAL_BUFFERS = OFF;
  74         IGNORE_GLOBAL_BUFFERS = OFF;
  75         IGNORE_CASCADE_BUFFERS = OFF;
  76         IGNORE_CARRY_BUFFERS = OFF;
  77         REMOVE_DUPLICATE_REGISTERS = ON;
  78         REMOVE_REDUNDANT_LOGIC_CELLS = OFF;
  79         ALLOW_POWER_UP_DONT_CARE = ON;
  80         PCI_IO = OFF;
  81         NOT_GATE_PUSH_BACK = ON;
  82         SLOW_SLEW_RATE = OFF;
  83         STATE_MACHINE_PROCESSING = AUTO;
  84 }
  85 DEFAULT_HARDCOPY_SETTINGS
  86 {
  87         HARDCOPY_EXTERNAL_CLOCK_JITTER = "0.0 NS";
  88 }
  89 DEFAULT_TIMING_REQUIREMENTS
  90 {
  91         INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF;
  92         RUN_ALL_TIMING_ANALYSES = ON;
  93         IGNORE_CLOCK_SETTINGS = OFF;
  94         DEFAULT_HOLD_MULTICYCLE = "SAME AS MULTICYCLE";
  95         CUT_OFF_IO_PIN_FEEDBACK = ON;
  96         CUT_OFF_CLEAR_AND_PRESET_PATHS = ON;
  97         CUT_OFF_READ_DURING_WRITE_PATHS = ON;
  98         CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS = ON;
  99         DO_MIN_ANALYSIS = ON;
 100         DO_MIN_TIMING = OFF;
 101         NUMBER_OF_PATHS_TO_REPORT = 200;
 102         NUMBER_OF_DESTINATION_TO_REPORT = 10;
 103         NUMBER_OF_SOURCES_PER_DESTINATION_TO_REPORT = 10;
 104         MAX_SCC_SIZE = 50;
 105 }
 106 HDL_SETTINGS
 107 {
 108         VERILOG_INPUT_VERSION = VERILOG_2001;
 109         ENABLE_IP_DEBUG = OFF;
 110         VHDL_INPUT_VERSION = VHDL93;
 111         VHDL_SHOW_LMF_MAPPING_MESSAGES = OFF;
 112 }
 113 PROJECT_INFO(sizetest)
 114 {
 115         USER_LIBRARIES = "e:\fpga\megacells\";
 116         ORIGINAL_QUARTUS_VERSION = 3.0;
 117         PROJECT_CREATION_TIME_DATE = "22:00:25  SEPTEMBER 28, 2003";
 118         LAST_QUARTUS_VERSION = 3.0;
 119         SHOW_REGISTRATION_MESSAGE = ON;
 120 }
 121 THIRD_PARTY_EDA_TOOLS(sizetest)
 122 {
 123         EDA_DESIGN_ENTRY_SYNTHESIS_TOOL = "<NONE>";
 124         EDA_SIMULATION_TOOL = "<NONE>";
 125         EDA_TIMING_ANALYSIS_TOOL = "<NONE>";
 126         EDA_BOARD_DESIGN_TOOL = "<NONE>";
 127         EDA_FORMAL_VERIFICATION_TOOL = "<NONE>";
 128         EDA_RESYNTHESIS_TOOL = "<NONE>";
 129 }
 130 EDA_TOOL_SETTINGS(eda_design_synthesis)
 131 {
 132         EDA_INPUT_GND_NAME = GND;
 133         EDA_INPUT_VCC_NAME = VCC;
 134         EDA_SHOW_LMF_MAPPING_MESSAGES = OFF;
 135         EDA_RUN_TOOL_AUTOMATICALLY = OFF;
 136         EDA_INPUT_DATA_FORMAT = EDIF;
 137         EDA_OUTPUT_DATA_FORMAT = NONE;
 138         USE_GENERATED_PHYSICAL_CONSTRAINTS = ON;
 139         RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL;
 140         RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL;
 141         RESYNTHESIS_RETIMING = FULL;
 142 }
 143 EDA_TOOL_SETTINGS(eda_simulation)
 144 {
 145         EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF;
 146         EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF;
 147         EDA_MAINTAIN_DESIGN_HIERARCHY = OFF;
 148         EDA_WRITE_DEVICE_CONTROL_PORTS = OFF;
 149         EDA_GENERATE_FUNCTIONAL_NETLIST = OFF;
 150         EDA_FLATTEN_BUSES = OFF;
 151         EDA_MAP_ILLEGAL_CHARACTERS = OFF;
 152         EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF;
 153         EDA_RUN_TOOL_AUTOMATICALLY = OFF;
 154         EDA_OUTPUT_DATA_FORMAT = NONE;
 155         USE_GENERATED_PHYSICAL_CONSTRAINTS = ON;
 156         RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL;
 157         RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL;
 158         RESYNTHESIS_RETIMING = FULL;
 159 }
 160 EDA_TOOL_SETTINGS(eda_timing_analysis)
 161 {
 162         EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF;
 163         EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF;
 164         EDA_MAINTAIN_DESIGN_HIERARCHY = OFF;
 165         EDA_WRITE_DEVICE_CONTROL_PORTS = OFF;
 166         EDA_GENERATE_FUNCTIONAL_NETLIST = OFF;
 167         EDA_FLATTEN_BUSES = OFF;
 168         EDA_MAP_ILLEGAL_CHARACTERS = OFF;
 169         EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF;
 170         EDA_RUN_TOOL_AUTOMATICALLY = OFF;
 171         EDA_OUTPUT_DATA_FORMAT = NONE;
 172         EDA_LAUNCH_CMD_LINE_TOOL = OFF;
 173         USE_GENERATED_PHYSICAL_CONSTRAINTS = ON;
 174         RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL;
 175         RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL;
 176         RESYNTHESIS_RETIMING = FULL;
 177 }
 178 EDA_TOOL_SETTINGS(eda_board_design)
 179 {
 180         EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF;
 181         EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF;
 182         EDA_MAINTAIN_DESIGN_HIERARCHY = OFF;
 183         EDA_WRITE_DEVICE_CONTROL_PORTS = OFF;
 184         EDA_GENERATE_FUNCTIONAL_NETLIST = OFF;
 185         EDA_FLATTEN_BUSES = OFF;
 186         EDA_MAP_ILLEGAL_CHARACTERS = OFF;
 187         EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF;
 188         EDA_RUN_TOOL_AUTOMATICALLY = OFF;
 189         EDA_OUTPUT_DATA_FORMAT = NONE;
 190         USE_GENERATED_PHYSICAL_CONSTRAINTS = ON;
 191         RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL;
 192         RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL;
 193         RESYNTHESIS_RETIMING = FULL;
 194 }
 195 EDA_TOOL_SETTINGS(eda_formal_verification)
 196 {
 197         EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF;
 198         EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF;
 199         EDA_MAINTAIN_DESIGN_HIERARCHY = OFF;
 200         EDA_WRITE_DEVICE_CONTROL_PORTS = OFF;
 201         EDA_GENERATE_FUNCTIONAL_NETLIST = OFF;
 202         EDA_FLATTEN_BUSES = OFF;
 203         EDA_MAP_ILLEGAL_CHARACTERS = OFF;
 204         EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF;
 205         EDA_RUN_TOOL_AUTOMATICALLY = OFF;
 206         EDA_OUTPUT_DATA_FORMAT = NONE;
 207         USE_GENERATED_PHYSICAL_CONSTRAINTS = ON;
 208         RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL;
 209         RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL;
 210         RESYNTHESIS_RETIMING = FULL;
 211 }
 212 EDA_TOOL_SETTINGS(eda_palace)
 213 {
 214         EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF;
 215         EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF;
 216         EDA_MAINTAIN_DESIGN_HIERARCHY = OFF;
 217         EDA_WRITE_DEVICE_CONTROL_PORTS = OFF;
 218         EDA_GENERATE_FUNCTIONAL_NETLIST = OFF;
 219         EDA_FLATTEN_BUSES = OFF;
 220         EDA_MAP_ILLEGAL_CHARACTERS = OFF;
 221         EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF;
 222         EDA_RUN_TOOL_AUTOMATICALLY = OFF;
 223         EDA_OUTPUT_DATA_FORMAT = NONE;
 224         RESYNTHESIS_RETIMING = FULL;
 225         RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL;
 226         RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL;
 227         USE_GENERATED_PHYSICAL_CONSTRAINTS = ON;
 228 }