Imported Upstream version 3.0
[debian/gnuradio] / usrp / fpga / toplevel / mrfm / mrfm.py
1 #!/usr/bin/env python
2 #
3 # This is mrfm_fft_sos.py
4 # Modification of Matt's mrfm_fft.py that reads filter coefs from file
5 #
6 # Copyright 2004,2005 Free Software Foundation, Inc.
7
8 # This file is part of GNU Radio
9
10 # GNU Radio is free software; you can redistribute it and/or modify
11 # it under the terms of the GNU General Public License as published by
12 # the Free Software Foundation; either version 2, or (at your option)
13 # any later version.
14
15 # GNU Radio is distributed in the hope that it will be useful,
16 # but WITHOUT ANY WARRANTY; without even the implied warranty of
17 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18 # GNU General Public License for more details.
19
20 # You should have received a copy of the GNU General Public License
21 # along with GNU Radio; see the file COPYING.  If not, write to
22 # the Free Software Foundation, Inc., 51 Franklin Street,
23 # Boston, MA 02110-1301, USA.
24
25
26 from gnuradio import gr, gru
27 from gnuradio import usrp
28
29 class source_c(usrp.source_c):
30     def __init__(self,fpga_filename):
31         usrp.source_c.__init__(self,which=0, decim_rate=64, nchan=2, mux=0x32103210, mode=0,
32                                fpga_filename=fpga_filename)
33
34         self._write_9862(0,2,0x80)  # Bypass ADC buffer, minimum gain
35         self._write_9862(0,3,0x80)  # Bypass ADC buffer, minimum gain
36
37         self._write_9862(0,8,0)   # TX PWR Down
38         self._write_9862(0,10,0)  # DAC offset
39         self._write_9862(0,11,0)  # DAC offset
40         self._write_9862(0,14,0x80)  # gain
41         self._write_9862(0,16,0xff)  # pga
42         self._write_9862(0,18,0x0c)  # TX IF
43         self._write_9862(0,19,0x01)  # TX Digital
44         self._write_9862(0,20,0x00)  # TX Mod
45
46         # max/min values are +/-2, so scale is set to make 2 = 32767 
47
48         self._write_fpga_reg(69,0x0e)   # debug mux
49         self._write_fpga_reg(5,-1)
50         self._write_fpga_reg(7,-1)
51         self._write_oe(0,0xffff, 0xffff)
52         self._write_oe(1,0xffff, 0xffff)
53         self._write_fpga_reg(14,0xf)
54
55         self.decim = None
56         
57     def set_coeffs(self,frac_bits,b20,b10,b00,a20,a10,b21,b11,b01,a21,a11):
58         def make_val(address,value):
59             return (address << 16) | (value & 0xffff)
60
61         # gain, scale already included in a's and b's from file
62
63         self._write_fpga_reg(67,make_val(1,b20))
64         self._write_fpga_reg(67,make_val(2,b10))
65         self._write_fpga_reg(67,make_val(3,b00))
66         self._write_fpga_reg(67,make_val(4,a20))
67         self._write_fpga_reg(67,make_val(5,a10))
68         
69         self._write_fpga_reg(67,make_val(7,b21))
70         self._write_fpga_reg(67,make_val(8,b11))
71         self._write_fpga_reg(67,make_val(9,b01))
72         self._write_fpga_reg(67,make_val(10,a21))
73         self._write_fpga_reg(67,make_val(11,a11))
74         
75         self._write_fpga_reg(68,frac_bits)   # Shift
76         
77         print "Biquad 0 : b2=%d b1=%d b0=%d a2=%d a1=%d" % (b20,b10,b00,a20,a10)
78         print "Biquad 1 : b2=%d b1=%d b0=%d a2=%d a1=%d" % (b21,b11,b01,a21,a11)
79
80     def set_decim_rate(self,rate=None):
81         i=2
82         turn=1
83         a=1
84         b=1
85         while (rate>1) and (i<257):
86             if (rate/i) * i == rate:
87                 if turn == 1:
88                     if a*i<257:
89                         a = a * i
90                         turn = 0
91                     elif b*i<257:
92                         b = b * i
93                         turn = 0
94                     else:
95                         print "Failed to set DECIMATOR"
96                         return self.decim
97                 elif b*i<257:
98                     b = b * i
99                     turn = 1
100                 elif a*i<257:
101                     a = a * i
102                     turn = 1
103                 else:
104                     print "Failed to set DECIMATOR"
105                     return self.decim
106                 rate=rate/i
107                 continue
108             i = i + 1
109         if rate > 1:
110             print "Failed to set DECIMATOR"
111             return self.decim
112         else:    
113             self.decim = a*b
114             print "a = %d  b = %d" % (a,b)
115             self._write_fpga_reg(64,(a-1)*256+(b-1))   # Set actual decimation
116
117     def decim_rate(self):
118         return self.decim
119     
120     def set_center_freq(self,freq):
121         self._write_fpga_reg(65,int(-freq/64e6*65536*65536))  # set center freq
122
123     def set_compensator(self,a11,a12,a21,a22,shift):
124         self._write_fpga_reg(70,a11)
125         self._write_fpga_reg(71,a12)
126         self._write_fpga_reg(72,a21)
127         self._write_fpga_reg(73,a22)
128         self._write_fpga_reg(74,shift)   # comp shift
129