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   1
   2
   3 module ram (input clock, input write,
   4             input [4:0] wr_addr, input [15:0] wr_data,
   5             input [4:0] rd_addr, output reg [15:0] rd_data);
   6
   7    reg [15:0]           ram_array [0:31];
   8
   9    always @(posedge clock)
  10      rd_data <= #1 ram_array[rd_addr];
  11
  12    always @(posedge clock)
  13      if(write)
  14        ram_array[wr_addr] <= #1 wr_data;
  15
  16 endmodule // ram