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   2
   3 module ram32_2sum (input clock, input write,
   4                    input [4:0] wr_addr, input [15:0] wr_data,
   5                    input [4:0] rd_addr1, input [4:0] rd_addr2,
   6                    output reg [15:0] sum);
   7
   8    reg [15:0]                   ram_array [0:31];
   9    wire [16:0]                  sum_int;
  10
  11    always @(posedge clock)
  12      if(write)
  13        ram_array[wr_addr] <= #1 wr_data;
  14
  15    assign sum_int = ram_array[rd_addr1] + ram_array[rd_addr2];
  16
  17    always @(posedge clock)
  18      sum <= #1 sum_int[16:1] + (sum_int[16]&sum_int[0]);
  19
  20
  21 endmodule // ram32_2sum
  22