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   1
   2
   3 module ram16_2sum (input clock, input write,
   4                    input [3:0] wr_addr, input [15:0] wr_data,
   5                    input [3:0] rd_addr1, input [3:0] rd_addr2,
   6                    output reg [15:0] sum);
   7
   8    reg signed [15:0]      ram_array [0:15];
   9    reg signed [15:0]      a,b;
  10    wire signed [16:0]     sum_int;
  11
  12    always @(posedge clock)
  13      if(write)
  14        ram_array[wr_addr] <= #1 wr_data;
  15
  16    always @(posedge clock)
  17      begin
  18         a <= #1 ram_array[rd_addr1];
  19         b <= #1 ram_array[rd_addr2];
  20      end
  21
  22    assign sum_int = {a[15],a} + {b[15],b};
  23
  24    always @(posedge clock)
  25      sum <= #1 sum_int[16:1] + (sum_int[16]&sum_int[0]);
  26
  27 endmodule // ram16_2sum