7 always #5 clock <= ~clock;
11 initial #1000 reset = 1'b0;
13 initial $dumpfile("test_hbd.vcd");
14 initial $dumpvars(0,test_hbd);
16 reg [15:0] i_in, q_in;
17 wire [15:0] i_out, q_out;
22 reg [15:0] coeff_data;
25 halfband_decim halfband_decim
26 ( .clock(clock),.reset(reset),.enable(),.strobe_in(strobe_in),.strobe_out(strobe_out),
27 .data_in(i_in),.data_out(i_out) );
29 always @(posedge strobe_out)
31 $display("-%d",65536-i_out);
50 initial #10000000 $finish; // Just in case...
55 repeat (40) @(posedge strobe_in);
59 repeat (40) @(posedge strobe_in);
63 repeat (40) @(posedge strobe_in);
65 repeat (40) @(posedge strobe_in);
67 repeat (41) @(posedge strobe_in);
69 repeat (40) @(posedge strobe_in);
71 repeat (40) @(posedge strobe_in);
72 repeat (7) @(posedge clock);