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   1 // -*- verilog -*-
   2 //
   3 //  USRP - Universal Software Radio Peripheral
   4 //
   5 //  Copyright (C) 2003 Matt Ettus
   6 //
   7 //  This program is free software; you can redistribute it and/or modify
   8 //  it under the terms of the GNU General Public License as published by
   9 //  the Free Software Foundation; either version 2 of the License, or
  10 //  (at your option) any later version.
  11 //
  12 //  This program is distributed in the hope that it will be useful,
  13 //  but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 //  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 //  GNU General Public License for more details.
  16 //
  17 //  You should have received a copy of the GNU General Public License
  18 //  along with this program; if not, write to the Free Software
  19 //  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
  20 //
  21
  22
  23 // Vendor Independent FIFO module
  24 // Width and Depth should be parameterizable
  25 // Asynchronous clocks for each side
  26 // Read side is read-acknowledge, not read-request
  27 // FIFO does not enforce "don't write when full, don't read when empty"
  28 // That is up to the connecting modules
  29 // The FIFO only holds 2^N-1 entries, not 2^N
  30
  31 module fifo (reset,data,write,wrclk,wr_used,q,read_ack,rdclk,rd_used);
  32    parameter width=32;
  33    parameter depth=10;
  34
  35    input reset;  // Asynchronous
  36    input [width-1:0] data;
  37    input write;
  38    input wrclk;
  39    output [depth-1:0] wr_used;
  40    output [width-1:0] q;
  41    input read_ack;
  42    input rdclk;
  43    output [depth-1:0] rd_used;
  44
  45    reg [depth-1:0] read_addr, write_addr,
  46                    read_addr_gray, read_addr_gray_sync,
  47                    write_addr_gray, write_addr_gray_sync;
  48
  49    // Pseudo-dual-port RAM
  50    dpram #(.depth(10),.width(width),.size(1024))
  51          fifo_ram (.wclk(wrclk),.wdata(data),.waddr(write_addr),.wen(write),
  52                    .rclk(rdclk), .rdata(q),.raddr(read_addr) );
  53
  54    wire [depth-1:0] wag,rag;
  55
  56    // Keep track of own side's pointer
  57    always @(posedge wrclk or posedge reset)
  58      if(reset) write_addr <= #1 0;
  59      else if(write) write_addr <= #1 write_addr + 1;
  60
  61    always @(posedge rdclk or posedge reset)
  62      if(reset) read_addr <= #1 0;
  63      else if(read_ack) read_addr <= #1 read_addr + 1;
  64
  65    // Convert own side pointer to gray
  66    bin2gray #(depth) write_b2g (write_addr,wag);
  67    bin2gray #(depth) read_b2g (read_addr,rag);
  68
  69    // Latch it
  70    always @(posedge wrclk or posedge reset)
  71      if(reset) write_addr_gray <= #1 0;
  72      else write_addr_gray <= #1 wag;
  73
  74    always @(posedge rdclk or posedge reset)
  75      if(reset) read_addr_gray <= #1 0;
  76      else read_addr_gray <= #1 rag;
  77
  78    // Send it to other side and latch
  79    always @(posedge wrclk or posedge reset)
  80      if(reset) read_addr_gray_sync <= #1 0;
  81      else read_addr_gray_sync <= #1 read_addr_gray;
  82
  83    always @(posedge rdclk or posedge reset)
  84      if(reset) write_addr_gray_sync <= #1 0;
  85      else write_addr_gray_sync <= #1 write_addr_gray;
  86
  87    wire [depth-1:0] write_addr_sync, read_addr_sync;
  88
  89    // Convert back to binary
  90    gray2bin #(depth) write_g2b (write_addr_gray_sync, write_addr_sync);
  91    gray2bin #(depth) read_g2b (read_addr_gray_sync, read_addr_sync);
  92
  93    assign rd_used = write_addr_sync - read_addr;
  94    assign wr_used = write_addr - read_addr_sync;
  95
  96 endmodule // fifo
  97
  98 module bin2gray(bin_val,gray_val);
  99    parameter width = 8;
 100    input [width-1:0] bin_val;
 101    output reg [width-1:0] gray_val;
 102
 103    integer i;
 104
 105    always @*
 106      begin
 107         gray_val[width-1] = bin_val[width-1];
 108         for(i=0;i<width-1;i=i+1)
 109           gray_val[i] = bin_val[i] ^ bin_val[i+1];
 110      end
 111 endmodule // bin2gray
 112
 113 module gray2bin(gray_val,bin_val);
 114    parameter width = 8;
 115    input [width-1:0] gray_val;
 116    output reg [width-1:0] bin_val;
 117
 118    integer i;
 119
 120    always @*
 121      begin
 122         bin_val[width-1] = gray_val[width-1];
 123         for(i=width-2;i>=0;i=i-1)
 124           bin_val[i] = bin_val[i+1] ^ gray_val[i];
 125      end
 126 endmodule // gray2bin