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   1 // -*- verilog -*-
   2 //
   3 //  USRP - Universal Software Radio Peripheral
   4 //
   5 //  Copyright (C) 2003 Matt Ettus
   6 //
   7 //  This program is free software; you can redistribute it and/or modify
   8 //  it under the terms of the GNU General Public License as published by
   9 //  the Free Software Foundation; either version 2 of the License, or
  10 //  (at your option) any later version.
  11 //
  12 //  This program is distributed in the hope that it will be useful,
  13 //  but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 //  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 //  GNU General Public License for more details.
  16 //
  17 //  You should have received a copy of the GNU General Public License
  18 //  along with this program; if not, write to the Free Software
  19 //  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
  20 //
  21
  22
  23 module cic_interp(clock,reset,enable,rate,strobe_in,strobe_out,signal_in,signal_out);
  24    parameter bw = 16;
  25    parameter N = 4;
  26    parameter log2_of_max_rate = 7;
  27    parameter maxbitgain = (N-1)*log2_of_max_rate;
  28
  29    input clock;
  30    input reset;
  31    input enable;
  32    input [7:0] rate;
  33    input strobe_in,strobe_out;
  34    input [bw-1:0] signal_in;
  35    wire [bw-1:0]        signal_in;
  36    output [bw-1:0] signal_out;
  37    wire [bw-1:0]   signal_out;
  38
  39    wire [bw+maxbitgain-1:0] signal_in_ext;
  40    reg [bw+maxbitgain-1:0] integrator [0:N-1];
  41    reg [bw+maxbitgain-1:0] differentiator [0:N-1];
  42    reg [bw+maxbitgain-1:0] pipeline [0:N-1];
  43
  44    integer i;
  45
  46    sign_extend #(bw,bw+maxbitgain)
  47       ext_input (.in(signal_in),.out(signal_in_ext));
  48
  49    //FIXME Note that this section has pipe and diff reversed
  50    // It still works, but is confusing
  51    always @(posedge clock)
  52      if(reset)
  53        for(i=0;i<N;i=i+1)
  54          integrator[i] <= #1 0;
  55      else if (enable & strobe_out)
  56        begin
  57           if(strobe_in)
  58             integrator[0] <= #1 integrator[0] + pipeline[N-1];
  59           for(i=1;i<N;i=i+1)
  60             integrator[i] <= #1 integrator[i] + integrator[i-1];
  61        end
  62
  63    always @(posedge clock)
  64      if(reset)
  65        begin
  66           for(i=0;i<N;i=i+1)
  67             begin
  68                differentiator[i] <= #1 0;
  69                pipeline[i] <= #1 0;
  70             end
  71        end
  72      else if (enable && strobe_in)
  73        begin
  74           differentiator[0] <= #1 signal_in_ext;
  75           pipeline[0] <= #1 signal_in_ext - differentiator[0];
  76           for(i=1;i<N;i=i+1)
  77             begin
  78                differentiator[i] <= #1 pipeline[i-1];
  79                pipeline[i] <= #1 pipeline[i-1] - differentiator[i];
  80             end
  81        end
  82
  83    wire [bw+maxbitgain-1:0] signal_out_unnorm = integrator[N-1];
  84
  85    cic_int_shifter cic_int_shifter(rate,signal_out_unnorm,signal_out);
  86
  87 endmodule // cic_interp
  88