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   1
   2 // Model of Pipelined [ZBT] Synchronous SRAM
   3
   4 module ssram(clock,addr,data,wen,ce);
   5    parameter addrbits = 19;
   6    parameter depth = 524288;
   7
   8    input clock;
   9    input [addrbits-1:0] addr;
  10    inout [35:0] data;
  11    input wen;
  12    input ce;
  13
  14    reg [35:0] ram [0:depth-1];
  15
  16    reg read_d1,read_d2;
  17    reg write_d1,write_d2;
  18    reg [addrbits-1:0] addr_d1,addr_d2;
  19
  20    always @(posedge clock)
  21      begin
  22         read_d1 <= #1 ce & ~wen;
  23         write_d1 <= #1 ce & wen;
  24         addr_d1 <= #1 addr;
  25         read_d2 <= #1 read_d1;
  26         write_d2 <= #1 write_d1;
  27         addr_d2 <= #1 addr_d1;
  28         if(write_d2)
  29           ram[addr_d2] = data;
  30      end // always @ (posedge clock)
  31
  32    data = (ce & read_d2) ? ram[addr_d2] : 36'bz;
  33
  34    always @(posedge clock)
  35      if(~ce & (write_d2 | write_d1 | wen))
  36        $display("$time ERROR:  RAM CE not asserted during write cycle");
  37
  38 endmodule // ssram