git.gag.com Git - debian/gnuradio/blob - usrp/fpga/megacells/sub32.v

   1 // megafunction wizard: %LPM_ADD_SUB%CBX%
   2 // GENERATION: STANDARD
   3 // VERSION: WM1.0
   4 // MODULE: lpm_add_sub
   5
   6 // ============================================================
   7 // File Name: sub32.v
   8 // Megafunction Name(s):
   9 //                      lpm_add_sub
  10 // ============================================================
  11 // ************************************************************
  12 // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
  13 // ************************************************************
  14
  15
  16 //Copyright (C) 1991-2003 Altera Corporation
  17 //Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
  18 //support information,  device programming or simulation file,  and any other
  19 //associated  documentation or information  provided by  Altera  or a partner
  20 //under  Altera's   Megafunction   Partnership   Program  may  be  used  only
  21 //to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
  22 //other  use  of such  megafunction  design,  netlist,  support  information,
  23 //device programming or simulation file,  or any other  related documentation
  24 //or information  is prohibited  for  any  other purpose,  including, but not
  25 //limited to  modification,  reverse engineering,  de-compiling, or use  with
  26 //any other  silicon devices,  unless such use is  explicitly  licensed under
  27 //a separate agreement with  Altera  or a megafunction partner.  Title to the
  28 //intellectual property,  including patents,  copyrights,  trademarks,  trade
  29 //secrets,  or maskworks,  embodied in any such megafunction design, netlist,
  30 //support  information,  device programming or simulation file,  or any other
  31 //related documentation or information provided by  Altera  or a megafunction
  32 //partner, remains with Altera, the megafunction partner, or their respective
  33 //licensors. No other licenses, including any licenses needed under any third
  34 //party's intellectual property, are provided herein.
  35
  36
  37 //lpm_add_sub DEVICE_FAMILY=Cyclone LPM_DIRECTION=SUB LPM_PIPELINE=1 LPM_WIDTH=32 aclr clken clock dataa datab result
  38 //VERSION_BEGIN 3.0 cbx_lpm_add_sub 2003:04:10:18:28:42:SJ cbx_mgl 2003:06:11:11:00:44:SJ cbx_stratix 2003:05:16:10:26:50:SJ  VERSION_END
  39
  40 //synthesis_resources = lut 32
  41 module  sub32_add_sub_cqa
  42         (
  43         aclr,
  44         clken,
  45         clock,
  46         dataa,
  47         datab,
  48         result) /* synthesis synthesis_clearbox=1 */;
  49         input   aclr;
  50         input   clken;
  51         input   clock;
  52         input   [31:0]  dataa;
  53         input   [31:0]  datab;
  54         output   [31:0]  result;
  55
  56         wire  [0:0]   wire_add_sub_cella_0cout;
  57         wire  [0:0]   wire_add_sub_cella_1cout;
  58         wire  [0:0]   wire_add_sub_cella_2cout;
  59         wire  [0:0]   wire_add_sub_cella_3cout;
  60         wire  [0:0]   wire_add_sub_cella_4cout;
  61         wire  [0:0]   wire_add_sub_cella_5cout;
  62         wire  [0:0]   wire_add_sub_cella_6cout;
  63         wire  [0:0]   wire_add_sub_cella_7cout;
  64         wire  [0:0]   wire_add_sub_cella_8cout;
  65         wire  [0:0]   wire_add_sub_cella_9cout;
  66         wire  [0:0]   wire_add_sub_cella_10cout;
  67         wire  [0:0]   wire_add_sub_cella_11cout;
  68         wire  [0:0]   wire_add_sub_cella_12cout;
  69         wire  [0:0]   wire_add_sub_cella_13cout;
  70         wire  [0:0]   wire_add_sub_cella_14cout;
  71         wire  [0:0]   wire_add_sub_cella_15cout;
  72         wire  [0:0]   wire_add_sub_cella_16cout;
  73         wire  [0:0]   wire_add_sub_cella_17cout;
  74         wire  [0:0]   wire_add_sub_cella_18cout;
  75         wire  [0:0]   wire_add_sub_cella_19cout;
  76         wire  [0:0]   wire_add_sub_cella_20cout;
  77         wire  [0:0]   wire_add_sub_cella_21cout;
  78         wire  [0:0]   wire_add_sub_cella_22cout;
  79         wire  [0:0]   wire_add_sub_cella_23cout;
  80         wire  [0:0]   wire_add_sub_cella_24cout;
  81         wire  [0:0]   wire_add_sub_cella_25cout;
  82         wire  [0:0]   wire_add_sub_cella_26cout;
  83         wire  [0:0]   wire_add_sub_cella_27cout;
  84         wire  [0:0]   wire_add_sub_cella_28cout;
  85         wire  [0:0]   wire_add_sub_cella_29cout;
  86         wire  [0:0]   wire_add_sub_cella_30cout;
  87         wire  [31:0]   wire_add_sub_cella_dataa;
  88         wire  [31:0]   wire_add_sub_cella_datab;
  89         wire  [31:0]   wire_add_sub_cella_regout;
  90
  91         stratix_lcell   add_sub_cella_0
  92         (
  93         .aclr(aclr),
  94         .cin(1'b1),
  95         .clk(clock),
  96         .cout(wire_add_sub_cella_0cout[0:0]),
  97         .dataa(wire_add_sub_cella_dataa[0:0]),
  98         .datab(wire_add_sub_cella_datab[0:0]),
  99         .ena(clken),
 100         .regout(wire_add_sub_cella_regout[0:0]));
 101         defparam
 102                 add_sub_cella_0.cin_used = "true",
 103                 add_sub_cella_0.lut_mask = "69b2",
 104                 add_sub_cella_0.operation_mode = "arithmetic",
 105                 add_sub_cella_0.sum_lutc_input = "cin",
 106                 add_sub_cella_0.lpm_type = "stratix_lcell";
 107         stratix_lcell   add_sub_cella_1
 108         (
 109         .aclr(aclr),
 110         .cin(wire_add_sub_cella_0cout[0:0]),
 111         .clk(clock),
 112         .cout(wire_add_sub_cella_1cout[0:0]),
 113         .dataa(wire_add_sub_cella_dataa[1:1]),
 114         .datab(wire_add_sub_cella_datab[1:1]),
 115         .ena(clken),
 116         .regout(wire_add_sub_cella_regout[1:1]));
 117         defparam
 118                 add_sub_cella_1.cin_used = "true",
 119                 add_sub_cella_1.lut_mask = "69b2",
 120                 add_sub_cella_1.operation_mode = "arithmetic",
 121                 add_sub_cella_1.sum_lutc_input = "cin",
 122                 add_sub_cella_1.lpm_type = "stratix_lcell";
 123         stratix_lcell   add_sub_cella_2
 124         (
 125         .aclr(aclr),
 126         .cin(wire_add_sub_cella_1cout[0:0]),
 127         .clk(clock),
 128         .cout(wire_add_sub_cella_2cout[0:0]),
 129         .dataa(wire_add_sub_cella_dataa[2:2]),
 130         .datab(wire_add_sub_cella_datab[2:2]),
 131         .ena(clken),
 132         .regout(wire_add_sub_cella_regout[2:2]));
 133         defparam
 134                 add_sub_cella_2.cin_used = "true",
 135                 add_sub_cella_2.lut_mask = "69b2",
 136                 add_sub_cella_2.operation_mode = "arithmetic",
 137                 add_sub_cella_2.sum_lutc_input = "cin",
 138                 add_sub_cella_2.lpm_type = "stratix_lcell";
 139         stratix_lcell   add_sub_cella_3
 140         (
 141         .aclr(aclr),
 142         .cin(wire_add_sub_cella_2cout[0:0]),
 143         .clk(clock),
 144         .cout(wire_add_sub_cella_3cout[0:0]),
 145         .dataa(wire_add_sub_cella_dataa[3:3]),
 146         .datab(wire_add_sub_cella_datab[3:3]),
 147         .ena(clken),
 148         .regout(wire_add_sub_cella_regout[3:3]));
 149         defparam
 150                 add_sub_cella_3.cin_used = "true",
 151                 add_sub_cella_3.lut_mask = "69b2",
 152                 add_sub_cella_3.operation_mode = "arithmetic",
 153                 add_sub_cella_3.sum_lutc_input = "cin",
 154                 add_sub_cella_3.lpm_type = "stratix_lcell";
 155         stratix_lcell   add_sub_cella_4
 156         (
 157         .aclr(aclr),
 158         .cin(wire_add_sub_cella_3cout[0:0]),
 159         .clk(clock),
 160         .cout(wire_add_sub_cella_4cout[0:0]),
 161         .dataa(wire_add_sub_cella_dataa[4:4]),
 162         .datab(wire_add_sub_cella_datab[4:4]),
 163         .ena(clken),
 164         .regout(wire_add_sub_cella_regout[4:4]));
 165         defparam
 166                 add_sub_cella_4.cin_used = "true",
 167                 add_sub_cella_4.lut_mask = "69b2",
 168                 add_sub_cella_4.operation_mode = "arithmetic",
 169                 add_sub_cella_4.sum_lutc_input = "cin",
 170                 add_sub_cella_4.lpm_type = "stratix_lcell";
 171         stratix_lcell   add_sub_cella_5
 172         (
 173         .aclr(aclr),
 174         .cin(wire_add_sub_cella_4cout[0:0]),
 175         .clk(clock),
 176         .cout(wire_add_sub_cella_5cout[0:0]),
 177         .dataa(wire_add_sub_cella_dataa[5:5]),
 178         .datab(wire_add_sub_cella_datab[5:5]),
 179         .ena(clken),
 180         .regout(wire_add_sub_cella_regout[5:5]));
 181         defparam
 182                 add_sub_cella_5.cin_used = "true",
 183                 add_sub_cella_5.lut_mask = "69b2",
 184                 add_sub_cella_5.operation_mode = "arithmetic",
 185                 add_sub_cella_5.sum_lutc_input = "cin",
 186                 add_sub_cella_5.lpm_type = "stratix_lcell";
 187         stratix_lcell   add_sub_cella_6
 188         (
 189         .aclr(aclr),
 190         .cin(wire_add_sub_cella_5cout[0:0]),
 191         .clk(clock),
 192         .cout(wire_add_sub_cella_6cout[0:0]),
 193         .dataa(wire_add_sub_cella_dataa[6:6]),
 194         .datab(wire_add_sub_cella_datab[6:6]),
 195         .ena(clken),
 196         .regout(wire_add_sub_cella_regout[6:6]));
 197         defparam
 198                 add_sub_cella_6.cin_used = "true",
 199                 add_sub_cella_6.lut_mask = "69b2",
 200                 add_sub_cella_6.operation_mode = "arithmetic",
 201                 add_sub_cella_6.sum_lutc_input = "cin",
 202                 add_sub_cella_6.lpm_type = "stratix_lcell";
 203         stratix_lcell   add_sub_cella_7
 204         (
 205         .aclr(aclr),
 206         .cin(wire_add_sub_cella_6cout[0:0]),
 207         .clk(clock),
 208         .cout(wire_add_sub_cella_7cout[0:0]),
 209         .dataa(wire_add_sub_cella_dataa[7:7]),
 210         .datab(wire_add_sub_cella_datab[7:7]),
 211         .ena(clken),
 212         .regout(wire_add_sub_cella_regout[7:7]));
 213         defparam
 214                 add_sub_cella_7.cin_used = "true",
 215                 add_sub_cella_7.lut_mask = "69b2",
 216                 add_sub_cella_7.operation_mode = "arithmetic",
 217                 add_sub_cella_7.sum_lutc_input = "cin",
 218                 add_sub_cella_7.lpm_type = "stratix_lcell";
 219         stratix_lcell   add_sub_cella_8
 220         (
 221         .aclr(aclr),
 222         .cin(wire_add_sub_cella_7cout[0:0]),
 223         .clk(clock),
 224         .cout(wire_add_sub_cella_8cout[0:0]),
 225         .dataa(wire_add_sub_cella_dataa[8:8]),
 226         .datab(wire_add_sub_cella_datab[8:8]),
 227         .ena(clken),
 228         .regout(wire_add_sub_cella_regout[8:8]));
 229         defparam
 230                 add_sub_cella_8.cin_used = "true",
 231                 add_sub_cella_8.lut_mask = "69b2",
 232                 add_sub_cella_8.operation_mode = "arithmetic",
 233                 add_sub_cella_8.sum_lutc_input = "cin",
 234                 add_sub_cella_8.lpm_type = "stratix_lcell";
 235         stratix_lcell   add_sub_cella_9
 236         (
 237         .aclr(aclr),
 238         .cin(wire_add_sub_cella_8cout[0:0]),
 239         .clk(clock),
 240         .cout(wire_add_sub_cella_9cout[0:0]),
 241         .dataa(wire_add_sub_cella_dataa[9:9]),
 242         .datab(wire_add_sub_cella_datab[9:9]),
 243         .ena(clken),
 244         .regout(wire_add_sub_cella_regout[9:9]));
 245         defparam
 246                 add_sub_cella_9.cin_used = "true",
 247                 add_sub_cella_9.lut_mask = "69b2",
 248                 add_sub_cella_9.operation_mode = "arithmetic",
 249                 add_sub_cella_9.sum_lutc_input = "cin",
 250                 add_sub_cella_9.lpm_type = "stratix_lcell";
 251         stratix_lcell   add_sub_cella_10
 252         (
 253         .aclr(aclr),
 254         .cin(wire_add_sub_cella_9cout[0:0]),
 255         .clk(clock),
 256         .cout(wire_add_sub_cella_10cout[0:0]),
 257         .dataa(wire_add_sub_cella_dataa[10:10]),
 258         .datab(wire_add_sub_cella_datab[10:10]),
 259         .ena(clken),
 260         .regout(wire_add_sub_cella_regout[10:10]));
 261         defparam
 262                 add_sub_cella_10.cin_used = "true",
 263                 add_sub_cella_10.lut_mask = "69b2",
 264                 add_sub_cella_10.operation_mode = "arithmetic",
 265                 add_sub_cella_10.sum_lutc_input = "cin",
 266                 add_sub_cella_10.lpm_type = "stratix_lcell";
 267         stratix_lcell   add_sub_cella_11
 268         (
 269         .aclr(aclr),
 270         .cin(wire_add_sub_cella_10cout[0:0]),
 271         .clk(clock),
 272         .cout(wire_add_sub_cella_11cout[0:0]),
 273         .dataa(wire_add_sub_cella_dataa[11:11]),
 274         .datab(wire_add_sub_cella_datab[11:11]),
 275         .ena(clken),
 276         .regout(wire_add_sub_cella_regout[11:11]));
 277         defparam
 278                 add_sub_cella_11.cin_used = "true",
 279                 add_sub_cella_11.lut_mask = "69b2",
 280                 add_sub_cella_11.operation_mode = "arithmetic",
 281                 add_sub_cella_11.sum_lutc_input = "cin",
 282                 add_sub_cella_11.lpm_type = "stratix_lcell";
 283         stratix_lcell   add_sub_cella_12
 284         (
 285         .aclr(aclr),
 286         .cin(wire_add_sub_cella_11cout[0:0]),
 287         .clk(clock),
 288         .cout(wire_add_sub_cella_12cout[0:0]),
 289         .dataa(wire_add_sub_cella_dataa[12:12]),
 290         .datab(wire_add_sub_cella_datab[12:12]),
 291         .ena(clken),
 292         .regout(wire_add_sub_cella_regout[12:12]));
 293         defparam
 294                 add_sub_cella_12.cin_used = "true",
 295                 add_sub_cella_12.lut_mask = "69b2",
 296                 add_sub_cella_12.operation_mode = "arithmetic",
 297                 add_sub_cella_12.sum_lutc_input = "cin",
 298                 add_sub_cella_12.lpm_type = "stratix_lcell";
 299         stratix_lcell   add_sub_cella_13
 300         (
 301         .aclr(aclr),
 302         .cin(wire_add_sub_cella_12cout[0:0]),
 303         .clk(clock),
 304         .cout(wire_add_sub_cella_13cout[0:0]),
 305         .dataa(wire_add_sub_cella_dataa[13:13]),
 306         .datab(wire_add_sub_cella_datab[13:13]),
 307         .ena(clken),
 308         .regout(wire_add_sub_cella_regout[13:13]));
 309         defparam
 310                 add_sub_cella_13.cin_used = "true",
 311                 add_sub_cella_13.lut_mask = "69b2",
 312                 add_sub_cella_13.operation_mode = "arithmetic",
 313                 add_sub_cella_13.sum_lutc_input = "cin",
 314                 add_sub_cella_13.lpm_type = "stratix_lcell";
 315         stratix_lcell   add_sub_cella_14
 316         (
 317         .aclr(aclr),
 318         .cin(wire_add_sub_cella_13cout[0:0]),
 319         .clk(clock),
 320         .cout(wire_add_sub_cella_14cout[0:0]),
 321         .dataa(wire_add_sub_cella_dataa[14:14]),
 322         .datab(wire_add_sub_cella_datab[14:14]),
 323         .ena(clken),
 324         .regout(wire_add_sub_cella_regout[14:14]));
 325         defparam
 326                 add_sub_cella_14.cin_used = "true",
 327                 add_sub_cella_14.lut_mask = "69b2",
 328                 add_sub_cella_14.operation_mode = "arithmetic",
 329                 add_sub_cella_14.sum_lutc_input = "cin",
 330                 add_sub_cella_14.lpm_type = "stratix_lcell";
 331         stratix_lcell   add_sub_cella_15
 332         (
 333         .aclr(aclr),
 334         .cin(wire_add_sub_cella_14cout[0:0]),
 335         .clk(clock),
 336         .cout(wire_add_sub_cella_15cout[0:0]),
 337         .dataa(wire_add_sub_cella_dataa[15:15]),
 338         .datab(wire_add_sub_cella_datab[15:15]),
 339         .ena(clken),
 340         .regout(wire_add_sub_cella_regout[15:15]));
 341         defparam
 342                 add_sub_cella_15.cin_used = "true",
 343                 add_sub_cella_15.lut_mask = "69b2",
 344                 add_sub_cella_15.operation_mode = "arithmetic",
 345                 add_sub_cella_15.sum_lutc_input = "cin",
 346                 add_sub_cella_15.lpm_type = "stratix_lcell";
 347         stratix_lcell   add_sub_cella_16
 348         (
 349         .aclr(aclr),
 350         .cin(wire_add_sub_cella_15cout[0:0]),
 351         .clk(clock),
 352         .cout(wire_add_sub_cella_16cout[0:0]),
 353         .dataa(wire_add_sub_cella_dataa[16:16]),
 354         .datab(wire_add_sub_cella_datab[16:16]),
 355         .ena(clken),
 356         .regout(wire_add_sub_cella_regout[16:16]));
 357         defparam
 358                 add_sub_cella_16.cin_used = "true",
 359                 add_sub_cella_16.lut_mask = "69b2",
 360                 add_sub_cella_16.operation_mode = "arithmetic",
 361                 add_sub_cella_16.sum_lutc_input = "cin",
 362                 add_sub_cella_16.lpm_type = "stratix_lcell";
 363         stratix_lcell   add_sub_cella_17
 364         (
 365         .aclr(aclr),
 366         .cin(wire_add_sub_cella_16cout[0:0]),
 367         .clk(clock),
 368         .cout(wire_add_sub_cella_17cout[0:0]),
 369         .dataa(wire_add_sub_cella_dataa[17:17]),
 370         .datab(wire_add_sub_cella_datab[17:17]),
 371         .ena(clken),
 372         .regout(wire_add_sub_cella_regout[17:17]));
 373         defparam
 374                 add_sub_cella_17.cin_used = "true",
 375                 add_sub_cella_17.lut_mask = "69b2",
 376                 add_sub_cella_17.operation_mode = "arithmetic",
 377                 add_sub_cella_17.sum_lutc_input = "cin",
 378                 add_sub_cella_17.lpm_type = "stratix_lcell";
 379         stratix_lcell   add_sub_cella_18
 380         (
 381         .aclr(aclr),
 382         .cin(wire_add_sub_cella_17cout[0:0]),
 383         .clk(clock),
 384         .cout(wire_add_sub_cella_18cout[0:0]),
 385         .dataa(wire_add_sub_cella_dataa[18:18]),
 386         .datab(wire_add_sub_cella_datab[18:18]),
 387         .ena(clken),
 388         .regout(wire_add_sub_cella_regout[18:18]));
 389         defparam
 390                 add_sub_cella_18.cin_used = "true",
 391                 add_sub_cella_18.lut_mask = "69b2",
 392                 add_sub_cella_18.operation_mode = "arithmetic",
 393                 add_sub_cella_18.sum_lutc_input = "cin",
 394                 add_sub_cella_18.lpm_type = "stratix_lcell";
 395         stratix_lcell   add_sub_cella_19
 396         (
 397         .aclr(aclr),
 398         .cin(wire_add_sub_cella_18cout[0:0]),
 399         .clk(clock),
 400         .cout(wire_add_sub_cella_19cout[0:0]),
 401         .dataa(wire_add_sub_cella_dataa[19:19]),
 402         .datab(wire_add_sub_cella_datab[19:19]),
 403         .ena(clken),
 404         .regout(wire_add_sub_cella_regout[19:19]));
 405         defparam
 406                 add_sub_cella_19.cin_used = "true",
 407                 add_sub_cella_19.lut_mask = "69b2",
 408                 add_sub_cella_19.operation_mode = "arithmetic",
 409                 add_sub_cella_19.sum_lutc_input = "cin",
 410                 add_sub_cella_19.lpm_type = "stratix_lcell";
 411         stratix_lcell   add_sub_cella_20
 412         (
 413         .aclr(aclr),
 414         .cin(wire_add_sub_cella_19cout[0:0]),
 415         .clk(clock),
 416         .cout(wire_add_sub_cella_20cout[0:0]),
 417         .dataa(wire_add_sub_cella_dataa[20:20]),
 418         .datab(wire_add_sub_cella_datab[20:20]),
 419         .ena(clken),
 420         .regout(wire_add_sub_cella_regout[20:20]));
 421         defparam
 422                 add_sub_cella_20.cin_used = "true",
 423                 add_sub_cella_20.lut_mask = "69b2",
 424                 add_sub_cella_20.operation_mode = "arithmetic",
 425                 add_sub_cella_20.sum_lutc_input = "cin",
 426                 add_sub_cella_20.lpm_type = "stratix_lcell";
 427         stratix_lcell   add_sub_cella_21
 428         (
 429         .aclr(aclr),
 430         .cin(wire_add_sub_cella_20cout[0:0]),
 431         .clk(clock),
 432         .cout(wire_add_sub_cella_21cout[0:0]),
 433         .dataa(wire_add_sub_cella_dataa[21:21]),
 434         .datab(wire_add_sub_cella_datab[21:21]),
 435         .ena(clken),
 436         .regout(wire_add_sub_cella_regout[21:21]));
 437         defparam
 438                 add_sub_cella_21.cin_used = "true",
 439                 add_sub_cella_21.lut_mask = "69b2",
 440                 add_sub_cella_21.operation_mode = "arithmetic",
 441                 add_sub_cella_21.sum_lutc_input = "cin",
 442                 add_sub_cella_21.lpm_type = "stratix_lcell";
 443         stratix_lcell   add_sub_cella_22
 444         (
 445         .aclr(aclr),
 446         .cin(wire_add_sub_cella_21cout[0:0]),
 447         .clk(clock),
 448         .cout(wire_add_sub_cella_22cout[0:0]),
 449         .dataa(wire_add_sub_cella_dataa[22:22]),
 450         .datab(wire_add_sub_cella_datab[22:22]),
 451         .ena(clken),
 452         .regout(wire_add_sub_cella_regout[22:22]));
 453         defparam
 454                 add_sub_cella_22.cin_used = "true",
 455                 add_sub_cella_22.lut_mask = "69b2",
 456                 add_sub_cella_22.operation_mode = "arithmetic",
 457                 add_sub_cella_22.sum_lutc_input = "cin",
 458                 add_sub_cella_22.lpm_type = "stratix_lcell";
 459         stratix_lcell   add_sub_cella_23
 460         (
 461         .aclr(aclr),
 462         .cin(wire_add_sub_cella_22cout[0:0]),
 463         .clk(clock),
 464         .cout(wire_add_sub_cella_23cout[0:0]),
 465         .dataa(wire_add_sub_cella_dataa[23:23]),
 466         .datab(wire_add_sub_cella_datab[23:23]),
 467         .ena(clken),
 468         .regout(wire_add_sub_cella_regout[23:23]));
 469         defparam
 470                 add_sub_cella_23.cin_used = "true",
 471                 add_sub_cella_23.lut_mask = "69b2",
 472                 add_sub_cella_23.operation_mode = "arithmetic",
 473                 add_sub_cella_23.sum_lutc_input = "cin",
 474                 add_sub_cella_23.lpm_type = "stratix_lcell";
 475         stratix_lcell   add_sub_cella_24
 476         (
 477         .aclr(aclr),
 478         .cin(wire_add_sub_cella_23cout[0:0]),
 479         .clk(clock),
 480         .cout(wire_add_sub_cella_24cout[0:0]),
 481         .dataa(wire_add_sub_cella_dataa[24:24]),
 482         .datab(wire_add_sub_cella_datab[24:24]),
 483         .ena(clken),
 484         .regout(wire_add_sub_cella_regout[24:24]));
 485         defparam
 486                 add_sub_cella_24.cin_used = "true",
 487                 add_sub_cella_24.lut_mask = "69b2",
 488                 add_sub_cella_24.operation_mode = "arithmetic",
 489                 add_sub_cella_24.sum_lutc_input = "cin",
 490                 add_sub_cella_24.lpm_type = "stratix_lcell";
 491         stratix_lcell   add_sub_cella_25
 492         (
 493         .aclr(aclr),
 494         .cin(wire_add_sub_cella_24cout[0:0]),
 495         .clk(clock),
 496         .cout(wire_add_sub_cella_25cout[0:0]),
 497         .dataa(wire_add_sub_cella_dataa[25:25]),
 498         .datab(wire_add_sub_cella_datab[25:25]),
 499         .ena(clken),
 500         .regout(wire_add_sub_cella_regout[25:25]));
 501         defparam
 502                 add_sub_cella_25.cin_used = "true",
 503                 add_sub_cella_25.lut_mask = "69b2",
 504                 add_sub_cella_25.operation_mode = "arithmetic",
 505                 add_sub_cella_25.sum_lutc_input = "cin",
 506                 add_sub_cella_25.lpm_type = "stratix_lcell";
 507         stratix_lcell   add_sub_cella_26
 508         (
 509         .aclr(aclr),
 510         .cin(wire_add_sub_cella_25cout[0:0]),
 511         .clk(clock),
 512         .cout(wire_add_sub_cella_26cout[0:0]),
 513         .dataa(wire_add_sub_cella_dataa[26:26]),
 514         .datab(wire_add_sub_cella_datab[26:26]),
 515         .ena(clken),
 516         .regout(wire_add_sub_cella_regout[26:26]));
 517         defparam
 518                 add_sub_cella_26.cin_used = "true",
 519                 add_sub_cella_26.lut_mask = "69b2",
 520                 add_sub_cella_26.operation_mode = "arithmetic",
 521                 add_sub_cella_26.sum_lutc_input = "cin",
 522                 add_sub_cella_26.lpm_type = "stratix_lcell";
 523         stratix_lcell   add_sub_cella_27
 524         (
 525         .aclr(aclr),
 526         .cin(wire_add_sub_cella_26cout[0:0]),
 527         .clk(clock),
 528         .cout(wire_add_sub_cella_27cout[0:0]),
 529         .dataa(wire_add_sub_cella_dataa[27:27]),
 530         .datab(wire_add_sub_cella_datab[27:27]),
 531         .ena(clken),
 532         .regout(wire_add_sub_cella_regout[27:27]));
 533         defparam
 534                 add_sub_cella_27.cin_used = "true",
 535                 add_sub_cella_27.lut_mask = "69b2",
 536                 add_sub_cella_27.operation_mode = "arithmetic",
 537                 add_sub_cella_27.sum_lutc_input = "cin",
 538                 add_sub_cella_27.lpm_type = "stratix_lcell";
 539         stratix_lcell   add_sub_cella_28
 540         (
 541         .aclr(aclr),
 542         .cin(wire_add_sub_cella_27cout[0:0]),
 543         .clk(clock),
 544         .cout(wire_add_sub_cella_28cout[0:0]),
 545         .dataa(wire_add_sub_cella_dataa[28:28]),
 546         .datab(wire_add_sub_cella_datab[28:28]),
 547         .ena(clken),
 548         .regout(wire_add_sub_cella_regout[28:28]));
 549         defparam
 550                 add_sub_cella_28.cin_used = "true",
 551                 add_sub_cella_28.lut_mask = "69b2",
 552                 add_sub_cella_28.operation_mode = "arithmetic",
 553                 add_sub_cella_28.sum_lutc_input = "cin",
 554                 add_sub_cella_28.lpm_type = "stratix_lcell";
 555         stratix_lcell   add_sub_cella_29
 556         (
 557         .aclr(aclr),
 558         .cin(wire_add_sub_cella_28cout[0:0]),
 559         .clk(clock),
 560         .cout(wire_add_sub_cella_29cout[0:0]),
 561         .dataa(wire_add_sub_cella_dataa[29:29]),
 562         .datab(wire_add_sub_cella_datab[29:29]),
 563         .ena(clken),
 564         .regout(wire_add_sub_cella_regout[29:29]));
 565         defparam
 566                 add_sub_cella_29.cin_used = "true",
 567                 add_sub_cella_29.lut_mask = "69b2",
 568                 add_sub_cella_29.operation_mode = "arithmetic",
 569                 add_sub_cella_29.sum_lutc_input = "cin",
 570                 add_sub_cella_29.lpm_type = "stratix_lcell";
 571         stratix_lcell   add_sub_cella_30
 572         (
 573         .aclr(aclr),
 574         .cin(wire_add_sub_cella_29cout[0:0]),
 575         .clk(clock),
 576         .cout(wire_add_sub_cella_30cout[0:0]),
 577         .dataa(wire_add_sub_cella_dataa[30:30]),
 578         .datab(wire_add_sub_cella_datab[30:30]),
 579         .ena(clken),
 580         .regout(wire_add_sub_cella_regout[30:30]));
 581         defparam
 582                 add_sub_cella_30.cin_used = "true",
 583                 add_sub_cella_30.lut_mask = "69b2",
 584                 add_sub_cella_30.operation_mode = "arithmetic",
 585                 add_sub_cella_30.sum_lutc_input = "cin",
 586                 add_sub_cella_30.lpm_type = "stratix_lcell";
 587         stratix_lcell   add_sub_cella_31
 588         (
 589         .aclr(aclr),
 590         .cin(wire_add_sub_cella_30cout[0:0]),
 591         .clk(clock),
 592         .dataa(wire_add_sub_cella_dataa[31:31]),
 593         .datab(wire_add_sub_cella_datab[31:31]),
 594         .ena(clken),
 595         .regout(wire_add_sub_cella_regout[31:31]));
 596         defparam
 597                 add_sub_cella_31.cin_used = "true",
 598                 add_sub_cella_31.lut_mask = "6969",
 599                 add_sub_cella_31.operation_mode = "normal",
 600                 add_sub_cella_31.sum_lutc_input = "cin",
 601                 add_sub_cella_31.lpm_type = "stratix_lcell";
 602         assign
 603                 wire_add_sub_cella_dataa = dataa,
 604                 wire_add_sub_cella_datab = datab;
 605         assign
 606                 result = wire_add_sub_cella_regout;
 607 endmodule //sub32_add_sub_cqa
 608 //VALID FILE
 609
 610
 611 module sub32 (
 612         dataa,
 613         datab,
 614         clock,
 615         aclr,
 616         clken,
 617         result)/* synthesis synthesis_clearbox = 1 */;
 618
 619         input   [31:0]  dataa;
 620         input   [31:0]  datab;
 621         input     clock;
 622         input     aclr;
 623         input     clken;
 624         output  [31:0]  result;
 625
 626         wire [31:0] sub_wire0;
 627         wire [31:0] result = sub_wire0[31:0];
 628
 629         sub32_add_sub_cqa       sub32_add_sub_cqa_component (
 630                                 .dataa (dataa),
 631                                 .datab (datab),
 632                                 .clken (clken),
 633                                 .aclr (aclr),
 634                                 .clock (clock),
 635                                 .result (sub_wire0));
 636
 637 endmodule
 638
 639 // ============================================================
 640 // CNX file retrieval info
 641 // ============================================================
 642 // Retrieval info: PRIVATE: nBit NUMERIC "32"
 643 // Retrieval info: PRIVATE: Function NUMERIC "1"
 644 // Retrieval info: PRIVATE: WhichConstant NUMERIC "0"
 645 // Retrieval info: PRIVATE: ConstantA NUMERIC "0"
 646 // Retrieval info: PRIVATE: ConstantB NUMERIC "0"
 647 // Retrieval info: PRIVATE: ValidCtA NUMERIC "0"
 648 // Retrieval info: PRIVATE: ValidCtB NUMERIC "0"
 649 // Retrieval info: PRIVATE: CarryIn NUMERIC "0"
 650 // Retrieval info: PRIVATE: CarryOut NUMERIC "0"
 651 // Retrieval info: PRIVATE: Overflow NUMERIC "0"
 652 // Retrieval info: PRIVATE: Latency NUMERIC "1"
 653 // Retrieval info: PRIVATE: aclr NUMERIC "1"
 654 // Retrieval info: PRIVATE: clken NUMERIC "1"
 655 // Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1"
 656 // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
 657 // Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
 658 // Retrieval info: CONSTANT: LPM_DIRECTION STRING "SUB"
 659 // Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB"
 660 // Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO"
 661 // Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
 662 // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
 663 // Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL result[31..0]
 664 // Retrieval info: USED_PORT: dataa 0 0 32 0 INPUT NODEFVAL dataa[31..0]
 665 // Retrieval info: USED_PORT: datab 0 0 32 0 INPUT NODEFVAL datab[31..0]
 666 // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
 667 // Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
 668 // Retrieval info: USED_PORT: clken 0 0 0 0 INPUT NODEFVAL clken
 669 // Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
 670 // Retrieval info: CONNECT: @dataa 0 0 32 0 dataa 0 0 32 0
 671 // Retrieval info: CONNECT: @datab 0 0 32 0 datab 0 0 32 0
 672 // Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
 673 // Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
 674 // Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
 675 // Retrieval info: LIBRARY: lpm lpm.lpm_components.all