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   1 // megafunction wizard: %FIFO%CBX%
   2 // GENERATION: STANDARD
   3 // VERSION: WM1.0
   4 // MODULE: dcfifo
   5
   6 // ============================================================
   7 // File Name: fifo_4k.v
   8 // Megafunction Name(s):
   9 //                      dcfifo
  10 // ============================================================
  11 // ************************************************************
  12 // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
  13 //
  14 // 5.0 Build 168 06/22/2005 SP 1 SJ Web Edition
  15 // ************************************************************
  16
  17
  18 //Copyright (C) 1991-2005 Altera Corporation
  19 //Your use of Altera Corporation's design tools, logic functions
  20 //and other software and tools, and its AMPP partner logic
  21 //functions, and any output files any of the foregoing
  22 //(including device programming or simulation files), and any
  23 //associated documentation or information are expressly subject
  24 //to the terms and conditions of the Altera Program License
  25 //Subscription Agreement, Altera MegaCore Function License
  26 //Agreement, or other applicable license agreement, including,
  27 //without limitation, that your use is for the sole purpose of
  28 //programming logic devices manufactured by Altera and sold by
  29 //Altera or its authorized distributors.  Please refer to the
  30 //applicable agreement for further details.
  31
  32
  33 //dcfifo ADD_RAM_OUTPUT_REGISTER="OFF" CLOCKS_ARE_SYNCHRONIZED="FALSE" DEVICE_FAMILY="Cyclone" LPM_NUMWORDS=4096 LPM_SHOWAHEAD="ON" LPM_WIDTH=16 LPM_WIDTHU=12 OVERFLOW_CHECKING="OFF" UNDERFLOW_CHECKING="OFF" USE_EAB="ON" aclr data q rdclk rdempty rdreq rdusedw wrclk wrfull wrreq wrusedw
  34 //VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_altdpram 2004:11:30:11:29:56:SJ cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_dcfifo 2005:03:07:17:11:14:SJ cbx_fifo_common 2004:12:13:14:26:24:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_counter 2005:02:02:04:37:10:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_scfifo 2005:03:10:10:52:20:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ  VERSION_END
  35
  36
  37 //a_gray2bin device_family="Cyclone" WIDTH=12 bin gray
  38 //VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_mgl 2005:05:19:13:51:58:SJ  VERSION_END
  39
  40 //synthesis_resources =
  41 //synopsys translate_off
  42 `timescale 1 ps / 1 ps
  43 //synopsys translate_on
  44 module  fifo_4k_a_gray2bin_9m4
  45         (
  46         bin,
  47         gray) /* synthesis synthesis_clearbox=1 */;
  48         output   [11:0]  bin;
  49         input   [11:0]  gray;
  50
  51         wire  xor0;
  52         wire  xor1;
  53         wire  xor10;
  54         wire  xor2;
  55         wire  xor3;
  56         wire  xor4;
  57         wire  xor5;
  58         wire  xor6;
  59         wire  xor7;
  60         wire  xor8;
  61         wire  xor9;
  62
  63         assign
  64                 bin = {gray[11], xor10, xor9, xor8, xor7, xor6, xor5, xor4, xor3, xor2, xor1, xor0},
  65                 xor0 = (gray[0] ^ xor1),
  66                 xor1 = (gray[1] ^ xor2),
  67                 xor10 = (gray[11] ^ gray[10]),
  68                 xor2 = (gray[2] ^ xor3),
  69                 xor3 = (gray[3] ^ xor4),
  70                 xor4 = (gray[4] ^ xor5),
  71                 xor5 = (gray[5] ^ xor6),
  72                 xor6 = (gray[6] ^ xor7),
  73                 xor7 = (gray[7] ^ xor8),
  74                 xor8 = (gray[8] ^ xor9),
  75                 xor9 = (gray[9] ^ xor10);
  76 endmodule //fifo_4k_a_gray2bin_9m4
  77
  78
  79 //a_graycounter DEVICE_FAMILY="Cyclone" WIDTH=12 aclr clock cnt_en q
  80 //VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ  VERSION_END
  81
  82 //synthesis_resources = lut 13
  83 //synopsys translate_off
  84 `timescale 1 ps / 1 ps
  85 //synopsys translate_on
  86 module  fifo_4k_a_graycounter_826
  87         (
  88         aclr,
  89         clock,
  90         cnt_en,
  91         q) /* synthesis synthesis_clearbox=1 */;
  92         input   aclr;
  93         input   clock;
  94         input   cnt_en;
  95         output   [11:0]  q;
  96
  97         wire  [0:0]   wire_countera_0cout;
  98         wire  [0:0]   wire_countera_1cout;
  99         wire  [0:0]   wire_countera_2cout;
 100         wire  [0:0]   wire_countera_3cout;
 101         wire  [0:0]   wire_countera_4cout;
 102         wire  [0:0]   wire_countera_5cout;
 103         wire  [0:0]   wire_countera_6cout;
 104         wire  [0:0]   wire_countera_7cout;
 105         wire  [0:0]   wire_countera_8cout;
 106         wire  [0:0]   wire_countera_9cout;
 107         wire  [0:0]   wire_countera_10cout;
 108         wire  [11:0]   wire_countera_regout;
 109         wire  wire_parity_cout;
 110         wire  wire_parity_regout;
 111         wire  [11:0]  power_modified_counter_values;
 112         wire sclr;
 113         wire updown;
 114
 115         cyclone_lcell   countera_0
 116         (
 117         .aclr(aclr),
 118         .cin(wire_parity_cout),
 119         .clk(clock),
 120         .combout(),
 121         .cout(wire_countera_0cout[0:0]),
 122         .dataa(cnt_en),
 123         .datab(wire_countera_regout[0:0]),
 124         .ena(1'b1),
 125         .regout(wire_countera_regout[0:0]),
 126         .sclr(sclr)
 127         `ifdef FORMAL_VERIFICATION
 128         `else
 129         // synopsys translate_off
 130         `endif
 131         ,
 132         .aload(1'b0),
 133         .datac(1'b1),
 134         .datad(1'b1),
 135         .inverta(1'b0),
 136         .regcascin(1'b0),
 137         .sload(1'b0)
 138         `ifdef FORMAL_VERIFICATION
 139         `else
 140         // synopsys translate_on
 141         `endif
 142         // synopsys translate_off
 143         ,
 144         .cin0(),
 145         .cin1(),
 146         .cout0(),
 147         .cout1(),
 148         .devclrn(),
 149         .devpor()
 150         // synopsys translate_on
 151         );
 152         defparam
 153                 countera_0.cin_used = "true",
 154                 countera_0.lut_mask = "c6a0",
 155                 countera_0.operation_mode = "arithmetic",
 156                 countera_0.sum_lutc_input = "cin",
 157                 countera_0.synch_mode = "on",
 158                 countera_0.lpm_type = "cyclone_lcell";
 159         cyclone_lcell   countera_1
 160         (
 161         .aclr(aclr),
 162         .cin(wire_countera_0cout[0:0]),
 163         .clk(clock),
 164         .combout(),
 165         .cout(wire_countera_1cout[0:0]),
 166         .dataa(power_modified_counter_values[0]),
 167         .datab(power_modified_counter_values[1]),
 168         .ena(1'b1),
 169         .regout(wire_countera_regout[1:1]),
 170         .sclr(sclr)
 171         `ifdef FORMAL_VERIFICATION
 172         `else
 173         // synopsys translate_off
 174         `endif
 175         ,
 176         .aload(1'b0),
 177         .datac(1'b1),
 178         .datad(1'b1),
 179         .inverta(1'b0),
 180         .regcascin(1'b0),
 181         .sload(1'b0)
 182         `ifdef FORMAL_VERIFICATION
 183         `else
 184         // synopsys translate_on
 185         `endif
 186         // synopsys translate_off
 187         ,
 188         .cin0(),
 189         .cin1(),
 190         .cout0(),
 191         .cout1(),
 192         .devclrn(),
 193         .devpor()
 194         // synopsys translate_on
 195         );
 196         defparam
 197                 countera_1.cin_used = "true",
 198                 countera_1.lut_mask = "6c50",
 199                 countera_1.operation_mode = "arithmetic",
 200                 countera_1.sum_lutc_input = "cin",
 201                 countera_1.synch_mode = "on",
 202                 countera_1.lpm_type = "cyclone_lcell";
 203         cyclone_lcell   countera_2
 204         (
 205         .aclr(aclr),
 206         .cin(wire_countera_1cout[0:0]),
 207         .clk(clock),
 208         .combout(),
 209         .cout(wire_countera_2cout[0:0]),
 210         .dataa(power_modified_counter_values[1]),
 211         .datab(power_modified_counter_values[2]),
 212         .ena(1'b1),
 213         .regout(wire_countera_regout[2:2]),
 214         .sclr(sclr)
 215         `ifdef FORMAL_VERIFICATION
 216         `else
 217         // synopsys translate_off
 218         `endif
 219         ,
 220         .aload(1'b0),
 221         .datac(1'b1),
 222         .datad(1'b1),
 223         .inverta(1'b0),
 224         .regcascin(1'b0),
 225         .sload(1'b0)
 226         `ifdef FORMAL_VERIFICATION
 227         `else
 228         // synopsys translate_on
 229         `endif
 230         // synopsys translate_off
 231         ,
 232         .cin0(),
 233         .cin1(),
 234         .cout0(),
 235         .cout1(),
 236         .devclrn(),
 237         .devpor()
 238         // synopsys translate_on
 239         );
 240         defparam
 241                 countera_2.cin_used = "true",
 242                 countera_2.lut_mask = "6c50",
 243                 countera_2.operation_mode = "arithmetic",
 244                 countera_2.sum_lutc_input = "cin",
 245                 countera_2.synch_mode = "on",
 246                 countera_2.lpm_type = "cyclone_lcell";
 247         cyclone_lcell   countera_3
 248         (
 249         .aclr(aclr),
 250         .cin(wire_countera_2cout[0:0]),
 251         .clk(clock),
 252         .combout(),
 253         .cout(wire_countera_3cout[0:0]),
 254         .dataa(power_modified_counter_values[2]),
 255         .datab(power_modified_counter_values[3]),
 256         .ena(1'b1),
 257         .regout(wire_countera_regout[3:3]),
 258         .sclr(sclr)
 259         `ifdef FORMAL_VERIFICATION
 260         `else
 261         // synopsys translate_off
 262         `endif
 263         ,
 264         .aload(1'b0),
 265         .datac(1'b1),
 266         .datad(1'b1),
 267         .inverta(1'b0),
 268         .regcascin(1'b0),
 269         .sload(1'b0)
 270         `ifdef FORMAL_VERIFICATION
 271         `else
 272         // synopsys translate_on
 273         `endif
 274         // synopsys translate_off
 275         ,
 276         .cin0(),
 277         .cin1(),
 278         .cout0(),
 279         .cout1(),
 280         .devclrn(),
 281         .devpor()
 282         // synopsys translate_on
 283         );
 284         defparam
 285                 countera_3.cin_used = "true",
 286                 countera_3.lut_mask = "6c50",
 287                 countera_3.operation_mode = "arithmetic",
 288                 countera_3.sum_lutc_input = "cin",
 289                 countera_3.synch_mode = "on",
 290                 countera_3.lpm_type = "cyclone_lcell";
 291         cyclone_lcell   countera_4
 292         (
 293         .aclr(aclr),
 294         .cin(wire_countera_3cout[0:0]),
 295         .clk(clock),
 296         .combout(),
 297         .cout(wire_countera_4cout[0:0]),
 298         .dataa(power_modified_counter_values[3]),
 299         .datab(power_modified_counter_values[4]),
 300         .ena(1'b1),
 301         .regout(wire_countera_regout[4:4]),
 302         .sclr(sclr)
 303         `ifdef FORMAL_VERIFICATION
 304         `else
 305         // synopsys translate_off
 306         `endif
 307         ,
 308         .aload(1'b0),
 309         .datac(1'b1),
 310         .datad(1'b1),
 311         .inverta(1'b0),
 312         .regcascin(1'b0),
 313         .sload(1'b0)
 314         `ifdef FORMAL_VERIFICATION
 315         `else
 316         // synopsys translate_on
 317         `endif
 318         // synopsys translate_off
 319         ,
 320         .cin0(),
 321         .cin1(),
 322         .cout0(),
 323         .cout1(),
 324         .devclrn(),
 325         .devpor()
 326         // synopsys translate_on
 327         );
 328         defparam
 329                 countera_4.cin_used = "true",
 330                 countera_4.lut_mask = "6c50",
 331                 countera_4.operation_mode = "arithmetic",
 332                 countera_4.sum_lutc_input = "cin",
 333                 countera_4.synch_mode = "on",
 334                 countera_4.lpm_type = "cyclone_lcell";
 335         cyclone_lcell   countera_5
 336         (
 337         .aclr(aclr),
 338         .cin(wire_countera_4cout[0:0]),
 339         .clk(clock),
 340         .combout(),
 341         .cout(wire_countera_5cout[0:0]),
 342         .dataa(power_modified_counter_values[4]),
 343         .datab(power_modified_counter_values[5]),
 344         .ena(1'b1),
 345         .regout(wire_countera_regout[5:5]),
 346         .sclr(sclr)
 347         `ifdef FORMAL_VERIFICATION
 348         `else
 349         // synopsys translate_off
 350         `endif
 351         ,
 352         .aload(1'b0),
 353         .datac(1'b1),
 354         .datad(1'b1),
 355         .inverta(1'b0),
 356         .regcascin(1'b0),
 357         .sload(1'b0)
 358         `ifdef FORMAL_VERIFICATION
 359         `else
 360         // synopsys translate_on
 361         `endif
 362         // synopsys translate_off
 363         ,
 364         .cin0(),
 365         .cin1(),
 366         .cout0(),
 367         .cout1(),
 368         .devclrn(),
 369         .devpor()
 370         // synopsys translate_on
 371         );
 372         defparam
 373                 countera_5.cin_used = "true",
 374                 countera_5.lut_mask = "6c50",
 375                 countera_5.operation_mode = "arithmetic",
 376                 countera_5.sum_lutc_input = "cin",
 377                 countera_5.synch_mode = "on",
 378                 countera_5.lpm_type = "cyclone_lcell";
 379         cyclone_lcell   countera_6
 380         (
 381         .aclr(aclr),
 382         .cin(wire_countera_5cout[0:0]),
 383         .clk(clock),
 384         .combout(),
 385         .cout(wire_countera_6cout[0:0]),
 386         .dataa(power_modified_counter_values[5]),
 387         .datab(power_modified_counter_values[6]),
 388         .ena(1'b1),
 389         .regout(wire_countera_regout[6:6]),
 390         .sclr(sclr)
 391         `ifdef FORMAL_VERIFICATION
 392         `else
 393         // synopsys translate_off
 394         `endif
 395         ,
 396         .aload(1'b0),
 397         .datac(1'b1),
 398         .datad(1'b1),
 399         .inverta(1'b0),
 400         .regcascin(1'b0),
 401         .sload(1'b0)
 402         `ifdef FORMAL_VERIFICATION
 403         `else
 404         // synopsys translate_on
 405         `endif
 406         // synopsys translate_off
 407         ,
 408         .cin0(),
 409         .cin1(),
 410         .cout0(),
 411         .cout1(),
 412         .devclrn(),
 413         .devpor()
 414         // synopsys translate_on
 415         );
 416         defparam
 417                 countera_6.cin_used = "true",
 418                 countera_6.lut_mask = "6c50",
 419                 countera_6.operation_mode = "arithmetic",
 420                 countera_6.sum_lutc_input = "cin",
 421                 countera_6.synch_mode = "on",
 422                 countera_6.lpm_type = "cyclone_lcell";
 423         cyclone_lcell   countera_7
 424         (
 425         .aclr(aclr),
 426         .cin(wire_countera_6cout[0:0]),
 427         .clk(clock),
 428         .combout(),
 429         .cout(wire_countera_7cout[0:0]),
 430         .dataa(power_modified_counter_values[6]),
 431         .datab(power_modified_counter_values[7]),
 432         .ena(1'b1),
 433         .regout(wire_countera_regout[7:7]),
 434         .sclr(sclr)
 435         `ifdef FORMAL_VERIFICATION
 436         `else
 437         // synopsys translate_off
 438         `endif
 439         ,
 440         .aload(1'b0),
 441         .datac(1'b1),
 442         .datad(1'b1),
 443         .inverta(1'b0),
 444         .regcascin(1'b0),
 445         .sload(1'b0)
 446         `ifdef FORMAL_VERIFICATION
 447         `else
 448         // synopsys translate_on
 449         `endif
 450         // synopsys translate_off
 451         ,
 452         .cin0(),
 453         .cin1(),
 454         .cout0(),
 455         .cout1(),
 456         .devclrn(),
 457         .devpor()
 458         // synopsys translate_on
 459         );
 460         defparam
 461                 countera_7.cin_used = "true",
 462                 countera_7.lut_mask = "6c50",
 463                 countera_7.operation_mode = "arithmetic",
 464                 countera_7.sum_lutc_input = "cin",
 465                 countera_7.synch_mode = "on",
 466                 countera_7.lpm_type = "cyclone_lcell";
 467         cyclone_lcell   countera_8
 468         (
 469         .aclr(aclr),
 470         .cin(wire_countera_7cout[0:0]),
 471         .clk(clock),
 472         .combout(),
 473         .cout(wire_countera_8cout[0:0]),
 474         .dataa(power_modified_counter_values[7]),
 475         .datab(power_modified_counter_values[8]),
 476         .ena(1'b1),
 477         .regout(wire_countera_regout[8:8]),
 478         .sclr(sclr)
 479         `ifdef FORMAL_VERIFICATION
 480         `else
 481         // synopsys translate_off
 482         `endif
 483         ,
 484         .aload(1'b0),
 485         .datac(1'b1),
 486         .datad(1'b1),
 487         .inverta(1'b0),
 488         .regcascin(1'b0),
 489         .sload(1'b0)
 490         `ifdef FORMAL_VERIFICATION
 491         `else
 492         // synopsys translate_on
 493         `endif
 494         // synopsys translate_off
 495         ,
 496         .cin0(),
 497         .cin1(),
 498         .cout0(),
 499         .cout1(),
 500         .devclrn(),
 501         .devpor()
 502         // synopsys translate_on
 503         );
 504         defparam
 505                 countera_8.cin_used = "true",
 506                 countera_8.lut_mask = "6c50",
 507                 countera_8.operation_mode = "arithmetic",
 508                 countera_8.sum_lutc_input = "cin",
 509                 countera_8.synch_mode = "on",
 510                 countera_8.lpm_type = "cyclone_lcell";
 511         cyclone_lcell   countera_9
 512         (
 513         .aclr(aclr),
 514         .cin(wire_countera_8cout[0:0]),
 515         .clk(clock),
 516         .combout(),
 517         .cout(wire_countera_9cout[0:0]),
 518         .dataa(power_modified_counter_values[8]),
 519         .datab(power_modified_counter_values[9]),
 520         .ena(1'b1),
 521         .regout(wire_countera_regout[9:9]),
 522         .sclr(sclr)
 523         `ifdef FORMAL_VERIFICATION
 524         `else
 525         // synopsys translate_off
 526         `endif
 527         ,
 528         .aload(1'b0),
 529         .datac(1'b1),
 530         .datad(1'b1),
 531         .inverta(1'b0),
 532         .regcascin(1'b0),
 533         .sload(1'b0)
 534         `ifdef FORMAL_VERIFICATION
 535         `else
 536         // synopsys translate_on
 537         `endif
 538         // synopsys translate_off
 539         ,
 540         .cin0(),
 541         .cin1(),
 542         .cout0(),
 543         .cout1(),
 544         .devclrn(),
 545         .devpor()
 546         // synopsys translate_on
 547         );
 548         defparam
 549                 countera_9.cin_used = "true",
 550                 countera_9.lut_mask = "6c50",
 551                 countera_9.operation_mode = "arithmetic",
 552                 countera_9.sum_lutc_input = "cin",
 553                 countera_9.synch_mode = "on",
 554                 countera_9.lpm_type = "cyclone_lcell";
 555         cyclone_lcell   countera_10
 556         (
 557         .aclr(aclr),
 558         .cin(wire_countera_9cout[0:0]),
 559         .clk(clock),
 560         .combout(),
 561         .cout(wire_countera_10cout[0:0]),
 562         .dataa(power_modified_counter_values[9]),
 563         .datab(power_modified_counter_values[10]),
 564         .ena(1'b1),
 565         .regout(wire_countera_regout[10:10]),
 566         .sclr(sclr)
 567         `ifdef FORMAL_VERIFICATION
 568         `else
 569         // synopsys translate_off
 570         `endif
 571         ,
 572         .aload(1'b0),
 573         .datac(1'b1),
 574         .datad(1'b1),
 575         .inverta(1'b0),
 576         .regcascin(1'b0),
 577         .sload(1'b0)
 578         `ifdef FORMAL_VERIFICATION
 579         `else
 580         // synopsys translate_on
 581         `endif
 582         // synopsys translate_off
 583         ,
 584         .cin0(),
 585         .cin1(),
 586         .cout0(),
 587         .cout1(),
 588         .devclrn(),
 589         .devpor()
 590         // synopsys translate_on
 591         );
 592         defparam
 593                 countera_10.cin_used = "true",
 594                 countera_10.lut_mask = "6c50",
 595                 countera_10.operation_mode = "arithmetic",
 596                 countera_10.sum_lutc_input = "cin",
 597                 countera_10.synch_mode = "on",
 598                 countera_10.lpm_type = "cyclone_lcell";
 599         cyclone_lcell   countera_11
 600         (
 601         .aclr(aclr),
 602         .cin(wire_countera_10cout[0:0]),
 603         .clk(clock),
 604         .combout(),
 605         .cout(),
 606         .dataa(power_modified_counter_values[11]),
 607         .ena(1'b1),
 608         .regout(wire_countera_regout[11:11]),
 609         .sclr(sclr)
 610         `ifdef FORMAL_VERIFICATION
 611         `else
 612         // synopsys translate_off
 613         `endif
 614         ,
 615         .aload(1'b0),
 616         .datab(1'b1),
 617         .datac(1'b1),
 618         .datad(1'b1),
 619         .inverta(1'b0),
 620         .regcascin(1'b0),
 621         .sload(1'b0)
 622         `ifdef FORMAL_VERIFICATION
 623         `else
 624         // synopsys translate_on
 625         `endif
 626         // synopsys translate_off
 627         ,
 628         .cin0(),
 629         .cin1(),
 630         .cout0(),
 631         .cout1(),
 632         .devclrn(),
 633         .devpor()
 634         // synopsys translate_on
 635         );
 636         defparam
 637                 countera_11.cin_used = "true",
 638                 countera_11.lut_mask = "5a5a",
 639                 countera_11.operation_mode = "normal",
 640                 countera_11.sum_lutc_input = "cin",
 641                 countera_11.synch_mode = "on",
 642                 countera_11.lpm_type = "cyclone_lcell";
 643         cyclone_lcell   parity
 644         (
 645         .aclr(aclr),
 646         .cin(updown),
 647         .clk(clock),
 648         .combout(),
 649         .cout(wire_parity_cout),
 650         .dataa(cnt_en),
 651         .datab(wire_parity_regout),
 652         .ena(1'b1),
 653         .regout(wire_parity_regout),
 654         .sclr(sclr)
 655         `ifdef FORMAL_VERIFICATION
 656         `else
 657         // synopsys translate_off
 658         `endif
 659         ,
 660         .aload(1'b0),
 661         .datac(1'b1),
 662         .datad(1'b1),
 663         .inverta(1'b0),
 664         .regcascin(1'b0),
 665         .sload(1'b0)
 666         `ifdef FORMAL_VERIFICATION
 667         `else
 668         // synopsys translate_on
 669         `endif
 670         // synopsys translate_off
 671         ,
 672         .cin0(),
 673         .cin1(),
 674         .cout0(),
 675         .cout1(),
 676         .devclrn(),
 677         .devpor()
 678         // synopsys translate_on
 679         );
 680         defparam
 681                 parity.cin_used = "true",
 682                 parity.lut_mask = "6682",
 683                 parity.operation_mode = "arithmetic",
 684                 parity.synch_mode = "on",
 685                 parity.lpm_type = "cyclone_lcell";
 686         assign
 687                 power_modified_counter_values = {wire_countera_regout[11:0]},
 688                 q = power_modified_counter_values,
 689                 sclr = 1'b0,
 690                 updown = 1'b1;
 691 endmodule //fifo_4k_a_graycounter_826
 692
 693
 694 //a_graycounter DEVICE_FAMILY="Cyclone" PVALUE=1 WIDTH=12 aclr clock cnt_en q
 695 //VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ  VERSION_END
 696
 697 //synthesis_resources = lut 13
 698 //synopsys translate_off
 699 `timescale 1 ps / 1 ps
 700 //synopsys translate_on
 701 module  fifo_4k_a_graycounter_3r6
 702         (
 703         aclr,
 704         clock,
 705         cnt_en,
 706         q) /* synthesis synthesis_clearbox=1 */;
 707         input   aclr;
 708         input   clock;
 709         input   cnt_en;
 710         output   [11:0]  q;
 711
 712         wire  [0:0]   wire_countera_0cout;
 713         wire  [0:0]   wire_countera_1cout;
 714         wire  [0:0]   wire_countera_2cout;
 715         wire  [0:0]   wire_countera_3cout;
 716         wire  [0:0]   wire_countera_4cout;
 717         wire  [0:0]   wire_countera_5cout;
 718         wire  [0:0]   wire_countera_6cout;
 719         wire  [0:0]   wire_countera_7cout;
 720         wire  [0:0]   wire_countera_8cout;
 721         wire  [0:0]   wire_countera_9cout;
 722         wire  [0:0]   wire_countera_10cout;
 723         wire  [11:0]   wire_countera_regout;
 724         wire  wire_parity_cout;
 725         wire  wire_parity_regout;
 726         wire  [11:0]  power_modified_counter_values;
 727         wire sclr;
 728         wire updown;
 729
 730         cyclone_lcell   countera_0
 731         (
 732         .aclr(aclr),
 733         .cin(wire_parity_cout),
 734         .clk(clock),
 735         .combout(),
 736         .cout(wire_countera_0cout[0:0]),
 737         .dataa(cnt_en),
 738         .datab(wire_countera_regout[0:0]),
 739         .ena(1'b1),
 740         .regout(wire_countera_regout[0:0]),
 741         .sclr(sclr)
 742         `ifdef FORMAL_VERIFICATION
 743         `else
 744         // synopsys translate_off
 745         `endif
 746         ,
 747         .aload(1'b0),
 748         .datac(1'b1),
 749         .datad(1'b1),
 750         .inverta(1'b0),
 751         .regcascin(1'b0),
 752         .sload(1'b0)
 753         `ifdef FORMAL_VERIFICATION
 754         `else
 755         // synopsys translate_on
 756         `endif
 757         // synopsys translate_off
 758         ,
 759         .cin0(),
 760         .cin1(),
 761         .cout0(),
 762         .cout1(),
 763         .devclrn(),
 764         .devpor()
 765         // synopsys translate_on
 766         );
 767         defparam
 768                 countera_0.cin_used = "true",
 769                 countera_0.lut_mask = "c6a0",
 770                 countera_0.operation_mode = "arithmetic",
 771                 countera_0.sum_lutc_input = "cin",
 772                 countera_0.synch_mode = "on",
 773                 countera_0.lpm_type = "cyclone_lcell";
 774         cyclone_lcell   countera_1
 775         (
 776         .aclr(aclr),
 777         .cin(wire_countera_0cout[0:0]),
 778         .clk(clock),
 779         .combout(),
 780         .cout(wire_countera_1cout[0:0]),
 781         .dataa(power_modified_counter_values[0]),
 782         .datab(power_modified_counter_values[1]),
 783         .ena(1'b1),
 784         .regout(wire_countera_regout[1:1]),
 785         .sclr(sclr)
 786         `ifdef FORMAL_VERIFICATION
 787         `else
 788         // synopsys translate_off
 789         `endif
 790         ,
 791         .aload(1'b0),
 792         .datac(1'b1),
 793         .datad(1'b1),
 794         .inverta(1'b0),
 795         .regcascin(1'b0),
 796         .sload(1'b0)
 797         `ifdef FORMAL_VERIFICATION
 798         `else
 799         // synopsys translate_on
 800         `endif
 801         // synopsys translate_off
 802         ,
 803         .cin0(),
 804         .cin1(),
 805         .cout0(),
 806         .cout1(),
 807         .devclrn(),
 808         .devpor()
 809         // synopsys translate_on
 810         );
 811         defparam
 812                 countera_1.cin_used = "true",
 813                 countera_1.lut_mask = "6c50",
 814                 countera_1.operation_mode = "arithmetic",
 815                 countera_1.sum_lutc_input = "cin",
 816                 countera_1.synch_mode = "on",
 817                 countera_1.lpm_type = "cyclone_lcell";
 818         cyclone_lcell   countera_2
 819         (
 820         .aclr(aclr),
 821         .cin(wire_countera_1cout[0:0]),
 822         .clk(clock),
 823         .combout(),
 824         .cout(wire_countera_2cout[0:0]),
 825         .dataa(power_modified_counter_values[1]),
 826         .datab(power_modified_counter_values[2]),
 827         .ena(1'b1),
 828         .regout(wire_countera_regout[2:2]),
 829         .sclr(sclr)
 830         `ifdef FORMAL_VERIFICATION
 831         `else
 832         // synopsys translate_off
 833         `endif
 834         ,
 835         .aload(1'b0),
 836         .datac(1'b1),
 837         .datad(1'b1),
 838         .inverta(1'b0),
 839         .regcascin(1'b0),
 840         .sload(1'b0)
 841         `ifdef FORMAL_VERIFICATION
 842         `else
 843         // synopsys translate_on
 844         `endif
 845         // synopsys translate_off
 846         ,
 847         .cin0(),
 848         .cin1(),
 849         .cout0(),
 850         .cout1(),
 851         .devclrn(),
 852         .devpor()
 853         // synopsys translate_on
 854         );
 855         defparam
 856                 countera_2.cin_used = "true",
 857                 countera_2.lut_mask = "6c50",
 858                 countera_2.operation_mode = "arithmetic",
 859                 countera_2.sum_lutc_input = "cin",
 860                 countera_2.synch_mode = "on",
 861                 countera_2.lpm_type = "cyclone_lcell";
 862         cyclone_lcell   countera_3
 863         (
 864         .aclr(aclr),
 865         .cin(wire_countera_2cout[0:0]),
 866         .clk(clock),
 867         .combout(),
 868         .cout(wire_countera_3cout[0:0]),
 869         .dataa(power_modified_counter_values[2]),
 870         .datab(power_modified_counter_values[3]),
 871         .ena(1'b1),
 872         .regout(wire_countera_regout[3:3]),
 873         .sclr(sclr)
 874         `ifdef FORMAL_VERIFICATION
 875         `else
 876         // synopsys translate_off
 877         `endif
 878         ,
 879         .aload(1'b0),
 880         .datac(1'b1),
 881         .datad(1'b1),
 882         .inverta(1'b0),
 883         .regcascin(1'b0),
 884         .sload(1'b0)
 885         `ifdef FORMAL_VERIFICATION
 886         `else
 887         // synopsys translate_on
 888         `endif
 889         // synopsys translate_off
 890         ,
 891         .cin0(),
 892         .cin1(),
 893         .cout0(),
 894         .cout1(),
 895         .devclrn(),
 896         .devpor()
 897         // synopsys translate_on
 898         );
 899         defparam
 900                 countera_3.cin_used = "true",
 901                 countera_3.lut_mask = "6c50",
 902                 countera_3.operation_mode = "arithmetic",
 903                 countera_3.sum_lutc_input = "cin",
 904                 countera_3.synch_mode = "on",
 905                 countera_3.lpm_type = "cyclone_lcell";
 906         cyclone_lcell   countera_4
 907         (
 908         .aclr(aclr),
 909         .cin(wire_countera_3cout[0:0]),
 910         .clk(clock),
 911         .combout(),
 912         .cout(wire_countera_4cout[0:0]),
 913         .dataa(power_modified_counter_values[3]),
 914         .datab(power_modified_counter_values[4]),
 915         .ena(1'b1),
 916         .regout(wire_countera_regout[4:4]),
 917         .sclr(sclr)
 918         `ifdef FORMAL_VERIFICATION
 919         `else
 920         // synopsys translate_off
 921         `endif
 922         ,
 923         .aload(1'b0),
 924         .datac(1'b1),
 925         .datad(1'b1),
 926         .inverta(1'b0),
 927         .regcascin(1'b0),
 928         .sload(1'b0)
 929         `ifdef FORMAL_VERIFICATION
 930         `else
 931         // synopsys translate_on
 932         `endif
 933         // synopsys translate_off
 934         ,
 935         .cin0(),
 936         .cin1(),
 937         .cout0(),
 938         .cout1(),
 939         .devclrn(),
 940         .devpor()
 941         // synopsys translate_on
 942         );
 943         defparam
 944                 countera_4.cin_used = "true",
 945                 countera_4.lut_mask = "6c50",
 946                 countera_4.operation_mode = "arithmetic",
 947                 countera_4.sum_lutc_input = "cin",
 948                 countera_4.synch_mode = "on",
 949                 countera_4.lpm_type = "cyclone_lcell";
 950         cyclone_lcell   countera_5
 951         (
 952         .aclr(aclr),
 953         .cin(wire_countera_4cout[0:0]),
 954         .clk(clock),
 955         .combout(),
 956         .cout(wire_countera_5cout[0:0]),
 957         .dataa(power_modified_counter_values[4]),
 958         .datab(power_modified_counter_values[5]),
 959         .ena(1'b1),
 960         .regout(wire_countera_regout[5:5]),
 961         .sclr(sclr)
 962         `ifdef FORMAL_VERIFICATION
 963         `else
 964         // synopsys translate_off
 965         `endif
 966         ,
 967         .aload(1'b0),
 968         .datac(1'b1),
 969         .datad(1'b1),
 970         .inverta(1'b0),
 971         .regcascin(1'b0),
 972         .sload(1'b0)
 973         `ifdef FORMAL_VERIFICATION
 974         `else
 975         // synopsys translate_on
 976         `endif
 977         // synopsys translate_off
 978         ,
 979         .cin0(),
 980         .cin1(),
 981         .cout0(),
 982         .cout1(),
 983         .devclrn(),
 984         .devpor()
 985         // synopsys translate_on
 986         );
 987         defparam
 988                 countera_5.cin_used = "true",
 989                 countera_5.lut_mask = "6c50",
 990                 countera_5.operation_mode = "arithmetic",
 991                 countera_5.sum_lutc_input = "cin",
 992                 countera_5.synch_mode = "on",
 993                 countera_5.lpm_type = "cyclone_lcell";
 994         cyclone_lcell   countera_6
 995         (
 996         .aclr(aclr),
 997         .cin(wire_countera_5cout[0:0]),
 998         .clk(clock),
 999         .combout(),
1000         .cout(wire_countera_6cout[0:0]),
1001         .dataa(power_modified_counter_values[5]),
1002         .datab(power_modified_counter_values[6]),
1003         .ena(1'b1),
1004         .regout(wire_countera_regout[6:6]),
1005         .sclr(sclr)
1006         `ifdef FORMAL_VERIFICATION
1007         `else
1008         // synopsys translate_off
1009         `endif
1010         ,
1011         .aload(1'b0),
1012         .datac(1'b1),
1013         .datad(1'b1),
1014         .inverta(1'b0),
1015         .regcascin(1'b0),
1016         .sload(1'b0)
1017         `ifdef FORMAL_VERIFICATION
1018         `else
1019         // synopsys translate_on
1020         `endif
1021         // synopsys translate_off
1022         ,
1023         .cin0(),
1024         .cin1(),
1025         .cout0(),
1026         .cout1(),
1027         .devclrn(),
1028         .devpor()
1029         // synopsys translate_on
1030         );
1031         defparam
1032                 countera_6.cin_used = "true",
1033                 countera_6.lut_mask = "6c50",
1034                 countera_6.operation_mode = "arithmetic",
1035                 countera_6.sum_lutc_input = "cin",
1036                 countera_6.synch_mode = "on",
1037                 countera_6.lpm_type = "cyclone_lcell";
1038         cyclone_lcell   countera_7
1039         (
1040         .aclr(aclr),
1041         .cin(wire_countera_6cout[0:0]),
1042         .clk(clock),
1043         .combout(),
1044         .cout(wire_countera_7cout[0:0]),
1045         .dataa(power_modified_counter_values[6]),
1046         .datab(power_modified_counter_values[7]),
1047         .ena(1'b1),
1048         .regout(wire_countera_regout[7:7]),
1049         .sclr(sclr)
1050         `ifdef FORMAL_VERIFICATION
1051         `else
1052         // synopsys translate_off
1053         `endif
1054         ,
1055         .aload(1'b0),
1056         .datac(1'b1),
1057         .datad(1'b1),
1058         .inverta(1'b0),
1059         .regcascin(1'b0),
1060         .sload(1'b0)
1061         `ifdef FORMAL_VERIFICATION
1062         `else
1063         // synopsys translate_on
1064         `endif
1065         // synopsys translate_off
1066         ,
1067         .cin0(),
1068         .cin1(),
1069         .cout0(),
1070         .cout1(),
1071         .devclrn(),
1072         .devpor()
1073         // synopsys translate_on
1074         );
1075         defparam
1076                 countera_7.cin_used = "true",
1077                 countera_7.lut_mask = "6c50",
1078                 countera_7.operation_mode = "arithmetic",
1079                 countera_7.sum_lutc_input = "cin",
1080                 countera_7.synch_mode = "on",
1081                 countera_7.lpm_type = "cyclone_lcell";
1082         cyclone_lcell   countera_8
1083         (
1084         .aclr(aclr),
1085         .cin(wire_countera_7cout[0:0]),
1086         .clk(clock),
1087         .combout(),
1088         .cout(wire_countera_8cout[0:0]),
1089         .dataa(power_modified_counter_values[7]),
1090         .datab(power_modified_counter_values[8]),
1091         .ena(1'b1),
1092         .regout(wire_countera_regout[8:8]),
1093         .sclr(sclr)
1094         `ifdef FORMAL_VERIFICATION
1095         `else
1096         // synopsys translate_off
1097         `endif
1098         ,
1099         .aload(1'b0),
1100         .datac(1'b1),
1101         .datad(1'b1),
1102         .inverta(1'b0),
1103         .regcascin(1'b0),
1104         .sload(1'b0)
1105         `ifdef FORMAL_VERIFICATION
1106         `else
1107         // synopsys translate_on
1108         `endif
1109         // synopsys translate_off
1110         ,
1111         .cin0(),
1112         .cin1(),
1113         .cout0(),
1114         .cout1(),
1115         .devclrn(),
1116         .devpor()
1117         // synopsys translate_on
1118         );
1119         defparam
1120                 countera_8.cin_used = "true",
1121                 countera_8.lut_mask = "6c50",
1122                 countera_8.operation_mode = "arithmetic",
1123                 countera_8.sum_lutc_input = "cin",
1124                 countera_8.synch_mode = "on",
1125                 countera_8.lpm_type = "cyclone_lcell";
1126         cyclone_lcell   countera_9
1127         (
1128         .aclr(aclr),
1129         .cin(wire_countera_8cout[0:0]),
1130         .clk(clock),
1131         .combout(),
1132         .cout(wire_countera_9cout[0:0]),
1133         .dataa(power_modified_counter_values[8]),
1134         .datab(power_modified_counter_values[9]),
1135         .ena(1'b1),
1136         .regout(wire_countera_regout[9:9]),
1137         .sclr(sclr)
1138         `ifdef FORMAL_VERIFICATION
1139         `else
1140         // synopsys translate_off
1141         `endif
1142         ,
1143         .aload(1'b0),
1144         .datac(1'b1),
1145         .datad(1'b1),
1146         .inverta(1'b0),
1147         .regcascin(1'b0),
1148         .sload(1'b0)
1149         `ifdef FORMAL_VERIFICATION
1150         `else
1151         // synopsys translate_on
1152         `endif
1153         // synopsys translate_off
1154         ,
1155         .cin0(),
1156         .cin1(),
1157         .cout0(),
1158         .cout1(),
1159         .devclrn(),
1160         .devpor()
1161         // synopsys translate_on
1162         );
1163         defparam
1164                 countera_9.cin_used = "true",
1165                 countera_9.lut_mask = "6c50",
1166                 countera_9.operation_mode = "arithmetic",
1167                 countera_9.sum_lutc_input = "cin",
1168                 countera_9.synch_mode = "on",
1169                 countera_9.lpm_type = "cyclone_lcell";
1170         cyclone_lcell   countera_10
1171         (
1172         .aclr(aclr),
1173         .cin(wire_countera_9cout[0:0]),
1174         .clk(clock),
1175         .combout(),
1176         .cout(wire_countera_10cout[0:0]),
1177         .dataa(power_modified_counter_values[9]),
1178         .datab(power_modified_counter_values[10]),
1179         .ena(1'b1),
1180         .regout(wire_countera_regout[10:10]),
1181         .sclr(sclr)
1182         `ifdef FORMAL_VERIFICATION
1183         `else
1184         // synopsys translate_off
1185         `endif
1186         ,
1187         .aload(1'b0),
1188         .datac(1'b1),
1189         .datad(1'b1),
1190         .inverta(1'b0),
1191         .regcascin(1'b0),
1192         .sload(1'b0)
1193         `ifdef FORMAL_VERIFICATION
1194         `else
1195         // synopsys translate_on
1196         `endif
1197         // synopsys translate_off
1198         ,
1199         .cin0(),
1200         .cin1(),
1201         .cout0(),
1202         .cout1(),
1203         .devclrn(),
1204         .devpor()
1205         // synopsys translate_on
1206         );
1207         defparam
1208                 countera_10.cin_used = "true",
1209                 countera_10.lut_mask = "6c50",
1210                 countera_10.operation_mode = "arithmetic",
1211                 countera_10.sum_lutc_input = "cin",
1212                 countera_10.synch_mode = "on",
1213                 countera_10.lpm_type = "cyclone_lcell";
1214         cyclone_lcell   countera_11
1215         (
1216         .aclr(aclr),
1217         .cin(wire_countera_10cout[0:0]),
1218         .clk(clock),
1219         .combout(),
1220         .cout(),
1221         .dataa(power_modified_counter_values[11]),
1222         .ena(1'b1),
1223         .regout(wire_countera_regout[11:11]),
1224         .sclr(sclr)
1225         `ifdef FORMAL_VERIFICATION
1226         `else
1227         // synopsys translate_off
1228         `endif
1229         ,
1230         .aload(1'b0),
1231         .datab(1'b1),
1232         .datac(1'b1),
1233         .datad(1'b1),
1234         .inverta(1'b0),
1235         .regcascin(1'b0),
1236         .sload(1'b0)
1237         `ifdef FORMAL_VERIFICATION
1238         `else
1239         // synopsys translate_on
1240         `endif
1241         // synopsys translate_off
1242         ,
1243         .cin0(),
1244         .cin1(),
1245         .cout0(),
1246         .cout1(),
1247         .devclrn(),
1248         .devpor()
1249         // synopsys translate_on
1250         );
1251         defparam
1252                 countera_11.cin_used = "true",
1253                 countera_11.lut_mask = "5a5a",
1254                 countera_11.operation_mode = "normal",
1255                 countera_11.sum_lutc_input = "cin",
1256                 countera_11.synch_mode = "on",
1257                 countera_11.lpm_type = "cyclone_lcell";
1258         cyclone_lcell   parity
1259         (
1260         .aclr(aclr),
1261         .cin(updown),
1262         .clk(clock),
1263         .combout(),
1264         .cout(wire_parity_cout),
1265         .dataa(cnt_en),
1266         .datab((~ wire_parity_regout)),
1267         .ena(1'b1),
1268         .regout(wire_parity_regout),
1269         .sclr(sclr)
1270         `ifdef FORMAL_VERIFICATION
1271         `else
1272         // synopsys translate_off
1273         `endif
1274         ,
1275         .aload(1'b0),
1276         .datac(1'b1),
1277         .datad(1'b1),
1278         .inverta(1'b0),
1279         .regcascin(1'b0),
1280         .sload(1'b0)
1281         `ifdef FORMAL_VERIFICATION
1282         `else
1283         // synopsys translate_on
1284         `endif
1285         // synopsys translate_off
1286         ,
1287         .cin0(),
1288         .cin1(),
1289         .cout0(),
1290         .cout1(),
1291         .devclrn(),
1292         .devpor()
1293         // synopsys translate_on
1294         );
1295         defparam
1296                 parity.cin_used = "true",
1297                 parity.lut_mask = "9982",
1298                 parity.operation_mode = "arithmetic",
1299                 parity.synch_mode = "on",
1300                 parity.lpm_type = "cyclone_lcell";
1301         assign
1302                 power_modified_counter_values = {wire_countera_regout[11:1], (~ wire_countera_regout[0])},
1303                 q = power_modified_counter_values,
1304                 sclr = 1'b0,
1305                 updown = 1'b1;
1306 endmodule //fifo_4k_a_graycounter_3r6
1307
1308
1309 //altsyncram ADDRESS_REG_B="CLOCK1" DEVICE_FAMILY="Cyclone" OPERATION_MODE="DUAL_PORT" OUTDATA_REG_B="UNREGISTERED" WIDTH_A=16 WIDTH_B=16 WIDTH_BYTEENA_A=1 WIDTHAD_A=12 WIDTHAD_B=12 address_a address_b clock0 clock1 clocken1 data_a q_b wren_a
1310 //VERSION_BEGIN 5.0 cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ  VERSION_END
1311
1312 //synthesis_resources = M4K 16
1313 //synopsys translate_off
1314 `timescale 1 ps / 1 ps
1315 //synopsys translate_on
1316 module  fifo_4k_altsyncram_8pl
1317         (
1318         address_a,
1319         address_b,
1320         clock0,
1321         clock1,
1322         clocken1,
1323         data_a,
1324         q_b,
1325         wren_a) /* synthesis synthesis_clearbox=1 */;
1326         input   [11:0]  address_a;
1327         input   [11:0]  address_b;
1328         input   clock0;
1329         input   clock1;
1330         input   clocken1;
1331         input   [15:0]  data_a;
1332         output   [15:0]  q_b;
1333         input   wren_a;
1334
1335         wire  [0:0]   wire_ram_block3a_0portbdataout;
1336         wire  [0:0]   wire_ram_block3a_1portbdataout;
1337         wire  [0:0]   wire_ram_block3a_2portbdataout;
1338         wire  [0:0]   wire_ram_block3a_3portbdataout;
1339         wire  [0:0]   wire_ram_block3a_4portbdataout;
1340         wire  [0:0]   wire_ram_block3a_5portbdataout;
1341         wire  [0:0]   wire_ram_block3a_6portbdataout;
1342         wire  [0:0]   wire_ram_block3a_7portbdataout;
1343         wire  [0:0]   wire_ram_block3a_8portbdataout;
1344         wire  [0:0]   wire_ram_block3a_9portbdataout;
1345         wire  [0:0]   wire_ram_block3a_10portbdataout;
1346         wire  [0:0]   wire_ram_block3a_11portbdataout;
1347         wire  [0:0]   wire_ram_block3a_12portbdataout;
1348         wire  [0:0]   wire_ram_block3a_13portbdataout;
1349         wire  [0:0]   wire_ram_block3a_14portbdataout;
1350         wire  [0:0]   wire_ram_block3a_15portbdataout;
1351         wire  [11:0]  address_a_wire;
1352         wire  [11:0]  address_b_wire;
1353
1354         cyclone_ram_block   ram_block3a_0
1355         (
1356         .clk0(clock0),
1357         .clk1(clock1),
1358         .ena0(wren_a),
1359         .ena1(clocken1),
1360         .portaaddr({address_a_wire[11:0]}),
1361         .portadatain({data_a[0]}),
1362         .portadataout(),
1363         .portawe(1'b1),
1364         .portbaddr({address_b_wire[11:0]}),
1365         .portbdataout(wire_ram_block3a_0portbdataout[0:0]),
1366         .portbrewe(1'b1)
1367         `ifdef FORMAL_VERIFICATION
1368         `else
1369         // synopsys translate_off
1370         `endif
1371         ,
1372         .clr0(1'b0),
1373         .clr1(1'b0),
1374         .portabyteenamasks(1'b1),
1375         .portbbyteenamasks(1'b1),
1376         .portbdatain(1'b0)
1377         `ifdef FORMAL_VERIFICATION
1378         `else
1379         // synopsys translate_on
1380         `endif
1381         // synopsys translate_off
1382         ,
1383         .devclrn(),
1384         .devpor()
1385         // synopsys translate_on
1386         );
1387         defparam
1388                 ram_block3a_0.connectivity_checking = "OFF",
1389                 ram_block3a_0.logical_ram_name = "ALTSYNCRAM",
1390                 ram_block3a_0.mixed_port_feed_through_mode = "dont_care",
1391                 ram_block3a_0.operation_mode = "dual_port",
1392                 ram_block3a_0.port_a_address_width = 12,
1393                 ram_block3a_0.port_a_data_width = 1,
1394                 ram_block3a_0.port_a_first_address = 0,
1395                 ram_block3a_0.port_a_first_bit_number = 0,
1396                 ram_block3a_0.port_a_last_address = 4095,
1397                 ram_block3a_0.port_a_logical_ram_depth = 4096,
1398                 ram_block3a_0.port_a_logical_ram_width = 16,
1399                 ram_block3a_0.port_b_address_clear = "none",
1400                 ram_block3a_0.port_b_address_clock = "clock1",
1401                 ram_block3a_0.port_b_address_width = 12,
1402                 ram_block3a_0.port_b_data_out_clear = "none",
1403                 ram_block3a_0.port_b_data_out_clock = "none",
1404                 ram_block3a_0.port_b_data_width = 1,
1405                 ram_block3a_0.port_b_first_address = 0,
1406                 ram_block3a_0.port_b_first_bit_number = 0,
1407                 ram_block3a_0.port_b_last_address = 4095,
1408                 ram_block3a_0.port_b_logical_ram_depth = 4096,
1409                 ram_block3a_0.port_b_logical_ram_width = 16,
1410                 ram_block3a_0.port_b_read_enable_write_enable_clock = "clock1",
1411                 ram_block3a_0.ram_block_type = "auto",
1412                 ram_block3a_0.lpm_type = "cyclone_ram_block";
1413         cyclone_ram_block   ram_block3a_1
1414         (
1415         .clk0(clock0),
1416         .clk1(clock1),
1417         .ena0(wren_a),
1418         .ena1(clocken1),
1419         .portaaddr({address_a_wire[11:0]}),
1420         .portadatain({data_a[1]}),
1421         .portadataout(),
1422         .portawe(1'b1),
1423         .portbaddr({address_b_wire[11:0]}),
1424         .portbdataout(wire_ram_block3a_1portbdataout[0:0]),
1425         .portbrewe(1'b1)
1426         `ifdef FORMAL_VERIFICATION
1427         `else
1428         // synopsys translate_off
1429         `endif
1430         ,
1431         .clr0(1'b0),
1432         .clr1(1'b0),
1433         .portabyteenamasks(1'b1),
1434         .portbbyteenamasks(1'b1),
1435         .portbdatain(1'b0)
1436         `ifdef FORMAL_VERIFICATION
1437         `else
1438         // synopsys translate_on
1439         `endif
1440         // synopsys translate_off
1441         ,
1442         .devclrn(),
1443         .devpor()
1444         // synopsys translate_on
1445         );
1446         defparam
1447                 ram_block3a_1.connectivity_checking = "OFF",
1448                 ram_block3a_1.logical_ram_name = "ALTSYNCRAM",
1449                 ram_block3a_1.mixed_port_feed_through_mode = "dont_care",
1450                 ram_block3a_1.operation_mode = "dual_port",
1451                 ram_block3a_1.port_a_address_width = 12,
1452                 ram_block3a_1.port_a_data_width = 1,
1453                 ram_block3a_1.port_a_first_address = 0,
1454                 ram_block3a_1.port_a_first_bit_number = 1,
1455                 ram_block3a_1.port_a_last_address = 4095,
1456                 ram_block3a_1.port_a_logical_ram_depth = 4096,
1457                 ram_block3a_1.port_a_logical_ram_width = 16,
1458                 ram_block3a_1.port_b_address_clear = "none",
1459                 ram_block3a_1.port_b_address_clock = "clock1",
1460                 ram_block3a_1.port_b_address_width = 12,
1461                 ram_block3a_1.port_b_data_out_clear = "none",
1462                 ram_block3a_1.port_b_data_out_clock = "none",
1463                 ram_block3a_1.port_b_data_width = 1,
1464                 ram_block3a_1.port_b_first_address = 0,
1465                 ram_block3a_1.port_b_first_bit_number = 1,
1466                 ram_block3a_1.port_b_last_address = 4095,
1467                 ram_block3a_1.port_b_logical_ram_depth = 4096,
1468                 ram_block3a_1.port_b_logical_ram_width = 16,
1469                 ram_block3a_1.port_b_read_enable_write_enable_clock = "clock1",
1470                 ram_block3a_1.ram_block_type = "auto",
1471                 ram_block3a_1.lpm_type = "cyclone_ram_block";
1472         cyclone_ram_block   ram_block3a_2
1473         (
1474         .clk0(clock0),
1475         .clk1(clock1),
1476         .ena0(wren_a),
1477         .ena1(clocken1),
1478         .portaaddr({address_a_wire[11:0]}),
1479         .portadatain({data_a[2]}),
1480         .portadataout(),
1481         .portawe(1'b1),
1482         .portbaddr({address_b_wire[11:0]}),
1483         .portbdataout(wire_ram_block3a_2portbdataout[0:0]),
1484         .portbrewe(1'b1)
1485         `ifdef FORMAL_VERIFICATION
1486         `else
1487         // synopsys translate_off
1488         `endif
1489         ,
1490         .clr0(1'b0),
1491         .clr1(1'b0),
1492         .portabyteenamasks(1'b1),
1493         .portbbyteenamasks(1'b1),
1494         .portbdatain(1'b0)
1495         `ifdef FORMAL_VERIFICATION
1496         `else
1497         // synopsys translate_on
1498         `endif
1499         // synopsys translate_off
1500         ,
1501         .devclrn(),
1502         .devpor()
1503         // synopsys translate_on
1504         );
1505         defparam
1506                 ram_block3a_2.connectivity_checking = "OFF",
1507                 ram_block3a_2.logical_ram_name = "ALTSYNCRAM",
1508                 ram_block3a_2.mixed_port_feed_through_mode = "dont_care",
1509                 ram_block3a_2.operation_mode = "dual_port",
1510                 ram_block3a_2.port_a_address_width = 12,
1511                 ram_block3a_2.port_a_data_width = 1,
1512                 ram_block3a_2.port_a_first_address = 0,
1513                 ram_block3a_2.port_a_first_bit_number = 2,
1514                 ram_block3a_2.port_a_last_address = 4095,
1515                 ram_block3a_2.port_a_logical_ram_depth = 4096,
1516                 ram_block3a_2.port_a_logical_ram_width = 16,
1517                 ram_block3a_2.port_b_address_clear = "none",
1518                 ram_block3a_2.port_b_address_clock = "clock1",
1519                 ram_block3a_2.port_b_address_width = 12,
1520                 ram_block3a_2.port_b_data_out_clear = "none",
1521                 ram_block3a_2.port_b_data_out_clock = "none",
1522                 ram_block3a_2.port_b_data_width = 1,
1523                 ram_block3a_2.port_b_first_address = 0,
1524                 ram_block3a_2.port_b_first_bit_number = 2,
1525                 ram_block3a_2.port_b_last_address = 4095,
1526                 ram_block3a_2.port_b_logical_ram_depth = 4096,
1527                 ram_block3a_2.port_b_logical_ram_width = 16,
1528                 ram_block3a_2.port_b_read_enable_write_enable_clock = "clock1",
1529                 ram_block3a_2.ram_block_type = "auto",
1530                 ram_block3a_2.lpm_type = "cyclone_ram_block";
1531         cyclone_ram_block   ram_block3a_3
1532         (
1533         .clk0(clock0),
1534         .clk1(clock1),
1535         .ena0(wren_a),
1536         .ena1(clocken1),
1537         .portaaddr({address_a_wire[11:0]}),
1538         .portadatain({data_a[3]}),
1539         .portadataout(),
1540         .portawe(1'b1),
1541         .portbaddr({address_b_wire[11:0]}),
1542         .portbdataout(wire_ram_block3a_3portbdataout[0:0]),
1543         .portbrewe(1'b1)
1544         `ifdef FORMAL_VERIFICATION
1545         `else
1546         // synopsys translate_off
1547         `endif
1548         ,
1549         .clr0(1'b0),
1550         .clr1(1'b0),
1551         .portabyteenamasks(1'b1),
1552         .portbbyteenamasks(1'b1),
1553         .portbdatain(1'b0)
1554         `ifdef FORMAL_VERIFICATION
1555         `else
1556         // synopsys translate_on
1557         `endif
1558         // synopsys translate_off
1559         ,
1560         .devclrn(),
1561         .devpor()
1562         // synopsys translate_on
1563         );
1564         defparam
1565                 ram_block3a_3.connectivity_checking = "OFF",
1566                 ram_block3a_3.logical_ram_name = "ALTSYNCRAM",
1567                 ram_block3a_3.mixed_port_feed_through_mode = "dont_care",
1568                 ram_block3a_3.operation_mode = "dual_port",
1569                 ram_block3a_3.port_a_address_width = 12,
1570                 ram_block3a_3.port_a_data_width = 1,
1571                 ram_block3a_3.port_a_first_address = 0,
1572                 ram_block3a_3.port_a_first_bit_number = 3,
1573                 ram_block3a_3.port_a_last_address = 4095,
1574                 ram_block3a_3.port_a_logical_ram_depth = 4096,
1575                 ram_block3a_3.port_a_logical_ram_width = 16,
1576                 ram_block3a_3.port_b_address_clear = "none",
1577                 ram_block3a_3.port_b_address_clock = "clock1",
1578                 ram_block3a_3.port_b_address_width = 12,
1579                 ram_block3a_3.port_b_data_out_clear = "none",
1580                 ram_block3a_3.port_b_data_out_clock = "none",
1581                 ram_block3a_3.port_b_data_width = 1,
1582                 ram_block3a_3.port_b_first_address = 0,
1583                 ram_block3a_3.port_b_first_bit_number = 3,
1584                 ram_block3a_3.port_b_last_address = 4095,
1585                 ram_block3a_3.port_b_logical_ram_depth = 4096,
1586                 ram_block3a_3.port_b_logical_ram_width = 16,
1587                 ram_block3a_3.port_b_read_enable_write_enable_clock = "clock1",
1588                 ram_block3a_3.ram_block_type = "auto",
1589                 ram_block3a_3.lpm_type = "cyclone_ram_block";
1590         cyclone_ram_block   ram_block3a_4
1591         (
1592         .clk0(clock0),
1593         .clk1(clock1),
1594         .ena0(wren_a),
1595         .ena1(clocken1),
1596         .portaaddr({address_a_wire[11:0]}),
1597         .portadatain({data_a[4]}),
1598         .portadataout(),
1599         .portawe(1'b1),
1600         .portbaddr({address_b_wire[11:0]}),
1601         .portbdataout(wire_ram_block3a_4portbdataout[0:0]),
1602         .portbrewe(1'b1)
1603         `ifdef FORMAL_VERIFICATION
1604         `else
1605         // synopsys translate_off
1606         `endif
1607         ,
1608         .clr0(1'b0),
1609         .clr1(1'b0),
1610         .portabyteenamasks(1'b1),
1611         .portbbyteenamasks(1'b1),
1612         .portbdatain(1'b0)
1613         `ifdef FORMAL_VERIFICATION
1614         `else
1615         // synopsys translate_on
1616         `endif
1617         // synopsys translate_off
1618         ,
1619         .devclrn(),
1620         .devpor()
1621         // synopsys translate_on
1622         );
1623         defparam
1624                 ram_block3a_4.connectivity_checking = "OFF",
1625                 ram_block3a_4.logical_ram_name = "ALTSYNCRAM",
1626                 ram_block3a_4.mixed_port_feed_through_mode = "dont_care",
1627                 ram_block3a_4.operation_mode = "dual_port",
1628                 ram_block3a_4.port_a_address_width = 12,
1629                 ram_block3a_4.port_a_data_width = 1,
1630                 ram_block3a_4.port_a_first_address = 0,
1631                 ram_block3a_4.port_a_first_bit_number = 4,
1632                 ram_block3a_4.port_a_last_address = 4095,
1633                 ram_block3a_4.port_a_logical_ram_depth = 4096,
1634                 ram_block3a_4.port_a_logical_ram_width = 16,
1635                 ram_block3a_4.port_b_address_clear = "none",
1636                 ram_block3a_4.port_b_address_clock = "clock1",
1637                 ram_block3a_4.port_b_address_width = 12,
1638                 ram_block3a_4.port_b_data_out_clear = "none",
1639                 ram_block3a_4.port_b_data_out_clock = "none",
1640                 ram_block3a_4.port_b_data_width = 1,
1641                 ram_block3a_4.port_b_first_address = 0,
1642                 ram_block3a_4.port_b_first_bit_number = 4,
1643                 ram_block3a_4.port_b_last_address = 4095,
1644                 ram_block3a_4.port_b_logical_ram_depth = 4096,
1645                 ram_block3a_4.port_b_logical_ram_width = 16,
1646                 ram_block3a_4.port_b_read_enable_write_enable_clock = "clock1",
1647                 ram_block3a_4.ram_block_type = "auto",
1648                 ram_block3a_4.lpm_type = "cyclone_ram_block";
1649         cyclone_ram_block   ram_block3a_5
1650         (
1651         .clk0(clock0),
1652         .clk1(clock1),
1653         .ena0(wren_a),
1654         .ena1(clocken1),
1655         .portaaddr({address_a_wire[11:0]}),
1656         .portadatain({data_a[5]}),
1657         .portadataout(),
1658         .portawe(1'b1),
1659         .portbaddr({address_b_wire[11:0]}),
1660         .portbdataout(wire_ram_block3a_5portbdataout[0:0]),
1661         .portbrewe(1'b1)
1662         `ifdef FORMAL_VERIFICATION
1663         `else
1664         // synopsys translate_off
1665         `endif
1666         ,
1667         .clr0(1'b0),
1668         .clr1(1'b0),
1669         .portabyteenamasks(1'b1),
1670         .portbbyteenamasks(1'b1),
1671         .portbdatain(1'b0)
1672         `ifdef FORMAL_VERIFICATION
1673         `else
1674         // synopsys translate_on
1675         `endif
1676         // synopsys translate_off
1677         ,
1678         .devclrn(),
1679         .devpor()
1680         // synopsys translate_on
1681         );
1682         defparam
1683                 ram_block3a_5.connectivity_checking = "OFF",
1684                 ram_block3a_5.logical_ram_name = "ALTSYNCRAM",
1685                 ram_block3a_5.mixed_port_feed_through_mode = "dont_care",
1686                 ram_block3a_5.operation_mode = "dual_port",
1687                 ram_block3a_5.port_a_address_width = 12,
1688                 ram_block3a_5.port_a_data_width = 1,
1689                 ram_block3a_5.port_a_first_address = 0,
1690                 ram_block3a_5.port_a_first_bit_number = 5,
1691                 ram_block3a_5.port_a_last_address = 4095,
1692                 ram_block3a_5.port_a_logical_ram_depth = 4096,
1693                 ram_block3a_5.port_a_logical_ram_width = 16,
1694                 ram_block3a_5.port_b_address_clear = "none",
1695                 ram_block3a_5.port_b_address_clock = "clock1",
1696                 ram_block3a_5.port_b_address_width = 12,
1697                 ram_block3a_5.port_b_data_out_clear = "none",
1698                 ram_block3a_5.port_b_data_out_clock = "none",
1699                 ram_block3a_5.port_b_data_width = 1,
1700                 ram_block3a_5.port_b_first_address = 0,
1701                 ram_block3a_5.port_b_first_bit_number = 5,
1702                 ram_block3a_5.port_b_last_address = 4095,
1703                 ram_block3a_5.port_b_logical_ram_depth = 4096,
1704                 ram_block3a_5.port_b_logical_ram_width = 16,
1705                 ram_block3a_5.port_b_read_enable_write_enable_clock = "clock1",
1706                 ram_block3a_5.ram_block_type = "auto",
1707                 ram_block3a_5.lpm_type = "cyclone_ram_block";
1708         cyclone_ram_block   ram_block3a_6
1709         (
1710         .clk0(clock0),
1711         .clk1(clock1),
1712         .ena0(wren_a),
1713         .ena1(clocken1),
1714         .portaaddr({address_a_wire[11:0]}),
1715         .portadatain({data_a[6]}),
1716         .portadataout(),
1717         .portawe(1'b1),
1718         .portbaddr({address_b_wire[11:0]}),
1719         .portbdataout(wire_ram_block3a_6portbdataout[0:0]),
1720         .portbrewe(1'b1)
1721         `ifdef FORMAL_VERIFICATION
1722         `else
1723         // synopsys translate_off
1724         `endif
1725         ,
1726         .clr0(1'b0),
1727         .clr1(1'b0),
1728         .portabyteenamasks(1'b1),
1729         .portbbyteenamasks(1'b1),
1730         .portbdatain(1'b0)
1731         `ifdef FORMAL_VERIFICATION
1732         `else
1733         // synopsys translate_on
1734         `endif
1735         // synopsys translate_off
1736         ,
1737         .devclrn(),
1738         .devpor()
1739         // synopsys translate_on
1740         );
1741         defparam
1742                 ram_block3a_6.connectivity_checking = "OFF",
1743                 ram_block3a_6.logical_ram_name = "ALTSYNCRAM",
1744                 ram_block3a_6.mixed_port_feed_through_mode = "dont_care",
1745                 ram_block3a_6.operation_mode = "dual_port",
1746                 ram_block3a_6.port_a_address_width = 12,
1747                 ram_block3a_6.port_a_data_width = 1,
1748                 ram_block3a_6.port_a_first_address = 0,
1749                 ram_block3a_6.port_a_first_bit_number = 6,
1750                 ram_block3a_6.port_a_last_address = 4095,
1751                 ram_block3a_6.port_a_logical_ram_depth = 4096,
1752                 ram_block3a_6.port_a_logical_ram_width = 16,
1753                 ram_block3a_6.port_b_address_clear = "none",
1754                 ram_block3a_6.port_b_address_clock = "clock1",
1755                 ram_block3a_6.port_b_address_width = 12,
1756                 ram_block3a_6.port_b_data_out_clear = "none",
1757                 ram_block3a_6.port_b_data_out_clock = "none",
1758                 ram_block3a_6.port_b_data_width = 1,
1759                 ram_block3a_6.port_b_first_address = 0,
1760                 ram_block3a_6.port_b_first_bit_number = 6,
1761                 ram_block3a_6.port_b_last_address = 4095,
1762                 ram_block3a_6.port_b_logical_ram_depth = 4096,
1763                 ram_block3a_6.port_b_logical_ram_width = 16,
1764                 ram_block3a_6.port_b_read_enable_write_enable_clock = "clock1",
1765                 ram_block3a_6.ram_block_type = "auto",
1766                 ram_block3a_6.lpm_type = "cyclone_ram_block";
1767         cyclone_ram_block   ram_block3a_7
1768         (
1769         .clk0(clock0),
1770         .clk1(clock1),
1771         .ena0(wren_a),
1772         .ena1(clocken1),
1773         .portaaddr({address_a_wire[11:0]}),
1774         .portadatain({data_a[7]}),
1775         .portadataout(),
1776         .portawe(1'b1),
1777         .portbaddr({address_b_wire[11:0]}),
1778         .portbdataout(wire_ram_block3a_7portbdataout[0:0]),
1779         .portbrewe(1'b1)
1780         `ifdef FORMAL_VERIFICATION
1781         `else
1782         // synopsys translate_off
1783         `endif
1784         ,
1785         .clr0(1'b0),
1786         .clr1(1'b0),
1787         .portabyteenamasks(1'b1),
1788         .portbbyteenamasks(1'b1),
1789         .portbdatain(1'b0)
1790         `ifdef FORMAL_VERIFICATION
1791         `else
1792         // synopsys translate_on
1793         `endif
1794         // synopsys translate_off
1795         ,
1796         .devclrn(),
1797         .devpor()
1798         // synopsys translate_on
1799         );
1800         defparam
1801                 ram_block3a_7.connectivity_checking = "OFF",
1802                 ram_block3a_7.logical_ram_name = "ALTSYNCRAM",
1803                 ram_block3a_7.mixed_port_feed_through_mode = "dont_care",
1804                 ram_block3a_7.operation_mode = "dual_port",
1805                 ram_block3a_7.port_a_address_width = 12,
1806                 ram_block3a_7.port_a_data_width = 1,
1807                 ram_block3a_7.port_a_first_address = 0,
1808                 ram_block3a_7.port_a_first_bit_number = 7,
1809                 ram_block3a_7.port_a_last_address = 4095,
1810                 ram_block3a_7.port_a_logical_ram_depth = 4096,
1811                 ram_block3a_7.port_a_logical_ram_width = 16,
1812                 ram_block3a_7.port_b_address_clear = "none",
1813                 ram_block3a_7.port_b_address_clock = "clock1",
1814                 ram_block3a_7.port_b_address_width = 12,
1815                 ram_block3a_7.port_b_data_out_clear = "none",
1816                 ram_block3a_7.port_b_data_out_clock = "none",
1817                 ram_block3a_7.port_b_data_width = 1,
1818                 ram_block3a_7.port_b_first_address = 0,
1819                 ram_block3a_7.port_b_first_bit_number = 7,
1820                 ram_block3a_7.port_b_last_address = 4095,
1821                 ram_block3a_7.port_b_logical_ram_depth = 4096,
1822                 ram_block3a_7.port_b_logical_ram_width = 16,
1823                 ram_block3a_7.port_b_read_enable_write_enable_clock = "clock1",
1824                 ram_block3a_7.ram_block_type = "auto",
1825                 ram_block3a_7.lpm_type = "cyclone_ram_block";
1826         cyclone_ram_block   ram_block3a_8
1827         (
1828         .clk0(clock0),
1829         .clk1(clock1),
1830         .ena0(wren_a),
1831         .ena1(clocken1),
1832         .portaaddr({address_a_wire[11:0]}),
1833         .portadatain({data_a[8]}),
1834         .portadataout(),
1835         .portawe(1'b1),
1836         .portbaddr({address_b_wire[11:0]}),
1837         .portbdataout(wire_ram_block3a_8portbdataout[0:0]),
1838         .portbrewe(1'b1)
1839         `ifdef FORMAL_VERIFICATION
1840         `else
1841         // synopsys translate_off
1842         `endif
1843         ,
1844         .clr0(1'b0),
1845         .clr1(1'b0),
1846         .portabyteenamasks(1'b1),
1847         .portbbyteenamasks(1'b1),
1848         .portbdatain(1'b0)
1849         `ifdef FORMAL_VERIFICATION
1850         `else
1851         // synopsys translate_on
1852         `endif
1853         // synopsys translate_off
1854         ,
1855         .devclrn(),
1856         .devpor()
1857         // synopsys translate_on
1858         );
1859         defparam
1860                 ram_block3a_8.connectivity_checking = "OFF",
1861                 ram_block3a_8.logical_ram_name = "ALTSYNCRAM",
1862                 ram_block3a_8.mixed_port_feed_through_mode = "dont_care",
1863                 ram_block3a_8.operation_mode = "dual_port",
1864                 ram_block3a_8.port_a_address_width = 12,
1865                 ram_block3a_8.port_a_data_width = 1,
1866                 ram_block3a_8.port_a_first_address = 0,
1867                 ram_block3a_8.port_a_first_bit_number = 8,
1868                 ram_block3a_8.port_a_last_address = 4095,
1869                 ram_block3a_8.port_a_logical_ram_depth = 4096,
1870                 ram_block3a_8.port_a_logical_ram_width = 16,
1871                 ram_block3a_8.port_b_address_clear = "none",
1872                 ram_block3a_8.port_b_address_clock = "clock1",
1873                 ram_block3a_8.port_b_address_width = 12,
1874                 ram_block3a_8.port_b_data_out_clear = "none",
1875                 ram_block3a_8.port_b_data_out_clock = "none",
1876                 ram_block3a_8.port_b_data_width = 1,
1877                 ram_block3a_8.port_b_first_address = 0,
1878                 ram_block3a_8.port_b_first_bit_number = 8,
1879                 ram_block3a_8.port_b_last_address = 4095,
1880                 ram_block3a_8.port_b_logical_ram_depth = 4096,
1881                 ram_block3a_8.port_b_logical_ram_width = 16,
1882                 ram_block3a_8.port_b_read_enable_write_enable_clock = "clock1",
1883                 ram_block3a_8.ram_block_type = "auto",
1884                 ram_block3a_8.lpm_type = "cyclone_ram_block";
1885         cyclone_ram_block   ram_block3a_9
1886         (
1887         .clk0(clock0),
1888         .clk1(clock1),
1889         .ena0(wren_a),
1890         .ena1(clocken1),
1891         .portaaddr({address_a_wire[11:0]}),
1892         .portadatain({data_a[9]}),
1893         .portadataout(),
1894         .portawe(1'b1),
1895         .portbaddr({address_b_wire[11:0]}),
1896         .portbdataout(wire_ram_block3a_9portbdataout[0:0]),
1897         .portbrewe(1'b1)
1898         `ifdef FORMAL_VERIFICATION
1899         `else
1900         // synopsys translate_off
1901         `endif
1902         ,
1903         .clr0(1'b0),
1904         .clr1(1'b0),
1905         .portabyteenamasks(1'b1),
1906         .portbbyteenamasks(1'b1),
1907         .portbdatain(1'b0)
1908         `ifdef FORMAL_VERIFICATION
1909         `else
1910         // synopsys translate_on
1911         `endif
1912         // synopsys translate_off
1913         ,
1914         .devclrn(),
1915         .devpor()
1916         // synopsys translate_on
1917         );
1918         defparam
1919                 ram_block3a_9.connectivity_checking = "OFF",
1920                 ram_block3a_9.logical_ram_name = "ALTSYNCRAM",
1921                 ram_block3a_9.mixed_port_feed_through_mode = "dont_care",
1922                 ram_block3a_9.operation_mode = "dual_port",
1923                 ram_block3a_9.port_a_address_width = 12,
1924                 ram_block3a_9.port_a_data_width = 1,
1925                 ram_block3a_9.port_a_first_address = 0,
1926                 ram_block3a_9.port_a_first_bit_number = 9,
1927                 ram_block3a_9.port_a_last_address = 4095,
1928                 ram_block3a_9.port_a_logical_ram_depth = 4096,
1929                 ram_block3a_9.port_a_logical_ram_width = 16,
1930                 ram_block3a_9.port_b_address_clear = "none",
1931                 ram_block3a_9.port_b_address_clock = "clock1",
1932                 ram_block3a_9.port_b_address_width = 12,
1933                 ram_block3a_9.port_b_data_out_clear = "none",
1934                 ram_block3a_9.port_b_data_out_clock = "none",
1935                 ram_block3a_9.port_b_data_width = 1,
1936                 ram_block3a_9.port_b_first_address = 0,
1937                 ram_block3a_9.port_b_first_bit_number = 9,
1938                 ram_block3a_9.port_b_last_address = 4095,
1939                 ram_block3a_9.port_b_logical_ram_depth = 4096,
1940                 ram_block3a_9.port_b_logical_ram_width = 16,
1941                 ram_block3a_9.port_b_read_enable_write_enable_clock = "clock1",
1942                 ram_block3a_9.ram_block_type = "auto",
1943                 ram_block3a_9.lpm_type = "cyclone_ram_block";
1944         cyclone_ram_block   ram_block3a_10
1945         (
1946         .clk0(clock0),
1947         .clk1(clock1),
1948         .ena0(wren_a),
1949         .ena1(clocken1),
1950         .portaaddr({address_a_wire[11:0]}),
1951         .portadatain({data_a[10]}),
1952         .portadataout(),
1953         .portawe(1'b1),
1954         .portbaddr({address_b_wire[11:0]}),
1955         .portbdataout(wire_ram_block3a_10portbdataout[0:0]),
1956         .portbrewe(1'b1)
1957         `ifdef FORMAL_VERIFICATION
1958         `else
1959         // synopsys translate_off
1960         `endif
1961         ,
1962         .clr0(1'b0),
1963         .clr1(1'b0),
1964         .portabyteenamasks(1'b1),
1965         .portbbyteenamasks(1'b1),
1966         .portbdatain(1'b0)
1967         `ifdef FORMAL_VERIFICATION
1968         `else
1969         // synopsys translate_on
1970         `endif
1971         // synopsys translate_off
1972         ,
1973         .devclrn(),
1974         .devpor()
1975         // synopsys translate_on
1976         );
1977         defparam
1978                 ram_block3a_10.connectivity_checking = "OFF",
1979                 ram_block3a_10.logical_ram_name = "ALTSYNCRAM",
1980                 ram_block3a_10.mixed_port_feed_through_mode = "dont_care",
1981                 ram_block3a_10.operation_mode = "dual_port",
1982                 ram_block3a_10.port_a_address_width = 12,
1983                 ram_block3a_10.port_a_data_width = 1,
1984                 ram_block3a_10.port_a_first_address = 0,
1985                 ram_block3a_10.port_a_first_bit_number = 10,
1986                 ram_block3a_10.port_a_last_address = 4095,
1987                 ram_block3a_10.port_a_logical_ram_depth = 4096,
1988                 ram_block3a_10.port_a_logical_ram_width = 16,
1989                 ram_block3a_10.port_b_address_clear = "none",
1990                 ram_block3a_10.port_b_address_clock = "clock1",
1991                 ram_block3a_10.port_b_address_width = 12,
1992                 ram_block3a_10.port_b_data_out_clear = "none",
1993                 ram_block3a_10.port_b_data_out_clock = "none",
1994                 ram_block3a_10.port_b_data_width = 1,
1995                 ram_block3a_10.port_b_first_address = 0,
1996                 ram_block3a_10.port_b_first_bit_number = 10,
1997                 ram_block3a_10.port_b_last_address = 4095,
1998                 ram_block3a_10.port_b_logical_ram_depth = 4096,
1999                 ram_block3a_10.port_b_logical_ram_width = 16,
2000                 ram_block3a_10.port_b_read_enable_write_enable_clock = "clock1",
2001                 ram_block3a_10.ram_block_type = "auto",
2002                 ram_block3a_10.lpm_type = "cyclone_ram_block";
2003         cyclone_ram_block   ram_block3a_11
2004         (
2005         .clk0(clock0),
2006         .clk1(clock1),
2007         .ena0(wren_a),
2008         .ena1(clocken1),
2009         .portaaddr({address_a_wire[11:0]}),
2010         .portadatain({data_a[11]}),
2011         .portadataout(),
2012         .portawe(1'b1),
2013         .portbaddr({address_b_wire[11:0]}),
2014         .portbdataout(wire_ram_block3a_11portbdataout[0:0]),
2015         .portbrewe(1'b1)
2016         `ifdef FORMAL_VERIFICATION
2017         `else
2018         // synopsys translate_off
2019         `endif
2020         ,
2021         .clr0(1'b0),
2022         .clr1(1'b0),
2023         .portabyteenamasks(1'b1),
2024         .portbbyteenamasks(1'b1),
2025         .portbdatain(1'b0)
2026         `ifdef FORMAL_VERIFICATION
2027         `else
2028         // synopsys translate_on
2029         `endif
2030         // synopsys translate_off
2031         ,
2032         .devclrn(),
2033         .devpor()
2034         // synopsys translate_on
2035         );
2036         defparam
2037                 ram_block3a_11.connectivity_checking = "OFF",
2038                 ram_block3a_11.logical_ram_name = "ALTSYNCRAM",
2039                 ram_block3a_11.mixed_port_feed_through_mode = "dont_care",
2040                 ram_block3a_11.operation_mode = "dual_port",
2041                 ram_block3a_11.port_a_address_width = 12,
2042                 ram_block3a_11.port_a_data_width = 1,
2043                 ram_block3a_11.port_a_first_address = 0,
2044                 ram_block3a_11.port_a_first_bit_number = 11,
2045                 ram_block3a_11.port_a_last_address = 4095,
2046                 ram_block3a_11.port_a_logical_ram_depth = 4096,
2047                 ram_block3a_11.port_a_logical_ram_width = 16,
2048                 ram_block3a_11.port_b_address_clear = "none",
2049                 ram_block3a_11.port_b_address_clock = "clock1",
2050                 ram_block3a_11.port_b_address_width = 12,
2051                 ram_block3a_11.port_b_data_out_clear = "none",
2052                 ram_block3a_11.port_b_data_out_clock = "none",
2053                 ram_block3a_11.port_b_data_width = 1,
2054                 ram_block3a_11.port_b_first_address = 0,
2055                 ram_block3a_11.port_b_first_bit_number = 11,
2056                 ram_block3a_11.port_b_last_address = 4095,
2057                 ram_block3a_11.port_b_logical_ram_depth = 4096,
2058                 ram_block3a_11.port_b_logical_ram_width = 16,
2059                 ram_block3a_11.port_b_read_enable_write_enable_clock = "clock1",
2060                 ram_block3a_11.ram_block_type = "auto",
2061                 ram_block3a_11.lpm_type = "cyclone_ram_block";
2062         cyclone_ram_block   ram_block3a_12
2063         (
2064         .clk0(clock0),
2065         .clk1(clock1),
2066         .ena0(wren_a),
2067         .ena1(clocken1),
2068         .portaaddr({address_a_wire[11:0]}),
2069         .portadatain({data_a[12]}),
2070         .portadataout(),
2071         .portawe(1'b1),
2072         .portbaddr({address_b_wire[11:0]}),
2073         .portbdataout(wire_ram_block3a_12portbdataout[0:0]),
2074         .portbrewe(1'b1)
2075         `ifdef FORMAL_VERIFICATION
2076         `else
2077         // synopsys translate_off
2078         `endif
2079         ,
2080         .clr0(1'b0),
2081         .clr1(1'b0),
2082         .portabyteenamasks(1'b1),
2083         .portbbyteenamasks(1'b1),
2084         .portbdatain(1'b0)
2085         `ifdef FORMAL_VERIFICATION
2086         `else
2087         // synopsys translate_on
2088         `endif
2089         // synopsys translate_off
2090         ,
2091         .devclrn(),
2092         .devpor()
2093         // synopsys translate_on
2094         );
2095         defparam
2096                 ram_block3a_12.connectivity_checking = "OFF",
2097                 ram_block3a_12.logical_ram_name = "ALTSYNCRAM",
2098                 ram_block3a_12.mixed_port_feed_through_mode = "dont_care",
2099                 ram_block3a_12.operation_mode = "dual_port",
2100                 ram_block3a_12.port_a_address_width = 12,
2101                 ram_block3a_12.port_a_data_width = 1,
2102                 ram_block3a_12.port_a_first_address = 0,
2103                 ram_block3a_12.port_a_first_bit_number = 12,
2104                 ram_block3a_12.port_a_last_address = 4095,
2105                 ram_block3a_12.port_a_logical_ram_depth = 4096,
2106                 ram_block3a_12.port_a_logical_ram_width = 16,
2107                 ram_block3a_12.port_b_address_clear = "none",
2108                 ram_block3a_12.port_b_address_clock = "clock1",
2109                 ram_block3a_12.port_b_address_width = 12,
2110                 ram_block3a_12.port_b_data_out_clear = "none",
2111                 ram_block3a_12.port_b_data_out_clock = "none",
2112                 ram_block3a_12.port_b_data_width = 1,
2113                 ram_block3a_12.port_b_first_address = 0,
2114                 ram_block3a_12.port_b_first_bit_number = 12,
2115                 ram_block3a_12.port_b_last_address = 4095,
2116                 ram_block3a_12.port_b_logical_ram_depth = 4096,
2117                 ram_block3a_12.port_b_logical_ram_width = 16,
2118                 ram_block3a_12.port_b_read_enable_write_enable_clock = "clock1",
2119                 ram_block3a_12.ram_block_type = "auto",
2120                 ram_block3a_12.lpm_type = "cyclone_ram_block";
2121         cyclone_ram_block   ram_block3a_13
2122         (
2123         .clk0(clock0),
2124         .clk1(clock1),
2125         .ena0(wren_a),
2126         .ena1(clocken1),
2127         .portaaddr({address_a_wire[11:0]}),
2128         .portadatain({data_a[13]}),
2129         .portadataout(),
2130         .portawe(1'b1),
2131         .portbaddr({address_b_wire[11:0]}),
2132         .portbdataout(wire_ram_block3a_13portbdataout[0:0]),
2133         .portbrewe(1'b1)
2134         `ifdef FORMAL_VERIFICATION
2135         `else
2136         // synopsys translate_off
2137         `endif
2138         ,
2139         .clr0(1'b0),
2140         .clr1(1'b0),
2141         .portabyteenamasks(1'b1),
2142         .portbbyteenamasks(1'b1),
2143         .portbdatain(1'b0)
2144         `ifdef FORMAL_VERIFICATION
2145         `else
2146         // synopsys translate_on
2147         `endif
2148         // synopsys translate_off
2149         ,
2150         .devclrn(),
2151         .devpor()
2152         // synopsys translate_on
2153         );
2154         defparam
2155                 ram_block3a_13.connectivity_checking = "OFF",
2156                 ram_block3a_13.logical_ram_name = "ALTSYNCRAM",
2157                 ram_block3a_13.mixed_port_feed_through_mode = "dont_care",
2158                 ram_block3a_13.operation_mode = "dual_port",
2159                 ram_block3a_13.port_a_address_width = 12,
2160                 ram_block3a_13.port_a_data_width = 1,
2161                 ram_block3a_13.port_a_first_address = 0,
2162                 ram_block3a_13.port_a_first_bit_number = 13,
2163                 ram_block3a_13.port_a_last_address = 4095,
2164                 ram_block3a_13.port_a_logical_ram_depth = 4096,
2165                 ram_block3a_13.port_a_logical_ram_width = 16,
2166                 ram_block3a_13.port_b_address_clear = "none",
2167                 ram_block3a_13.port_b_address_clock = "clock1",
2168                 ram_block3a_13.port_b_address_width = 12,
2169                 ram_block3a_13.port_b_data_out_clear = "none",
2170                 ram_block3a_13.port_b_data_out_clock = "none",
2171                 ram_block3a_13.port_b_data_width = 1,
2172                 ram_block3a_13.port_b_first_address = 0,
2173                 ram_block3a_13.port_b_first_bit_number = 13,
2174                 ram_block3a_13.port_b_last_address = 4095,
2175                 ram_block3a_13.port_b_logical_ram_depth = 4096,
2176                 ram_block3a_13.port_b_logical_ram_width = 16,
2177                 ram_block3a_13.port_b_read_enable_write_enable_clock = "clock1",
2178                 ram_block3a_13.ram_block_type = "auto",
2179                 ram_block3a_13.lpm_type = "cyclone_ram_block";
2180         cyclone_ram_block   ram_block3a_14
2181         (
2182         .clk0(clock0),
2183         .clk1(clock1),
2184         .ena0(wren_a),
2185         .ena1(clocken1),
2186         .portaaddr({address_a_wire[11:0]}),
2187         .portadatain({data_a[14]}),
2188         .portadataout(),
2189         .portawe(1'b1),
2190         .portbaddr({address_b_wire[11:0]}),
2191         .portbdataout(wire_ram_block3a_14portbdataout[0:0]),
2192         .portbrewe(1'b1)
2193         `ifdef FORMAL_VERIFICATION
2194         `else
2195         // synopsys translate_off
2196         `endif
2197         ,
2198         .clr0(1'b0),
2199         .clr1(1'b0),
2200         .portabyteenamasks(1'b1),
2201         .portbbyteenamasks(1'b1),
2202         .portbdatain(1'b0)
2203         `ifdef FORMAL_VERIFICATION
2204         `else
2205         // synopsys translate_on
2206         `endif
2207         // synopsys translate_off
2208         ,
2209         .devclrn(),
2210         .devpor()
2211         // synopsys translate_on
2212         );
2213         defparam
2214                 ram_block3a_14.connectivity_checking = "OFF",
2215                 ram_block3a_14.logical_ram_name = "ALTSYNCRAM",
2216                 ram_block3a_14.mixed_port_feed_through_mode = "dont_care",
2217                 ram_block3a_14.operation_mode = "dual_port",
2218                 ram_block3a_14.port_a_address_width = 12,
2219                 ram_block3a_14.port_a_data_width = 1,
2220                 ram_block3a_14.port_a_first_address = 0,
2221                 ram_block3a_14.port_a_first_bit_number = 14,
2222                 ram_block3a_14.port_a_last_address = 4095,
2223                 ram_block3a_14.port_a_logical_ram_depth = 4096,
2224                 ram_block3a_14.port_a_logical_ram_width = 16,
2225                 ram_block3a_14.port_b_address_clear = "none",
2226                 ram_block3a_14.port_b_address_clock = "clock1",
2227                 ram_block3a_14.port_b_address_width = 12,
2228                 ram_block3a_14.port_b_data_out_clear = "none",
2229                 ram_block3a_14.port_b_data_out_clock = "none",
2230                 ram_block3a_14.port_b_data_width = 1,
2231                 ram_block3a_14.port_b_first_address = 0,
2232                 ram_block3a_14.port_b_first_bit_number = 14,
2233                 ram_block3a_14.port_b_last_address = 4095,
2234                 ram_block3a_14.port_b_logical_ram_depth = 4096,
2235                 ram_block3a_14.port_b_logical_ram_width = 16,
2236                 ram_block3a_14.port_b_read_enable_write_enable_clock = "clock1",
2237                 ram_block3a_14.ram_block_type = "auto",
2238                 ram_block3a_14.lpm_type = "cyclone_ram_block";
2239         cyclone_ram_block   ram_block3a_15
2240         (
2241         .clk0(clock0),
2242         .clk1(clock1),
2243         .ena0(wren_a),
2244         .ena1(clocken1),
2245         .portaaddr({address_a_wire[11:0]}),
2246         .portadatain({data_a[15]}),
2247         .portadataout(),
2248         .portawe(1'b1),
2249         .portbaddr({address_b_wire[11:0]}),
2250         .portbdataout(wire_ram_block3a_15portbdataout[0:0]),
2251         .portbrewe(1'b1)
2252         `ifdef FORMAL_VERIFICATION
2253         `else
2254         // synopsys translate_off
2255         `endif
2256         ,
2257         .clr0(1'b0),
2258         .clr1(1'b0),
2259         .portabyteenamasks(1'b1),
2260         .portbbyteenamasks(1'b1),
2261         .portbdatain(1'b0)
2262         `ifdef FORMAL_VERIFICATION
2263         `else
2264         // synopsys translate_on
2265         `endif
2266         // synopsys translate_off
2267         ,
2268         .devclrn(),
2269         .devpor()
2270         // synopsys translate_on
2271         );
2272         defparam
2273                 ram_block3a_15.connectivity_checking = "OFF",
2274                 ram_block3a_15.logical_ram_name = "ALTSYNCRAM",
2275                 ram_block3a_15.mixed_port_feed_through_mode = "dont_care",
2276                 ram_block3a_15.operation_mode = "dual_port",
2277                 ram_block3a_15.port_a_address_width = 12,
2278                 ram_block3a_15.port_a_data_width = 1,
2279                 ram_block3a_15.port_a_first_address = 0,
2280                 ram_block3a_15.port_a_first_bit_number = 15,
2281                 ram_block3a_15.port_a_last_address = 4095,
2282                 ram_block3a_15.port_a_logical_ram_depth = 4096,
2283                 ram_block3a_15.port_a_logical_ram_width = 16,
2284                 ram_block3a_15.port_b_address_clear = "none",
2285                 ram_block3a_15.port_b_address_clock = "clock1",
2286                 ram_block3a_15.port_b_address_width = 12,
2287                 ram_block3a_15.port_b_data_out_clear = "none",
2288                 ram_block3a_15.port_b_data_out_clock = "none",
2289                 ram_block3a_15.port_b_data_width = 1,
2290                 ram_block3a_15.port_b_first_address = 0,
2291                 ram_block3a_15.port_b_first_bit_number = 15,
2292                 ram_block3a_15.port_b_last_address = 4095,
2293                 ram_block3a_15.port_b_logical_ram_depth = 4096,
2294                 ram_block3a_15.port_b_logical_ram_width = 16,
2295                 ram_block3a_15.port_b_read_enable_write_enable_clock = "clock1",
2296                 ram_block3a_15.ram_block_type = "auto",
2297                 ram_block3a_15.lpm_type = "cyclone_ram_block";
2298         assign
2299                 address_a_wire = address_a,
2300                 address_b_wire = address_b,
2301                 q_b = {wire_ram_block3a_15portbdataout[0], wire_ram_block3a_14portbdataout[0], wire_ram_block3a_13portbdataout[0], wire_ram_block3a_12portbdataout[0], wire_ram_block3a_11portbdataout[0], wire_ram_block3a_10portbdataout[0], wire_ram_block3a_9portbdataout[0], wire_ram_block3a_8portbdataout[0], wire_ram_block3a_7portbdataout[0], wire_ram_block3a_6portbdataout[0], wire_ram_block3a_5portbdataout[0], wire_ram_block3a_4portbdataout[0], wire_ram_block3a_3portbdataout[0], wire_ram_block3a_2portbdataout[0], wire_ram_block3a_1portbdataout[0], wire_ram_block3a_0portbdataout[0]};
2302 endmodule //fifo_4k_altsyncram_8pl
2303
2304
2305 //dffpipe DELAY=1 WIDTH=12 clock clrn d q
2306 //VERSION_BEGIN 5.0 cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ  VERSION_END
2307
2308 //synthesis_resources = lut 12
2309 //synopsys translate_off
2310 `timescale 1 ps / 1 ps
2311 //synopsys translate_on
2312 module  fifo_4k_dffpipe_bb3
2313         (
2314         clock,
2315         clrn,
2316         d,
2317         q) /* synthesis synthesis_clearbox=1 */
2318                 /* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF" */;
2319         input   clock;
2320         input   clrn;
2321         input   [11:0]  d;
2322         output   [11:0]  q;
2323
2324         wire    [11:0]  wire_dffe4a_D;
2325         reg     [11:0]  dffe4a;
2326         wire ena;
2327         wire prn;
2328         wire sclr;
2329
2330         // synopsys translate_off
2331         initial
2332                 dffe4a[0:0] = 0;
2333         // synopsys translate_on
2334         always @ ( posedge clock or  negedge prn or  negedge clrn)
2335                 if (prn == 1'b0) dffe4a[0:0] <= 1'b1;
2336                 else if (clrn == 1'b0) dffe4a[0:0] <= 1'b0;
2337                 else if  (ena == 1'b1)   dffe4a[0:0] <= wire_dffe4a_D[0:0];
2338         // synopsys translate_off
2339         initial
2340                 dffe4a[1:1] = 0;
2341         // synopsys translate_on
2342         always @ ( posedge clock or  negedge prn or  negedge clrn)
2343                 if (prn == 1'b0) dffe4a[1:1] <= 1'b1;
2344                 else if (clrn == 1'b0) dffe4a[1:1] <= 1'b0;
2345                 else if  (ena == 1'b1)   dffe4a[1:1] <= wire_dffe4a_D[1:1];
2346         // synopsys translate_off
2347         initial
2348                 dffe4a[2:2] = 0;
2349         // synopsys translate_on
2350         always @ ( posedge clock or  negedge prn or  negedge clrn)
2351                 if (prn == 1'b0) dffe4a[2:2] <= 1'b1;
2352                 else if (clrn == 1'b0) dffe4a[2:2] <= 1'b0;
2353                 else if  (ena == 1'b1)   dffe4a[2:2] <= wire_dffe4a_D[2:2];
2354         // synopsys translate_off
2355         initial
2356                 dffe4a[3:3] = 0;
2357         // synopsys translate_on
2358         always @ ( posedge clock or  negedge prn or  negedge clrn)
2359                 if (prn == 1'b0) dffe4a[3:3] <= 1'b1;
2360                 else if (clrn == 1'b0) dffe4a[3:3] <= 1'b0;
2361                 else if  (ena == 1'b1)   dffe4a[3:3] <= wire_dffe4a_D[3:3];
2362         // synopsys translate_off
2363         initial
2364                 dffe4a[4:4] = 0;
2365         // synopsys translate_on
2366         always @ ( posedge clock or  negedge prn or  negedge clrn)
2367                 if (prn == 1'b0) dffe4a[4:4] <= 1'b1;
2368                 else if (clrn == 1'b0) dffe4a[4:4] <= 1'b0;
2369                 else if  (ena == 1'b1)   dffe4a[4:4] <= wire_dffe4a_D[4:4];
2370         // synopsys translate_off
2371         initial
2372                 dffe4a[5:5] = 0;
2373         // synopsys translate_on
2374         always @ ( posedge clock or  negedge prn or  negedge clrn)
2375                 if (prn == 1'b0) dffe4a[5:5] <= 1'b1;
2376                 else if (clrn == 1'b0) dffe4a[5:5] <= 1'b0;
2377                 else if  (ena == 1'b1)   dffe4a[5:5] <= wire_dffe4a_D[5:5];
2378         // synopsys translate_off
2379         initial
2380                 dffe4a[6:6] = 0;
2381         // synopsys translate_on
2382         always @ ( posedge clock or  negedge prn or  negedge clrn)
2383                 if (prn == 1'b0) dffe4a[6:6] <= 1'b1;
2384                 else if (clrn == 1'b0) dffe4a[6:6] <= 1'b0;
2385                 else if  (ena == 1'b1)   dffe4a[6:6] <= wire_dffe4a_D[6:6];
2386         // synopsys translate_off
2387         initial
2388                 dffe4a[7:7] = 0;
2389         // synopsys translate_on
2390         always @ ( posedge clock or  negedge prn or  negedge clrn)
2391                 if (prn == 1'b0) dffe4a[7:7] <= 1'b1;
2392                 else if (clrn == 1'b0) dffe4a[7:7] <= 1'b0;
2393                 else if  (ena == 1'b1)   dffe4a[7:7] <= wire_dffe4a_D[7:7];
2394         // synopsys translate_off
2395         initial
2396                 dffe4a[8:8] = 0;
2397         // synopsys translate_on
2398         always @ ( posedge clock or  negedge prn or  negedge clrn)
2399                 if (prn == 1'b0) dffe4a[8:8] <= 1'b1;
2400                 else if (clrn == 1'b0) dffe4a[8:8] <= 1'b0;
2401                 else if  (ena == 1'b1)   dffe4a[8:8] <= wire_dffe4a_D[8:8];
2402         // synopsys translate_off
2403         initial
2404                 dffe4a[9:9] = 0;
2405         // synopsys translate_on
2406         always @ ( posedge clock or  negedge prn or  negedge clrn)
2407                 if (prn == 1'b0) dffe4a[9:9] <= 1'b1;
2408                 else if (clrn == 1'b0) dffe4a[9:9] <= 1'b0;
2409                 else if  (ena == 1'b1)   dffe4a[9:9] <= wire_dffe4a_D[9:9];
2410         // synopsys translate_off
2411         initial
2412                 dffe4a[10:10] = 0;
2413         // synopsys translate_on
2414         always @ ( posedge clock or  negedge prn or  negedge clrn)
2415                 if (prn == 1'b0) dffe4a[10:10] <= 1'b1;
2416                 else if (clrn == 1'b0) dffe4a[10:10] <= 1'b0;
2417                 else if  (ena == 1'b1)   dffe4a[10:10] <= wire_dffe4a_D[10:10];
2418         // synopsys translate_off
2419         initial
2420                 dffe4a[11:11] = 0;
2421         // synopsys translate_on
2422         always @ ( posedge clock or  negedge prn or  negedge clrn)
2423                 if (prn == 1'b0) dffe4a[11:11] <= 1'b1;
2424                 else if (clrn == 1'b0) dffe4a[11:11] <= 1'b0;
2425                 else if  (ena == 1'b1)   dffe4a[11:11] <= wire_dffe4a_D[11:11];
2426         assign
2427                 wire_dffe4a_D = (d & {12{(~ sclr)}});
2428         assign
2429                 ena = 1'b1,
2430                 prn = 1'b1,
2431                 q = dffe4a,
2432                 sclr = 1'b0;
2433 endmodule //fifo_4k_dffpipe_bb3
2434
2435
2436 //dffpipe WIDTH=12 clock clrn d q
2437 //VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_altdpram 2004:11:30:11:29:56:SJ cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_dcfifo 2005:03:07:17:11:14:SJ cbx_fifo_common 2004:12:13:14:26:24:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_counter 2005:02:02:04:37:10:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_scfifo 2005:03:10:10:52:20:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ  VERSION_END
2438
2439
2440 //dffpipe WIDTH=12 clock clrn d q
2441 //VERSION_BEGIN 5.0 cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ  VERSION_END
2442
2443 //synthesis_resources = lut 12
2444 //synopsys translate_off
2445 `timescale 1 ps / 1 ps
2446 //synopsys translate_on
2447 module  fifo_4k_dffpipe_em2
2448         (
2449         clock,
2450         clrn,
2451         d,
2452         q) /* synthesis synthesis_clearbox=1 */
2453                 /* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF" */;
2454         input   clock;
2455         input   clrn;
2456         input   [11:0]  d;
2457         output   [11:0]  q;
2458
2459         wire    [11:0]  wire_dffe6a_D;
2460         reg     [11:0]  dffe6a;
2461         wire ena;
2462         wire prn;
2463         wire sclr;
2464
2465         // synopsys translate_off
2466         initial
2467                 dffe6a[0:0] = 0;
2468         // synopsys translate_on
2469         always @ ( posedge clock or  negedge prn or  negedge clrn)
2470                 if (prn == 1'b0) dffe6a[0:0] <= 1'b1;
2471                 else if (clrn == 1'b0) dffe6a[0:0] <= 1'b0;
2472                 else if  (ena == 1'b1)   dffe6a[0:0] <= wire_dffe6a_D[0:0];
2473         // synopsys translate_off
2474         initial
2475                 dffe6a[1:1] = 0;
2476         // synopsys translate_on
2477         always @ ( posedge clock or  negedge prn or  negedge clrn)
2478                 if (prn == 1'b0) dffe6a[1:1] <= 1'b1;
2479                 else if (clrn == 1'b0) dffe6a[1:1] <= 1'b0;
2480                 else if  (ena == 1'b1)   dffe6a[1:1] <= wire_dffe6a_D[1:1];
2481         // synopsys translate_off
2482         initial
2483                 dffe6a[2:2] = 0;
2484         // synopsys translate_on
2485         always @ ( posedge clock or  negedge prn or  negedge clrn)
2486                 if (prn == 1'b0) dffe6a[2:2] <= 1'b1;
2487                 else if (clrn == 1'b0) dffe6a[2:2] <= 1'b0;
2488                 else if  (ena == 1'b1)   dffe6a[2:2] <= wire_dffe6a_D[2:2];
2489         // synopsys translate_off
2490         initial
2491                 dffe6a[3:3] = 0;
2492         // synopsys translate_on
2493         always @ ( posedge clock or  negedge prn or  negedge clrn)
2494                 if (prn == 1'b0) dffe6a[3:3] <= 1'b1;
2495                 else if (clrn == 1'b0) dffe6a[3:3] <= 1'b0;
2496                 else if  (ena == 1'b1)   dffe6a[3:3] <= wire_dffe6a_D[3:3];
2497         // synopsys translate_off
2498         initial
2499                 dffe6a[4:4] = 0;
2500         // synopsys translate_on
2501         always @ ( posedge clock or  negedge prn or  negedge clrn)
2502                 if (prn == 1'b0) dffe6a[4:4] <= 1'b1;
2503                 else if (clrn == 1'b0) dffe6a[4:4] <= 1'b0;
2504                 else if  (ena == 1'b1)   dffe6a[4:4] <= wire_dffe6a_D[4:4];
2505         // synopsys translate_off
2506         initial
2507                 dffe6a[5:5] = 0;
2508         // synopsys translate_on
2509         always @ ( posedge clock or  negedge prn or  negedge clrn)
2510                 if (prn == 1'b0) dffe6a[5:5] <= 1'b1;
2511                 else if (clrn == 1'b0) dffe6a[5:5] <= 1'b0;
2512                 else if  (ena == 1'b1)   dffe6a[5:5] <= wire_dffe6a_D[5:5];
2513         // synopsys translate_off
2514         initial
2515                 dffe6a[6:6] = 0;
2516         // synopsys translate_on
2517         always @ ( posedge clock or  negedge prn or  negedge clrn)
2518                 if (prn == 1'b0) dffe6a[6:6] <= 1'b1;
2519                 else if (clrn == 1'b0) dffe6a[6:6] <= 1'b0;
2520                 else if  (ena == 1'b1)   dffe6a[6:6] <= wire_dffe6a_D[6:6];
2521         // synopsys translate_off
2522         initial
2523                 dffe6a[7:7] = 0;
2524         // synopsys translate_on
2525         always @ ( posedge clock or  negedge prn or  negedge clrn)
2526                 if (prn == 1'b0) dffe6a[7:7] <= 1'b1;
2527                 else if (clrn == 1'b0) dffe6a[7:7] <= 1'b0;
2528                 else if  (ena == 1'b1)   dffe6a[7:7] <= wire_dffe6a_D[7:7];
2529         // synopsys translate_off
2530         initial
2531                 dffe6a[8:8] = 0;
2532         // synopsys translate_on
2533         always @ ( posedge clock or  negedge prn or  negedge clrn)
2534                 if (prn == 1'b0) dffe6a[8:8] <= 1'b1;
2535                 else if (clrn == 1'b0) dffe6a[8:8] <= 1'b0;
2536                 else if  (ena == 1'b1)   dffe6a[8:8] <= wire_dffe6a_D[8:8];
2537         // synopsys translate_off
2538         initial
2539                 dffe6a[9:9] = 0;
2540         // synopsys translate_on
2541         always @ ( posedge clock or  negedge prn or  negedge clrn)
2542                 if (prn == 1'b0) dffe6a[9:9] <= 1'b1;
2543                 else if (clrn == 1'b0) dffe6a[9:9] <= 1'b0;
2544                 else if  (ena == 1'b1)   dffe6a[9:9] <= wire_dffe6a_D[9:9];
2545         // synopsys translate_off
2546         initial
2547                 dffe6a[10:10] = 0;
2548         // synopsys translate_on
2549         always @ ( posedge clock or  negedge prn or  negedge clrn)
2550                 if (prn == 1'b0) dffe6a[10:10] <= 1'b1;
2551                 else if (clrn == 1'b0) dffe6a[10:10] <= 1'b0;
2552                 else if  (ena == 1'b1)   dffe6a[10:10] <= wire_dffe6a_D[10:10];
2553         // synopsys translate_off
2554         initial
2555                 dffe6a[11:11] = 0;
2556         // synopsys translate_on
2557         always @ ( posedge clock or  negedge prn or  negedge clrn)
2558                 if (prn == 1'b0) dffe6a[11:11] <= 1'b1;
2559                 else if (clrn == 1'b0) dffe6a[11:11] <= 1'b0;
2560                 else if  (ena == 1'b1)   dffe6a[11:11] <= wire_dffe6a_D[11:11];
2561         assign
2562                 wire_dffe6a_D = (d & {12{(~ sclr)}});
2563         assign
2564                 ena = 1'b1,
2565                 prn = 1'b1,
2566                 q = dffe6a,
2567                 sclr = 1'b0;
2568 endmodule //fifo_4k_dffpipe_em2
2569
2570 //synthesis_resources = lut 12
2571 //synopsys translate_off
2572 `timescale 1 ps / 1 ps
2573 //synopsys translate_on
2574 module  fifo_4k_alt_synch_pipe_em2
2575         (
2576         clock,
2577         clrn,
2578         d,
2579         q) /* synthesis synthesis_clearbox=1 */
2580                 /* synthesis ALTERA_ATTRIBUTE="X_ON_VIOLATION_OPTION=OFF" */;
2581         input   clock;
2582         input   clrn;
2583         input   [11:0]  d;
2584         output   [11:0]  q;
2585
2586         wire  [11:0]   wire_dffpipe5_q;
2587
2588         fifo_4k_dffpipe_em2   dffpipe5
2589         (
2590         .clock(clock),
2591         .clrn(clrn),
2592         .d(d),
2593         .q(wire_dffpipe5_q));
2594         assign
2595                 q = wire_dffpipe5_q;
2596 endmodule //fifo_4k_alt_synch_pipe_em2
2597
2598
2599 //lpm_add_sub DEVICE_FAMILY="Cyclone" LPM_DIRECTION="SUB" LPM_WIDTH=12 dataa datab result
2600 //VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ  VERSION_END
2601
2602 //synthesis_resources = lut 12
2603 //synopsys translate_off
2604 `timescale 1 ps / 1 ps
2605 //synopsys translate_on
2606 module  fifo_4k_add_sub_b18
2607         (
2608         dataa,
2609         datab,
2610         result) /* synthesis synthesis_clearbox=1 */;
2611         input   [11:0]  dataa;
2612         input   [11:0]  datab;
2613         output   [11:0]  result;
2614
2615         wire  [11:0]   wire_add_sub_cella_combout;
2616         wire  [0:0]   wire_add_sub_cella_0cout;
2617         wire  [0:0]   wire_add_sub_cella_1cout;
2618         wire  [0:0]   wire_add_sub_cella_2cout;
2619         wire  [0:0]   wire_add_sub_cella_3cout;
2620         wire  [0:0]   wire_add_sub_cella_4cout;
2621         wire  [0:0]   wire_add_sub_cella_5cout;
2622         wire  [0:0]   wire_add_sub_cella_6cout;
2623         wire  [0:0]   wire_add_sub_cella_7cout;
2624         wire  [0:0]   wire_add_sub_cella_8cout;
2625         wire  [0:0]   wire_add_sub_cella_9cout;
2626         wire  [0:0]   wire_add_sub_cella_10cout;
2627         wire  [11:0]   wire_add_sub_cella_dataa;
2628         wire  [11:0]   wire_add_sub_cella_datab;
2629
2630         cyclone_lcell   add_sub_cella_0
2631         (
2632         .cin(1'b1),
2633         .combout(wire_add_sub_cella_combout[0:0]),
2634         .cout(wire_add_sub_cella_0cout[0:0]),
2635         .dataa(wire_add_sub_cella_dataa[0:0]),
2636         .datab(wire_add_sub_cella_datab[0:0]),
2637         .regout()
2638         `ifdef FORMAL_VERIFICATION
2639         `else
2640         // synopsys translate_off
2641         `endif
2642         ,
2643         .aclr(1'b0),
2644         .aload(1'b0),
2645         .clk(1'b1),
2646         .datac(1'b1),
2647         .datad(1'b1),
2648         .ena(1'b1),
2649         .inverta(1'b0),
2650         .regcascin(1'b0),
2651         .sclr(1'b0),
2652         .sload(1'b0)
2653         `ifdef FORMAL_VERIFICATION
2654         `else
2655         // synopsys translate_on
2656         `endif
2657         // synopsys translate_off
2658         ,
2659         .cin0(),
2660         .cin1(),
2661         .cout0(),
2662         .cout1(),
2663         .devclrn(),
2664         .devpor()
2665         // synopsys translate_on
2666         );
2667         defparam
2668                 add_sub_cella_0.cin_used = "true",
2669                 add_sub_cella_0.lut_mask = "69b2",
2670                 add_sub_cella_0.operation_mode = "arithmetic",
2671                 add_sub_cella_0.sum_lutc_input = "cin",
2672                 add_sub_cella_0.lpm_type = "cyclone_lcell";
2673         cyclone_lcell   add_sub_cella_1
2674         (
2675         .cin(wire_add_sub_cella_0cout[0:0]),
2676         .combout(wire_add_sub_cella_combout[1:1]),
2677         .cout(wire_add_sub_cella_1cout[0:0]),
2678         .dataa(wire_add_sub_cella_dataa[1:1]),
2679         .datab(wire_add_sub_cella_datab[1:1]),
2680         .regout()
2681         `ifdef FORMAL_VERIFICATION
2682         `else
2683         // synopsys translate_off
2684         `endif
2685         ,
2686         .aclr(1'b0),
2687         .aload(1'b0),
2688         .clk(1'b1),
2689         .datac(1'b1),
2690         .datad(1'b1),
2691         .ena(1'b1),
2692         .inverta(1'b0),
2693         .regcascin(1'b0),
2694         .sclr(1'b0),
2695         .sload(1'b0)
2696         `ifdef FORMAL_VERIFICATION
2697         `else
2698         // synopsys translate_on
2699         `endif
2700         // synopsys translate_off
2701         ,
2702         .cin0(),
2703         .cin1(),
2704         .cout0(),
2705         .cout1(),
2706         .devclrn(),
2707         .devpor()
2708         // synopsys translate_on
2709         );
2710         defparam
2711                 add_sub_cella_1.cin_used = "true",
2712                 add_sub_cella_1.lut_mask = "69b2",
2713                 add_sub_cella_1.operation_mode = "arithmetic",
2714                 add_sub_cella_1.sum_lutc_input = "cin",
2715                 add_sub_cella_1.lpm_type = "cyclone_lcell";
2716         cyclone_lcell   add_sub_cella_2
2717         (
2718         .cin(wire_add_sub_cella_1cout[0:0]),
2719         .combout(wire_add_sub_cella_combout[2:2]),
2720         .cout(wire_add_sub_cella_2cout[0:0]),
2721         .dataa(wire_add_sub_cella_dataa[2:2]),
2722         .datab(wire_add_sub_cella_datab[2:2]),
2723         .regout()
2724         `ifdef FORMAL_VERIFICATION
2725         `else
2726         // synopsys translate_off
2727         `endif
2728         ,
2729         .aclr(1'b0),
2730         .aload(1'b0),
2731         .clk(1'b1),
2732         .datac(1'b1),
2733         .datad(1'b1),
2734         .ena(1'b1),
2735         .inverta(1'b0),
2736         .regcascin(1'b0),
2737         .sclr(1'b0),
2738         .sload(1'b0)
2739         `ifdef FORMAL_VERIFICATION
2740         `else
2741         // synopsys translate_on
2742         `endif
2743         // synopsys translate_off
2744         ,
2745         .cin0(),
2746         .cin1(),
2747         .cout0(),
2748         .cout1(),
2749         .devclrn(),
2750         .devpor()
2751         // synopsys translate_on
2752         );
2753         defparam
2754                 add_sub_cella_2.cin_used = "true",
2755                 add_sub_cella_2.lut_mask = "69b2",
2756                 add_sub_cella_2.operation_mode = "arithmetic",
2757                 add_sub_cella_2.sum_lutc_input = "cin",
2758                 add_sub_cella_2.lpm_type = "cyclone_lcell";
2759         cyclone_lcell   add_sub_cella_3
2760         (
2761         .cin(wire_add_sub_cella_2cout[0:0]),
2762         .combout(wire_add_sub_cella_combout[3:3]),
2763         .cout(wire_add_sub_cella_3cout[0:0]),
2764         .dataa(wire_add_sub_cella_dataa[3:3]),
2765         .datab(wire_add_sub_cella_datab[3:3]),
2766         .regout()
2767         `ifdef FORMAL_VERIFICATION
2768         `else
2769         // synopsys translate_off
2770         `endif
2771         ,
2772         .aclr(1'b0),
2773         .aload(1'b0),
2774         .clk(1'b1),
2775         .datac(1'b1),
2776         .datad(1'b1),
2777         .ena(1'b1),
2778         .inverta(1'b0),
2779         .regcascin(1'b0),
2780         .sclr(1'b0),
2781         .sload(1'b0)
2782         `ifdef FORMAL_VERIFICATION
2783         `else
2784         // synopsys translate_on
2785         `endif
2786         // synopsys translate_off
2787         ,
2788         .cin0(),
2789         .cin1(),
2790         .cout0(),
2791         .cout1(),
2792         .devclrn(),
2793         .devpor()
2794         // synopsys translate_on
2795         );
2796         defparam
2797                 add_sub_cella_3.cin_used = "true",
2798                 add_sub_cella_3.lut_mask = "69b2",
2799                 add_sub_cella_3.operation_mode = "arithmetic",
2800                 add_sub_cella_3.sum_lutc_input = "cin",
2801                 add_sub_cella_3.lpm_type = "cyclone_lcell";
2802         cyclone_lcell   add_sub_cella_4
2803         (
2804         .cin(wire_add_sub_cella_3cout[0:0]),
2805         .combout(wire_add_sub_cella_combout[4:4]),
2806         .cout(wire_add_sub_cella_4cout[0:0]),
2807         .dataa(wire_add_sub_cella_dataa[4:4]),
2808         .datab(wire_add_sub_cella_datab[4:4]),
2809         .regout()
2810         `ifdef FORMAL_VERIFICATION
2811         `else
2812         // synopsys translate_off
2813         `endif
2814         ,
2815         .aclr(1'b0),
2816         .aload(1'b0),
2817         .clk(1'b1),
2818         .datac(1'b1),
2819         .datad(1'b1),
2820         .ena(1'b1),
2821         .inverta(1'b0),
2822         .regcascin(1'b0),
2823         .sclr(1'b0),
2824         .sload(1'b0)
2825         `ifdef FORMAL_VERIFICATION
2826         `else
2827         // synopsys translate_on
2828         `endif
2829         // synopsys translate_off
2830         ,
2831         .cin0(),
2832         .cin1(),
2833         .cout0(),
2834         .cout1(),
2835         .devclrn(),
2836         .devpor()
2837         // synopsys translate_on
2838         );
2839         defparam
2840                 add_sub_cella_4.cin_used = "true",
2841                 add_sub_cella_4.lut_mask = "69b2",
2842                 add_sub_cella_4.operation_mode = "arithmetic",
2843                 add_sub_cella_4.sum_lutc_input = "cin",
2844                 add_sub_cella_4.lpm_type = "cyclone_lcell";
2845         cyclone_lcell   add_sub_cella_5
2846         (
2847         .cin(wire_add_sub_cella_4cout[0:0]),
2848         .combout(wire_add_sub_cella_combout[5:5]),
2849         .cout(wire_add_sub_cella_5cout[0:0]),
2850         .dataa(wire_add_sub_cella_dataa[5:5]),
2851         .datab(wire_add_sub_cella_datab[5:5]),
2852         .regout()
2853         `ifdef FORMAL_VERIFICATION
2854         `else
2855         // synopsys translate_off
2856         `endif
2857         ,
2858         .aclr(1'b0),
2859         .aload(1'b0),
2860         .clk(1'b1),
2861         .datac(1'b1),
2862         .datad(1'b1),
2863         .ena(1'b1),
2864         .inverta(1'b0),
2865         .regcascin(1'b0),
2866         .sclr(1'b0),
2867         .sload(1'b0)
2868         `ifdef FORMAL_VERIFICATION
2869         `else
2870         // synopsys translate_on
2871         `endif
2872         // synopsys translate_off
2873         ,
2874         .cin0(),
2875         .cin1(),
2876         .cout0(),
2877         .cout1(),
2878         .devclrn(),
2879         .devpor()
2880         // synopsys translate_on
2881         );
2882         defparam
2883                 add_sub_cella_5.cin_used = "true",
2884                 add_sub_cella_5.lut_mask = "69b2",
2885                 add_sub_cella_5.operation_mode = "arithmetic",
2886                 add_sub_cella_5.sum_lutc_input = "cin",
2887                 add_sub_cella_5.lpm_type = "cyclone_lcell";
2888         cyclone_lcell   add_sub_cella_6
2889         (
2890         .cin(wire_add_sub_cella_5cout[0:0]),
2891         .combout(wire_add_sub_cella_combout[6:6]),
2892         .cout(wire_add_sub_cella_6cout[0:0]),
2893         .dataa(wire_add_sub_cella_dataa[6:6]),
2894         .datab(wire_add_sub_cella_datab[6:6]),
2895         .regout()
2896         `ifdef FORMAL_VERIFICATION
2897         `else
2898         // synopsys translate_off
2899         `endif
2900         ,
2901         .aclr(1'b0),
2902         .aload(1'b0),
2903         .clk(1'b1),
2904         .datac(1'b1),
2905         .datad(1'b1),
2906         .ena(1'b1),
2907         .inverta(1'b0),
2908         .regcascin(1'b0),
2909         .sclr(1'b0),
2910         .sload(1'b0)
2911         `ifdef FORMAL_VERIFICATION
2912         `else
2913         // synopsys translate_on
2914         `endif
2915         // synopsys translate_off
2916         ,
2917         .cin0(),
2918         .cin1(),
2919         .cout0(),
2920         .cout1(),
2921         .devclrn(),
2922         .devpor()
2923         // synopsys translate_on
2924         );
2925         defparam
2926                 add_sub_cella_6.cin_used = "true",
2927                 add_sub_cella_6.lut_mask = "69b2",
2928                 add_sub_cella_6.operation_mode = "arithmetic",
2929                 add_sub_cella_6.sum_lutc_input = "cin",
2930                 add_sub_cella_6.lpm_type = "cyclone_lcell";
2931         cyclone_lcell   add_sub_cella_7
2932         (
2933         .cin(wire_add_sub_cella_6cout[0:0]),
2934         .combout(wire_add_sub_cella_combout[7:7]),
2935         .cout(wire_add_sub_cella_7cout[0:0]),
2936         .dataa(wire_add_sub_cella_dataa[7:7]),
2937         .datab(wire_add_sub_cella_datab[7:7]),
2938         .regout()
2939         `ifdef FORMAL_VERIFICATION
2940         `else
2941         // synopsys translate_off
2942         `endif
2943         ,
2944         .aclr(1'b0),
2945         .aload(1'b0),
2946         .clk(1'b1),
2947         .datac(1'b1),
2948         .datad(1'b1),
2949         .ena(1'b1),
2950         .inverta(1'b0),
2951         .regcascin(1'b0),
2952         .sclr(1'b0),
2953         .sload(1'b0)
2954         `ifdef FORMAL_VERIFICATION
2955         `else
2956         // synopsys translate_on
2957         `endif
2958         // synopsys translate_off
2959         ,
2960         .cin0(),
2961         .cin1(),
2962         .cout0(),
2963         .cout1(),
2964         .devclrn(),
2965         .devpor()
2966         // synopsys translate_on
2967         );
2968         defparam
2969                 add_sub_cella_7.cin_used = "true",
2970                 add_sub_cella_7.lut_mask = "69b2",
2971                 add_sub_cella_7.operation_mode = "arithmetic",
2972                 add_sub_cella_7.sum_lutc_input = "cin",
2973                 add_sub_cella_7.lpm_type = "cyclone_lcell";
2974         cyclone_lcell   add_sub_cella_8
2975         (
2976         .cin(wire_add_sub_cella_7cout[0:0]),
2977         .combout(wire_add_sub_cella_combout[8:8]),
2978         .cout(wire_add_sub_cella_8cout[0:0]),
2979         .dataa(wire_add_sub_cella_dataa[8:8]),
2980         .datab(wire_add_sub_cella_datab[8:8]),
2981         .regout()
2982         `ifdef FORMAL_VERIFICATION
2983         `else
2984         // synopsys translate_off
2985         `endif
2986         ,
2987         .aclr(1'b0),
2988         .aload(1'b0),
2989         .clk(1'b1),
2990         .datac(1'b1),
2991         .datad(1'b1),
2992         .ena(1'b1),
2993         .inverta(1'b0),
2994         .regcascin(1'b0),
2995         .sclr(1'b0),
2996         .sload(1'b0)
2997         `ifdef FORMAL_VERIFICATION
2998         `else
2999         // synopsys translate_on
3000         `endif
3001         // synopsys translate_off
3002         ,
3003         .cin0(),
3004         .cin1(),
3005         .cout0(),
3006         .cout1(),
3007         .devclrn(),
3008         .devpor()
3009         // synopsys translate_on
3010         );
3011         defparam
3012                 add_sub_cella_8.cin_used = "true",
3013                 add_sub_cella_8.lut_mask = "69b2",
3014                 add_sub_cella_8.operation_mode = "arithmetic",
3015                 add_sub_cella_8.sum_lutc_input = "cin",
3016                 add_sub_cella_8.lpm_type = "cyclone_lcell";
3017         cyclone_lcell   add_sub_cella_9
3018         (
3019         .cin(wire_add_sub_cella_8cout[0:0]),
3020         .combout(wire_add_sub_cella_combout[9:9]),
3021         .cout(wire_add_sub_cella_9cout[0:0]),
3022         .dataa(wire_add_sub_cella_dataa[9:9]),
3023         .datab(wire_add_sub_cella_datab[9:9]),
3024         .regout()
3025         `ifdef FORMAL_VERIFICATION
3026         `else
3027         // synopsys translate_off
3028         `endif
3029         ,
3030         .aclr(1'b0),
3031         .aload(1'b0),
3032         .clk(1'b1),
3033         .datac(1'b1),
3034         .datad(1'b1),
3035         .ena(1'b1),
3036         .inverta(1'b0),
3037         .regcascin(1'b0),
3038         .sclr(1'b0),
3039         .sload(1'b0)
3040         `ifdef FORMAL_VERIFICATION
3041         `else
3042         // synopsys translate_on
3043         `endif
3044         // synopsys translate_off
3045         ,
3046         .cin0(),
3047         .cin1(),
3048         .cout0(),
3049         .cout1(),
3050         .devclrn(),
3051         .devpor()
3052         // synopsys translate_on
3053         );
3054         defparam
3055                 add_sub_cella_9.cin_used = "true",
3056                 add_sub_cella_9.lut_mask = "69b2",
3057                 add_sub_cella_9.operation_mode = "arithmetic",
3058                 add_sub_cella_9.sum_lutc_input = "cin",
3059                 add_sub_cella_9.lpm_type = "cyclone_lcell";
3060         cyclone_lcell   add_sub_cella_10
3061         (
3062         .cin(wire_add_sub_cella_9cout[0:0]),
3063         .combout(wire_add_sub_cella_combout[10:10]),
3064         .cout(wire_add_sub_cella_10cout[0:0]),
3065         .dataa(wire_add_sub_cella_dataa[10:10]),
3066         .datab(wire_add_sub_cella_datab[10:10]),
3067         .regout()
3068         `ifdef FORMAL_VERIFICATION
3069         `else
3070         // synopsys translate_off
3071         `endif
3072         ,
3073         .aclr(1'b0),
3074         .aload(1'b0),
3075         .clk(1'b1),
3076         .datac(1'b1),
3077         .datad(1'b1),
3078         .ena(1'b1),
3079         .inverta(1'b0),
3080         .regcascin(1'b0),
3081         .sclr(1'b0),
3082         .sload(1'b0)
3083         `ifdef FORMAL_VERIFICATION
3084         `else
3085         // synopsys translate_on
3086         `endif
3087         // synopsys translate_off
3088         ,
3089         .cin0(),
3090         .cin1(),
3091         .cout0(),
3092         .cout1(),
3093         .devclrn(),
3094         .devpor()
3095         // synopsys translate_on
3096         );
3097         defparam
3098                 add_sub_cella_10.cin_used = "true",
3099                 add_sub_cella_10.lut_mask = "69b2",
3100                 add_sub_cella_10.operation_mode = "arithmetic",
3101                 add_sub_cella_10.sum_lutc_input = "cin",
3102                 add_sub_cella_10.lpm_type = "cyclone_lcell";
3103         cyclone_lcell   add_sub_cella_11
3104         (
3105         .cin(wire_add_sub_cella_10cout[0:0]),
3106         .combout(wire_add_sub_cella_combout[11:11]),
3107         .cout(),
3108         .dataa(wire_add_sub_cella_dataa[11:11]),
3109         .datab(wire_add_sub_cella_datab[11:11]),
3110         .regout()
3111         `ifdef FORMAL_VERIFICATION
3112         `else
3113         // synopsys translate_off
3114         `endif
3115         ,
3116         .aclr(1'b0),
3117         .aload(1'b0),
3118         .clk(1'b1),
3119         .datac(1'b1),
3120         .datad(1'b1),
3121         .ena(1'b1),
3122         .inverta(1'b0),
3123         .regcascin(1'b0),
3124         .sclr(1'b0),
3125         .sload(1'b0)
3126         `ifdef FORMAL_VERIFICATION
3127         `else
3128         // synopsys translate_on
3129         `endif
3130         // synopsys translate_off
3131         ,
3132         .cin0(),
3133         .cin1(),
3134         .cout0(),
3135         .cout1(),
3136         .devclrn(),
3137         .devpor()
3138         // synopsys translate_on
3139         );
3140         defparam
3141                 add_sub_cella_11.cin_used = "true",
3142                 add_sub_cella_11.lut_mask = "6969",
3143                 add_sub_cella_11.operation_mode = "normal",
3144                 add_sub_cella_11.sum_lutc_input = "cin",
3145                 add_sub_cella_11.lpm_type = "cyclone_lcell";
3146         assign
3147                 wire_add_sub_cella_dataa = dataa,
3148                 wire_add_sub_cella_datab = datab;
3149         assign
3150                 result = wire_add_sub_cella_combout;
3151 endmodule //fifo_4k_add_sub_b18
3152
3153
3154 //lpm_compare DEVICE_FAMILY="Cyclone" LPM_WIDTH=12 aeb dataa datab
3155 //VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ  VERSION_END
3156
3157
3158 //lpm_compare DEVICE_FAMILY="Cyclone" LPM_WIDTH=12 aeb dataa datab
3159 //VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ  VERSION_END
3160
3161 //synthesis_resources = lut 104 M4K 16
3162 //synopsys translate_off
3163 `timescale 1 ps / 1 ps
3164 //synopsys translate_on
3165 module  fifo_4k_dcfifo_6cq
3166         (
3167         aclr,
3168         data,
3169         q,
3170         rdclk,
3171         rdempty,
3172         rdreq,
3173         rdusedw,
3174         wrclk,
3175         wrfull,
3176         wrreq,
3177         wrusedw) /* synthesis synthesis_clearbox=1 */
3178                 /* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF;{ -from \"rdptr_g|power_modified_counter_values\" -to \"ws_dgrp|dffpipe5|dffe6a\" }CUT=ON;{ -from \"delayed_wrptr_g\" -to \"rs_dgwp|dffpipe5|dffe6a\" }CUT=ON" */;
3179         input   aclr;
3180         input   [15:0]  data;
3181         output   [15:0]  q;
3182         input   rdclk;
3183         output   rdempty;
3184         input   rdreq;
3185         output   [11:0]  rdusedw;
3186         input   wrclk;
3187         output   wrfull;
3188         input   wrreq;
3189         output   [11:0]  wrusedw;
3190
3191         wire  [11:0]   wire_rdptr_g_gray2bin_bin;
3192         wire  [11:0]   wire_rs_dgwp_gray2bin_bin;
3193         wire  [11:0]   wire_wrptr_g_gray2bin_bin;
3194         wire  [11:0]   wire_ws_dgrp_gray2bin_bin;
3195         wire  [11:0]   wire_rdptr_g_q;
3196         wire  [11:0]   wire_rdptr_g1p_q;
3197         wire  [11:0]   wire_wrptr_g1p_q;
3198         wire  [15:0]   wire_fifo_ram_q_b;
3199         reg     [11:0]  delayed_wrptr_g;
3200         reg     [11:0]  wrptr_g;
3201         wire  [11:0]   wire_rs_brp_q;
3202         wire  [11:0]   wire_rs_bwp_q;
3203         wire  [11:0]   wire_rs_dgwp_q;
3204         wire  [11:0]   wire_ws_brp_q;
3205         wire  [11:0]   wire_ws_bwp_q;
3206         wire  [11:0]   wire_ws_dgrp_q;
3207         wire  [11:0]   wire_rdusedw_sub_result;
3208         wire  [11:0]   wire_wrusedw_sub_result;
3209         reg     wire_rdempty_eq_comp_aeb_int;
3210         wire    wire_rdempty_eq_comp_aeb;
3211         wire    [11:0]  wire_rdempty_eq_comp_dataa;
3212         wire    [11:0]  wire_rdempty_eq_comp_datab;
3213         reg     wire_wrfull_eq_comp_aeb_int;
3214         wire    wire_wrfull_eq_comp_aeb;
3215         wire    [11:0]  wire_wrfull_eq_comp_dataa;
3216         wire    [11:0]  wire_wrfull_eq_comp_datab;
3217         wire  int_rdempty;
3218         wire  int_wrfull;
3219         wire  valid_rdreq;
3220         wire  valid_wrreq;
3221
3222         fifo_4k_a_gray2bin_9m4   rdptr_g_gray2bin
3223         (
3224         .bin(wire_rdptr_g_gray2bin_bin),
3225         .gray(wire_rdptr_g_q));
3226         fifo_4k_a_gray2bin_9m4   rs_dgwp_gray2bin
3227         (
3228         .bin(wire_rs_dgwp_gray2bin_bin),
3229         .gray(wire_rs_dgwp_q));
3230         fifo_4k_a_gray2bin_9m4   wrptr_g_gray2bin
3231         (
3232         .bin(wire_wrptr_g_gray2bin_bin),
3233         .gray(wrptr_g));
3234         fifo_4k_a_gray2bin_9m4   ws_dgrp_gray2bin
3235         (
3236         .bin(wire_ws_dgrp_gray2bin_bin),
3237         .gray(wire_ws_dgrp_q));
3238         fifo_4k_a_graycounter_826   rdptr_g
3239         (
3240         .aclr(aclr),
3241         .clock(rdclk),
3242         .cnt_en(valid_rdreq),
3243         .q(wire_rdptr_g_q));
3244         fifo_4k_a_graycounter_3r6   rdptr_g1p
3245         (
3246         .aclr(aclr),
3247         .clock(rdclk),
3248         .cnt_en(valid_rdreq),
3249         .q(wire_rdptr_g1p_q));
3250         fifo_4k_a_graycounter_3r6   wrptr_g1p
3251         (
3252         .aclr(aclr),
3253         .clock(wrclk),
3254         .cnt_en(valid_wrreq),
3255         .q(wire_wrptr_g1p_q));
3256         fifo_4k_altsyncram_8pl   fifo_ram
3257         (
3258         .address_a(wrptr_g),
3259         .address_b(((wire_rdptr_g_q & {12{int_rdempty}}) | (wire_rdptr_g1p_q & {12{(~ int_rdempty)}}))),
3260         .clock0(wrclk),
3261         .clock1(rdclk),
3262         .clocken1((valid_rdreq | int_rdempty)),
3263         .data_a(data),
3264         .q_b(wire_fifo_ram_q_b),
3265         .wren_a(valid_wrreq));
3266         // synopsys translate_off
3267         initial
3268                 delayed_wrptr_g = 0;
3269         // synopsys translate_on
3270         always @ ( posedge wrclk or  posedge aclr)
3271                 if (aclr == 1'b1) delayed_wrptr_g <= 12'b0;
3272                 else  delayed_wrptr_g <= wrptr_g;
3273         // synopsys translate_off
3274         initial
3275                 wrptr_g = 0;
3276         // synopsys translate_on
3277         always @ ( posedge wrclk or  posedge aclr)
3278                 if (aclr == 1'b1) wrptr_g <= 12'b0;
3279                 else if  (valid_wrreq == 1'b1)   wrptr_g <= wire_wrptr_g1p_q;
3280         fifo_4k_dffpipe_bb3   rs_brp
3281         (
3282         .clock(rdclk),
3283         .clrn((~ aclr)),
3284         .d(wire_rdptr_g_gray2bin_bin),
3285         .q(wire_rs_brp_q));
3286         fifo_4k_dffpipe_bb3   rs_bwp
3287         (
3288         .clock(rdclk),
3289         .clrn((~ aclr)),
3290         .d(wire_rs_dgwp_gray2bin_bin),
3291         .q(wire_rs_bwp_q));
3292         fifo_4k_alt_synch_pipe_em2   rs_dgwp
3293         (
3294         .clock(rdclk),
3295         .clrn((~ aclr)),
3296         .d(delayed_wrptr_g),
3297         .q(wire_rs_dgwp_q));
3298         fifo_4k_dffpipe_bb3   ws_brp
3299         (
3300         .clock(wrclk),
3301         .clrn((~ aclr)),
3302         .d(wire_ws_dgrp_gray2bin_bin),
3303         .q(wire_ws_brp_q));
3304         fifo_4k_dffpipe_bb3   ws_bwp
3305         (
3306         .clock(wrclk),
3307         .clrn((~ aclr)),
3308         .d(wire_wrptr_g_gray2bin_bin),
3309         .q(wire_ws_bwp_q));
3310         fifo_4k_alt_synch_pipe_em2   ws_dgrp
3311         (
3312         .clock(wrclk),
3313         .clrn((~ aclr)),
3314         .d(wire_rdptr_g_q),
3315         .q(wire_ws_dgrp_q));
3316         fifo_4k_add_sub_b18   rdusedw_sub
3317         (
3318         .dataa(wire_rs_bwp_q),
3319         .datab(wire_rs_brp_q),
3320         .result(wire_rdusedw_sub_result));
3321         fifo_4k_add_sub_b18   wrusedw_sub
3322         (
3323         .dataa(wire_ws_bwp_q),
3324         .datab(wire_ws_brp_q),
3325         .result(wire_wrusedw_sub_result));
3326         always @(wire_rdempty_eq_comp_dataa or wire_rdempty_eq_comp_datab)
3327                 if (wire_rdempty_eq_comp_dataa == wire_rdempty_eq_comp_datab)
3328                         begin
3329                                 wire_rdempty_eq_comp_aeb_int = 1'b1;
3330                         end
3331                 else
3332                         begin
3333                                 wire_rdempty_eq_comp_aeb_int = 1'b0;
3334                         end
3335         assign
3336                 wire_rdempty_eq_comp_aeb = wire_rdempty_eq_comp_aeb_int;
3337         assign
3338                 wire_rdempty_eq_comp_dataa = wire_rs_dgwp_q,
3339                 wire_rdempty_eq_comp_datab = wire_rdptr_g_q;
3340         always @(wire_wrfull_eq_comp_dataa or wire_wrfull_eq_comp_datab)
3341                 if (wire_wrfull_eq_comp_dataa == wire_wrfull_eq_comp_datab)
3342                         begin
3343                                 wire_wrfull_eq_comp_aeb_int = 1'b1;
3344                         end
3345                 else
3346                         begin
3347                                 wire_wrfull_eq_comp_aeb_int = 1'b0;
3348                         end
3349         assign
3350                 wire_wrfull_eq_comp_aeb = wire_wrfull_eq_comp_aeb_int;
3351         assign
3352                 wire_wrfull_eq_comp_dataa = wire_ws_dgrp_q,
3353                 wire_wrfull_eq_comp_datab = wire_wrptr_g1p_q;
3354         assign
3355                 int_rdempty = wire_rdempty_eq_comp_aeb,
3356                 int_wrfull = wire_wrfull_eq_comp_aeb,
3357                 q = wire_fifo_ram_q_b,
3358                 rdempty = int_rdempty,
3359                 rdusedw = wire_rdusedw_sub_result,
3360                 valid_rdreq = rdreq,
3361                 valid_wrreq = wrreq,
3362                 wrfull = int_wrfull,
3363                 wrusedw = wire_wrusedw_sub_result;
3364 endmodule //fifo_4k_dcfifo_6cq
3365 //VALID FILE
3366
3367
3368 // synopsys translate_off
3369 `timescale 1 ps / 1 ps
3370 // synopsys translate_on
3371 module fifo_4k (
3372         data,
3373         wrreq,
3374         rdreq,
3375         rdclk,
3376         wrclk,
3377         aclr,
3378         q,
3379         rdempty,
3380         rdusedw,
3381         wrfull,
3382         wrusedw)/* synthesis synthesis_clearbox = 1 */;
3383
3384         input   [15:0]  data;
3385         input     wrreq;
3386         input     rdreq;
3387         input     rdclk;
3388         input     wrclk;
3389         input     aclr;
3390         output  [15:0]  q;
3391         output    rdempty;
3392         output  [11:0]  rdusedw;
3393         output    wrfull;
3394         output  [11:0]  wrusedw;
3395
3396         wire  sub_wire0;
3397         wire [11:0] sub_wire1;
3398         wire  sub_wire2;
3399         wire [15:0] sub_wire3;
3400         wire [11:0] sub_wire4;
3401         wire  rdempty = sub_wire0;
3402         wire [11:0] wrusedw = sub_wire1[11:0];
3403         wire  wrfull = sub_wire2;
3404         wire [15:0] q = sub_wire3[15:0];
3405         wire [11:0] rdusedw = sub_wire4[11:0];
3406
3407         fifo_4k_dcfifo_6cq      fifo_4k_dcfifo_6cq_component (
3408                                 .wrclk (wrclk),
3409                                 .rdreq (rdreq),
3410                                 .aclr (aclr),
3411                                 .rdclk (rdclk),
3412                                 .wrreq (wrreq),
3413                                 .data (data),
3414                                 .rdempty (sub_wire0),
3415                                 .wrusedw (sub_wire1),
3416                                 .wrfull (sub_wire2),
3417                                 .q (sub_wire3),
3418                                 .rdusedw (sub_wire4));
3419
3420 endmodule
3421
3422 // ============================================================
3423 // CNX file retrieval info
3424 // ============================================================
3425 // Retrieval info: PRIVATE: Width NUMERIC "16"
3426 // Retrieval info: PRIVATE: Depth NUMERIC "4096"
3427 // Retrieval info: PRIVATE: Clock NUMERIC "4"
3428 // Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
3429 // Retrieval info: PRIVATE: Full NUMERIC "1"
3430 // Retrieval info: PRIVATE: Empty NUMERIC "1"
3431 // Retrieval info: PRIVATE: UsedW NUMERIC "1"
3432 // Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
3433 // Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
3434 // Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
3435 // Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
3436 // Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
3437 // Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
3438 // Retrieval info: PRIVATE: rsFull NUMERIC "0"
3439 // Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
3440 // Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
3441 // Retrieval info: PRIVATE: wsFull NUMERIC "1"
3442 // Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
3443 // Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
3444 // Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
3445 // Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
3446 // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
3447 // Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
3448 // Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
3449 // Retrieval info: PRIVATE: Optimize NUMERIC "2"
3450 // Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
3451 // Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
3452 // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
3453 // Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
3454 // Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096"
3455 // Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12"
3456 // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
3457 // Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"
3458 // Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
3459 // Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
3460 // Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
3461 // Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
3462 // Retrieval info: CONSTANT: USE_EAB STRING "ON"
3463 // Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
3464 // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
3465 // Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
3466 // Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
3467 // Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
3468 // Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
3469 // Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
3470 // Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
3471 // Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
3472 // Retrieval info: USED_PORT: rdusedw 0 0 12 0 OUTPUT NODEFVAL rdusedw[11..0]
3473 // Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
3474 // Retrieval info: USED_PORT: wrusedw 0 0 12 0 OUTPUT NODEFVAL wrusedw[11..0]
3475 // Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
3476 // Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
3477 // Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
3478 // Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
3479 // Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
3480 // Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
3481 // Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
3482 // Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
3483 // Retrieval info: CONNECT: rdusedw 0 0 12 0 @rdusedw 0 0 12 0
3484 // Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
3485 // Retrieval info: CONNECT: wrusedw 0 0 12 0 @wrusedw 0 0 12 0
3486 // Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
3487 // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
3488 // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.v TRUE
3489 // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.inc FALSE
3490 // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.cmp FALSE
3491 // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.bsf FALSE
3492 // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_inst.v FALSE
3493 // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_bb.v TRUE
3494 // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_waveforms.html TRUE
3495 // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_wave*.jpg FALSE