git.gag.com Git - debian/gnuradio/blob - usrp/fpga/megacells/fifo_2k.v

   1 // megafunction wizard: %FIFO%CBX%
   2 // GENERATION: STANDARD
   3 // VERSION: WM1.0
   4 // MODULE: dcfifo
   5
   6 // ============================================================
   7 // File Name: fifo_2k.v
   8 // Megafunction Name(s):
   9 //                      dcfifo
  10 // ============================================================
  11 // ************************************************************
  12 // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
  13 //
  14 // 5.0 Build 168 06/22/2005 SP 1 SJ Web Edition
  15 // ************************************************************
  16
  17
  18 //Copyright (C) 1991-2005 Altera Corporation
  19 //Your use of Altera Corporation's design tools, logic functions
  20 //and other software and tools, and its AMPP partner logic
  21 //functions, and any output files any of the foregoing
  22 //(including device programming or simulation files), and any
  23 //associated documentation or information are expressly subject
  24 //to the terms and conditions of the Altera Program License
  25 //Subscription Agreement, Altera MegaCore Function License
  26 //Agreement, or other applicable license agreement, including,
  27 //without limitation, that your use is for the sole purpose of
  28 //programming logic devices manufactured by Altera and sold by
  29 //Altera or its authorized distributors.  Please refer to the
  30 //applicable agreement for further details.
  31
  32
  33 //dcfifo ADD_RAM_OUTPUT_REGISTER="OFF" CLOCKS_ARE_SYNCHRONIZED="FALSE" DEVICE_FAMILY="Cyclone" LPM_NUMWORDS=2048 LPM_SHOWAHEAD="ON" LPM_WIDTH=16 LPM_WIDTHU=11 OVERFLOW_CHECKING="OFF" UNDERFLOW_CHECKING="OFF" USE_EAB="ON" aclr data q rdclk rdempty rdreq rdusedw wrclk wrfull wrreq wrusedw
  34 //VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_altdpram 2004:11:30:11:29:56:SJ cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_dcfifo 2005:03:07:17:11:14:SJ cbx_fifo_common 2004:12:13:14:26:24:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_counter 2005:02:02:04:37:10:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_scfifo 2005:03:10:10:52:20:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ  VERSION_END
  35
  36
  37 //a_gray2bin device_family="Cyclone" WIDTH=11 bin gray
  38 //VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_mgl 2005:05:19:13:51:58:SJ  VERSION_END
  39
  40 //synthesis_resources =
  41 //synopsys translate_off
  42 `timescale 1 ps / 1 ps
  43 //synopsys translate_on
  44 module  fifo_2k_a_gray2bin_8m4
  45         (
  46         bin,
  47         gray) /* synthesis synthesis_clearbox=1 */;
  48         output   [10:0]  bin;
  49         input   [10:0]  gray;
  50
  51         wire  xor0;
  52         wire  xor1;
  53         wire  xor2;
  54         wire  xor3;
  55         wire  xor4;
  56         wire  xor5;
  57         wire  xor6;
  58         wire  xor7;
  59         wire  xor8;
  60         wire  xor9;
  61
  62         assign
  63                 bin = {gray[10], xor9, xor8, xor7, xor6, xor5, xor4, xor3, xor2, xor1, xor0},
  64                 xor0 = (gray[0] ^ xor1),
  65                 xor1 = (gray[1] ^ xor2),
  66                 xor2 = (gray[2] ^ xor3),
  67                 xor3 = (gray[3] ^ xor4),
  68                 xor4 = (gray[4] ^ xor5),
  69                 xor5 = (gray[5] ^ xor6),
  70                 xor6 = (gray[6] ^ xor7),
  71                 xor7 = (gray[7] ^ xor8),
  72                 xor8 = (gray[8] ^ xor9),
  73                 xor9 = (gray[10] ^ gray[9]);
  74 endmodule //fifo_2k_a_gray2bin_8m4
  75
  76
  77 //a_graycounter DEVICE_FAMILY="Cyclone" WIDTH=11 aclr clock cnt_en q
  78 //VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ  VERSION_END
  79
  80 //synthesis_resources = lut 12
  81 //synopsys translate_off
  82 `timescale 1 ps / 1 ps
  83 //synopsys translate_on
  84 module  fifo_2k_a_graycounter_726
  85         (
  86         aclr,
  87         clock,
  88         cnt_en,
  89         q) /* synthesis synthesis_clearbox=1 */;
  90         input   aclr;
  91         input   clock;
  92         input   cnt_en;
  93         output   [10:0]  q;
  94
  95         wire  [0:0]   wire_countera_0cout;
  96         wire  [0:0]   wire_countera_1cout;
  97         wire  [0:0]   wire_countera_2cout;
  98         wire  [0:0]   wire_countera_3cout;
  99         wire  [0:0]   wire_countera_4cout;
 100         wire  [0:0]   wire_countera_5cout;
 101         wire  [0:0]   wire_countera_6cout;
 102         wire  [0:0]   wire_countera_7cout;
 103         wire  [0:0]   wire_countera_8cout;
 104         wire  [0:0]   wire_countera_9cout;
 105         wire  [10:0]   wire_countera_regout;
 106         wire  wire_parity_cout;
 107         wire  wire_parity_regout;
 108         wire  [10:0]  power_modified_counter_values;
 109         wire sclr;
 110         wire updown;
 111
 112         cyclone_lcell   countera_0
 113         (
 114         .aclr(aclr),
 115         .cin(wire_parity_cout),
 116         .clk(clock),
 117         .combout(),
 118         .cout(wire_countera_0cout[0:0]),
 119         .dataa(cnt_en),
 120         .datab(wire_countera_regout[0:0]),
 121         .ena(1'b1),
 122         .regout(wire_countera_regout[0:0]),
 123         .sclr(sclr)
 124         `ifdef FORMAL_VERIFICATION
 125         `else
 126         // synopsys translate_off
 127         `endif
 128         ,
 129         .aload(1'b0),
 130         .datac(1'b1),
 131         .datad(1'b1),
 132         .inverta(1'b0),
 133         .regcascin(1'b0),
 134         .sload(1'b0)
 135         `ifdef FORMAL_VERIFICATION
 136         `else
 137         // synopsys translate_on
 138         `endif
 139         // synopsys translate_off
 140         ,
 141         .cin0(),
 142         .cin1(),
 143         .cout0(),
 144         .cout1(),
 145         .devclrn(),
 146         .devpor()
 147         // synopsys translate_on
 148         );
 149         defparam
 150                 countera_0.cin_used = "true",
 151                 countera_0.lut_mask = "c6a0",
 152                 countera_0.operation_mode = "arithmetic",
 153                 countera_0.sum_lutc_input = "cin",
 154                 countera_0.synch_mode = "on",
 155                 countera_0.lpm_type = "cyclone_lcell";
 156         cyclone_lcell   countera_1
 157         (
 158         .aclr(aclr),
 159         .cin(wire_countera_0cout[0:0]),
 160         .clk(clock),
 161         .combout(),
 162         .cout(wire_countera_1cout[0:0]),
 163         .dataa(power_modified_counter_values[0]),
 164         .datab(power_modified_counter_values[1]),
 165         .ena(1'b1),
 166         .regout(wire_countera_regout[1:1]),
 167         .sclr(sclr)
 168         `ifdef FORMAL_VERIFICATION
 169         `else
 170         // synopsys translate_off
 171         `endif
 172         ,
 173         .aload(1'b0),
 174         .datac(1'b1),
 175         .datad(1'b1),
 176         .inverta(1'b0),
 177         .regcascin(1'b0),
 178         .sload(1'b0)
 179         `ifdef FORMAL_VERIFICATION
 180         `else
 181         // synopsys translate_on
 182         `endif
 183         // synopsys translate_off
 184         ,
 185         .cin0(),
 186         .cin1(),
 187         .cout0(),
 188         .cout1(),
 189         .devclrn(),
 190         .devpor()
 191         // synopsys translate_on
 192         );
 193         defparam
 194                 countera_1.cin_used = "true",
 195                 countera_1.lut_mask = "6c50",
 196                 countera_1.operation_mode = "arithmetic",
 197                 countera_1.sum_lutc_input = "cin",
 198                 countera_1.synch_mode = "on",
 199                 countera_1.lpm_type = "cyclone_lcell";
 200         cyclone_lcell   countera_2
 201         (
 202         .aclr(aclr),
 203         .cin(wire_countera_1cout[0:0]),
 204         .clk(clock),
 205         .combout(),
 206         .cout(wire_countera_2cout[0:0]),
 207         .dataa(power_modified_counter_values[1]),
 208         .datab(power_modified_counter_values[2]),
 209         .ena(1'b1),
 210         .regout(wire_countera_regout[2:2]),
 211         .sclr(sclr)
 212         `ifdef FORMAL_VERIFICATION
 213         `else
 214         // synopsys translate_off
 215         `endif
 216         ,
 217         .aload(1'b0),
 218         .datac(1'b1),
 219         .datad(1'b1),
 220         .inverta(1'b0),
 221         .regcascin(1'b0),
 222         .sload(1'b0)
 223         `ifdef FORMAL_VERIFICATION
 224         `else
 225         // synopsys translate_on
 226         `endif
 227         // synopsys translate_off
 228         ,
 229         .cin0(),
 230         .cin1(),
 231         .cout0(),
 232         .cout1(),
 233         .devclrn(),
 234         .devpor()
 235         // synopsys translate_on
 236         );
 237         defparam
 238                 countera_2.cin_used = "true",
 239                 countera_2.lut_mask = "6c50",
 240                 countera_2.operation_mode = "arithmetic",
 241                 countera_2.sum_lutc_input = "cin",
 242                 countera_2.synch_mode = "on",
 243                 countera_2.lpm_type = "cyclone_lcell";
 244         cyclone_lcell   countera_3
 245         (
 246         .aclr(aclr),
 247         .cin(wire_countera_2cout[0:0]),
 248         .clk(clock),
 249         .combout(),
 250         .cout(wire_countera_3cout[0:0]),
 251         .dataa(power_modified_counter_values[2]),
 252         .datab(power_modified_counter_values[3]),
 253         .ena(1'b1),
 254         .regout(wire_countera_regout[3:3]),
 255         .sclr(sclr)
 256         `ifdef FORMAL_VERIFICATION
 257         `else
 258         // synopsys translate_off
 259         `endif
 260         ,
 261         .aload(1'b0),
 262         .datac(1'b1),
 263         .datad(1'b1),
 264         .inverta(1'b0),
 265         .regcascin(1'b0),
 266         .sload(1'b0)
 267         `ifdef FORMAL_VERIFICATION
 268         `else
 269         // synopsys translate_on
 270         `endif
 271         // synopsys translate_off
 272         ,
 273         .cin0(),
 274         .cin1(),
 275         .cout0(),
 276         .cout1(),
 277         .devclrn(),
 278         .devpor()
 279         // synopsys translate_on
 280         );
 281         defparam
 282                 countera_3.cin_used = "true",
 283                 countera_3.lut_mask = "6c50",
 284                 countera_3.operation_mode = "arithmetic",
 285                 countera_3.sum_lutc_input = "cin",
 286                 countera_3.synch_mode = "on",
 287                 countera_3.lpm_type = "cyclone_lcell";
 288         cyclone_lcell   countera_4
 289         (
 290         .aclr(aclr),
 291         .cin(wire_countera_3cout[0:0]),
 292         .clk(clock),
 293         .combout(),
 294         .cout(wire_countera_4cout[0:0]),
 295         .dataa(power_modified_counter_values[3]),
 296         .datab(power_modified_counter_values[4]),
 297         .ena(1'b1),
 298         .regout(wire_countera_regout[4:4]),
 299         .sclr(sclr)
 300         `ifdef FORMAL_VERIFICATION
 301         `else
 302         // synopsys translate_off
 303         `endif
 304         ,
 305         .aload(1'b0),
 306         .datac(1'b1),
 307         .datad(1'b1),
 308         .inverta(1'b0),
 309         .regcascin(1'b0),
 310         .sload(1'b0)
 311         `ifdef FORMAL_VERIFICATION
 312         `else
 313         // synopsys translate_on
 314         `endif
 315         // synopsys translate_off
 316         ,
 317         .cin0(),
 318         .cin1(),
 319         .cout0(),
 320         .cout1(),
 321         .devclrn(),
 322         .devpor()
 323         // synopsys translate_on
 324         );
 325         defparam
 326                 countera_4.cin_used = "true",
 327                 countera_4.lut_mask = "6c50",
 328                 countera_4.operation_mode = "arithmetic",
 329                 countera_4.sum_lutc_input = "cin",
 330                 countera_4.synch_mode = "on",
 331                 countera_4.lpm_type = "cyclone_lcell";
 332         cyclone_lcell   countera_5
 333         (
 334         .aclr(aclr),
 335         .cin(wire_countera_4cout[0:0]),
 336         .clk(clock),
 337         .combout(),
 338         .cout(wire_countera_5cout[0:0]),
 339         .dataa(power_modified_counter_values[4]),
 340         .datab(power_modified_counter_values[5]),
 341         .ena(1'b1),
 342         .regout(wire_countera_regout[5:5]),
 343         .sclr(sclr)
 344         `ifdef FORMAL_VERIFICATION
 345         `else
 346         // synopsys translate_off
 347         `endif
 348         ,
 349         .aload(1'b0),
 350         .datac(1'b1),
 351         .datad(1'b1),
 352         .inverta(1'b0),
 353         .regcascin(1'b0),
 354         .sload(1'b0)
 355         `ifdef FORMAL_VERIFICATION
 356         `else
 357         // synopsys translate_on
 358         `endif
 359         // synopsys translate_off
 360         ,
 361         .cin0(),
 362         .cin1(),
 363         .cout0(),
 364         .cout1(),
 365         .devclrn(),
 366         .devpor()
 367         // synopsys translate_on
 368         );
 369         defparam
 370                 countera_5.cin_used = "true",
 371                 countera_5.lut_mask = "6c50",
 372                 countera_5.operation_mode = "arithmetic",
 373                 countera_5.sum_lutc_input = "cin",
 374                 countera_5.synch_mode = "on",
 375                 countera_5.lpm_type = "cyclone_lcell";
 376         cyclone_lcell   countera_6
 377         (
 378         .aclr(aclr),
 379         .cin(wire_countera_5cout[0:0]),
 380         .clk(clock),
 381         .combout(),
 382         .cout(wire_countera_6cout[0:0]),
 383         .dataa(power_modified_counter_values[5]),
 384         .datab(power_modified_counter_values[6]),
 385         .ena(1'b1),
 386         .regout(wire_countera_regout[6:6]),
 387         .sclr(sclr)
 388         `ifdef FORMAL_VERIFICATION
 389         `else
 390         // synopsys translate_off
 391         `endif
 392         ,
 393         .aload(1'b0),
 394         .datac(1'b1),
 395         .datad(1'b1),
 396         .inverta(1'b0),
 397         .regcascin(1'b0),
 398         .sload(1'b0)
 399         `ifdef FORMAL_VERIFICATION
 400         `else
 401         // synopsys translate_on
 402         `endif
 403         // synopsys translate_off
 404         ,
 405         .cin0(),
 406         .cin1(),
 407         .cout0(),
 408         .cout1(),
 409         .devclrn(),
 410         .devpor()
 411         // synopsys translate_on
 412         );
 413         defparam
 414                 countera_6.cin_used = "true",
 415                 countera_6.lut_mask = "6c50",
 416                 countera_6.operation_mode = "arithmetic",
 417                 countera_6.sum_lutc_input = "cin",
 418                 countera_6.synch_mode = "on",
 419                 countera_6.lpm_type = "cyclone_lcell";
 420         cyclone_lcell   countera_7
 421         (
 422         .aclr(aclr),
 423         .cin(wire_countera_6cout[0:0]),
 424         .clk(clock),
 425         .combout(),
 426         .cout(wire_countera_7cout[0:0]),
 427         .dataa(power_modified_counter_values[6]),
 428         .datab(power_modified_counter_values[7]),
 429         .ena(1'b1),
 430         .regout(wire_countera_regout[7:7]),
 431         .sclr(sclr)
 432         `ifdef FORMAL_VERIFICATION
 433         `else
 434         // synopsys translate_off
 435         `endif
 436         ,
 437         .aload(1'b0),
 438         .datac(1'b1),
 439         .datad(1'b1),
 440         .inverta(1'b0),
 441         .regcascin(1'b0),
 442         .sload(1'b0)
 443         `ifdef FORMAL_VERIFICATION
 444         `else
 445         // synopsys translate_on
 446         `endif
 447         // synopsys translate_off
 448         ,
 449         .cin0(),
 450         .cin1(),
 451         .cout0(),
 452         .cout1(),
 453         .devclrn(),
 454         .devpor()
 455         // synopsys translate_on
 456         );
 457         defparam
 458                 countera_7.cin_used = "true",
 459                 countera_7.lut_mask = "6c50",
 460                 countera_7.operation_mode = "arithmetic",
 461                 countera_7.sum_lutc_input = "cin",
 462                 countera_7.synch_mode = "on",
 463                 countera_7.lpm_type = "cyclone_lcell";
 464         cyclone_lcell   countera_8
 465         (
 466         .aclr(aclr),
 467         .cin(wire_countera_7cout[0:0]),
 468         .clk(clock),
 469         .combout(),
 470         .cout(wire_countera_8cout[0:0]),
 471         .dataa(power_modified_counter_values[7]),
 472         .datab(power_modified_counter_values[8]),
 473         .ena(1'b1),
 474         .regout(wire_countera_regout[8:8]),
 475         .sclr(sclr)
 476         `ifdef FORMAL_VERIFICATION
 477         `else
 478         // synopsys translate_off
 479         `endif
 480         ,
 481         .aload(1'b0),
 482         .datac(1'b1),
 483         .datad(1'b1),
 484         .inverta(1'b0),
 485         .regcascin(1'b0),
 486         .sload(1'b0)
 487         `ifdef FORMAL_VERIFICATION
 488         `else
 489         // synopsys translate_on
 490         `endif
 491         // synopsys translate_off
 492         ,
 493         .cin0(),
 494         .cin1(),
 495         .cout0(),
 496         .cout1(),
 497         .devclrn(),
 498         .devpor()
 499         // synopsys translate_on
 500         );
 501         defparam
 502                 countera_8.cin_used = "true",
 503                 countera_8.lut_mask = "6c50",
 504                 countera_8.operation_mode = "arithmetic",
 505                 countera_8.sum_lutc_input = "cin",
 506                 countera_8.synch_mode = "on",
 507                 countera_8.lpm_type = "cyclone_lcell";
 508         cyclone_lcell   countera_9
 509         (
 510         .aclr(aclr),
 511         .cin(wire_countera_8cout[0:0]),
 512         .clk(clock),
 513         .combout(),
 514         .cout(wire_countera_9cout[0:0]),
 515         .dataa(power_modified_counter_values[8]),
 516         .datab(power_modified_counter_values[9]),
 517         .ena(1'b1),
 518         .regout(wire_countera_regout[9:9]),
 519         .sclr(sclr)
 520         `ifdef FORMAL_VERIFICATION
 521         `else
 522         // synopsys translate_off
 523         `endif
 524         ,
 525         .aload(1'b0),
 526         .datac(1'b1),
 527         .datad(1'b1),
 528         .inverta(1'b0),
 529         .regcascin(1'b0),
 530         .sload(1'b0)
 531         `ifdef FORMAL_VERIFICATION
 532         `else
 533         // synopsys translate_on
 534         `endif
 535         // synopsys translate_off
 536         ,
 537         .cin0(),
 538         .cin1(),
 539         .cout0(),
 540         .cout1(),
 541         .devclrn(),
 542         .devpor()
 543         // synopsys translate_on
 544         );
 545         defparam
 546                 countera_9.cin_used = "true",
 547                 countera_9.lut_mask = "6c50",
 548                 countera_9.operation_mode = "arithmetic",
 549                 countera_9.sum_lutc_input = "cin",
 550                 countera_9.synch_mode = "on",
 551                 countera_9.lpm_type = "cyclone_lcell";
 552         cyclone_lcell   countera_10
 553         (
 554         .aclr(aclr),
 555         .cin(wire_countera_9cout[0:0]),
 556         .clk(clock),
 557         .combout(),
 558         .cout(),
 559         .dataa(power_modified_counter_values[10]),
 560         .ena(1'b1),
 561         .regout(wire_countera_regout[10:10]),
 562         .sclr(sclr)
 563         `ifdef FORMAL_VERIFICATION
 564         `else
 565         // synopsys translate_off
 566         `endif
 567         ,
 568         .aload(1'b0),
 569         .datab(1'b1),
 570         .datac(1'b1),
 571         .datad(1'b1),
 572         .inverta(1'b0),
 573         .regcascin(1'b0),
 574         .sload(1'b0)
 575         `ifdef FORMAL_VERIFICATION
 576         `else
 577         // synopsys translate_on
 578         `endif
 579         // synopsys translate_off
 580         ,
 581         .cin0(),
 582         .cin1(),
 583         .cout0(),
 584         .cout1(),
 585         .devclrn(),
 586         .devpor()
 587         // synopsys translate_on
 588         );
 589         defparam
 590                 countera_10.cin_used = "true",
 591                 countera_10.lut_mask = "5a5a",
 592                 countera_10.operation_mode = "normal",
 593                 countera_10.sum_lutc_input = "cin",
 594                 countera_10.synch_mode = "on",
 595                 countera_10.lpm_type = "cyclone_lcell";
 596         cyclone_lcell   parity
 597         (
 598         .aclr(aclr),
 599         .cin(updown),
 600         .clk(clock),
 601         .combout(),
 602         .cout(wire_parity_cout),
 603         .dataa(cnt_en),
 604         .datab(wire_parity_regout),
 605         .ena(1'b1),
 606         .regout(wire_parity_regout),
 607         .sclr(sclr)
 608         `ifdef FORMAL_VERIFICATION
 609         `else
 610         // synopsys translate_off
 611         `endif
 612         ,
 613         .aload(1'b0),
 614         .datac(1'b1),
 615         .datad(1'b1),
 616         .inverta(1'b0),
 617         .regcascin(1'b0),
 618         .sload(1'b0)
 619         `ifdef FORMAL_VERIFICATION
 620         `else
 621         // synopsys translate_on
 622         `endif
 623         // synopsys translate_off
 624         ,
 625         .cin0(),
 626         .cin1(),
 627         .cout0(),
 628         .cout1(),
 629         .devclrn(),
 630         .devpor()
 631         // synopsys translate_on
 632         );
 633         defparam
 634                 parity.cin_used = "true",
 635                 parity.lut_mask = "6682",
 636                 parity.operation_mode = "arithmetic",
 637                 parity.synch_mode = "on",
 638                 parity.lpm_type = "cyclone_lcell";
 639         assign
 640                 power_modified_counter_values = {wire_countera_regout[10:0]},
 641                 q = power_modified_counter_values,
 642                 sclr = 1'b0,
 643                 updown = 1'b1;
 644 endmodule //fifo_2k_a_graycounter_726
 645
 646
 647 //a_graycounter DEVICE_FAMILY="Cyclone" PVALUE=1 WIDTH=11 aclr clock cnt_en q
 648 //VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ  VERSION_END
 649
 650 //synthesis_resources = lut 12
 651 //synopsys translate_off
 652 `timescale 1 ps / 1 ps
 653 //synopsys translate_on
 654 module  fifo_2k_a_graycounter_2r6
 655         (
 656         aclr,
 657         clock,
 658         cnt_en,
 659         q) /* synthesis synthesis_clearbox=1 */;
 660         input   aclr;
 661         input   clock;
 662         input   cnt_en;
 663         output   [10:0]  q;
 664
 665         wire  [0:0]   wire_countera_0cout;
 666         wire  [0:0]   wire_countera_1cout;
 667         wire  [0:0]   wire_countera_2cout;
 668         wire  [0:0]   wire_countera_3cout;
 669         wire  [0:0]   wire_countera_4cout;
 670         wire  [0:0]   wire_countera_5cout;
 671         wire  [0:0]   wire_countera_6cout;
 672         wire  [0:0]   wire_countera_7cout;
 673         wire  [0:0]   wire_countera_8cout;
 674         wire  [0:0]   wire_countera_9cout;
 675         wire  [10:0]   wire_countera_regout;
 676         wire  wire_parity_cout;
 677         wire  wire_parity_regout;
 678         wire  [10:0]  power_modified_counter_values;
 679         wire sclr;
 680         wire updown;
 681
 682         cyclone_lcell   countera_0
 683         (
 684         .aclr(aclr),
 685         .cin(wire_parity_cout),
 686         .clk(clock),
 687         .combout(),
 688         .cout(wire_countera_0cout[0:0]),
 689         .dataa(cnt_en),
 690         .datab(wire_countera_regout[0:0]),
 691         .ena(1'b1),
 692         .regout(wire_countera_regout[0:0]),
 693         .sclr(sclr)
 694         `ifdef FORMAL_VERIFICATION
 695         `else
 696         // synopsys translate_off
 697         `endif
 698         ,
 699         .aload(1'b0),
 700         .datac(1'b1),
 701         .datad(1'b1),
 702         .inverta(1'b0),
 703         .regcascin(1'b0),
 704         .sload(1'b0)
 705         `ifdef FORMAL_VERIFICATION
 706         `else
 707         // synopsys translate_on
 708         `endif
 709         // synopsys translate_off
 710         ,
 711         .cin0(),
 712         .cin1(),
 713         .cout0(),
 714         .cout1(),
 715         .devclrn(),
 716         .devpor()
 717         // synopsys translate_on
 718         );
 719         defparam
 720                 countera_0.cin_used = "true",
 721                 countera_0.lut_mask = "c6a0",
 722                 countera_0.operation_mode = "arithmetic",
 723                 countera_0.sum_lutc_input = "cin",
 724                 countera_0.synch_mode = "on",
 725                 countera_0.lpm_type = "cyclone_lcell";
 726         cyclone_lcell   countera_1
 727         (
 728         .aclr(aclr),
 729         .cin(wire_countera_0cout[0:0]),
 730         .clk(clock),
 731         .combout(),
 732         .cout(wire_countera_1cout[0:0]),
 733         .dataa(power_modified_counter_values[0]),
 734         .datab(power_modified_counter_values[1]),
 735         .ena(1'b1),
 736         .regout(wire_countera_regout[1:1]),
 737         .sclr(sclr)
 738         `ifdef FORMAL_VERIFICATION
 739         `else
 740         // synopsys translate_off
 741         `endif
 742         ,
 743         .aload(1'b0),
 744         .datac(1'b1),
 745         .datad(1'b1),
 746         .inverta(1'b0),
 747         .regcascin(1'b0),
 748         .sload(1'b0)
 749         `ifdef FORMAL_VERIFICATION
 750         `else
 751         // synopsys translate_on
 752         `endif
 753         // synopsys translate_off
 754         ,
 755         .cin0(),
 756         .cin1(),
 757         .cout0(),
 758         .cout1(),
 759         .devclrn(),
 760         .devpor()
 761         // synopsys translate_on
 762         );
 763         defparam
 764                 countera_1.cin_used = "true",
 765                 countera_1.lut_mask = "6c50",
 766                 countera_1.operation_mode = "arithmetic",
 767                 countera_1.sum_lutc_input = "cin",
 768                 countera_1.synch_mode = "on",
 769                 countera_1.lpm_type = "cyclone_lcell";
 770         cyclone_lcell   countera_2
 771         (
 772         .aclr(aclr),
 773         .cin(wire_countera_1cout[0:0]),
 774         .clk(clock),
 775         .combout(),
 776         .cout(wire_countera_2cout[0:0]),
 777         .dataa(power_modified_counter_values[1]),
 778         .datab(power_modified_counter_values[2]),
 779         .ena(1'b1),
 780         .regout(wire_countera_regout[2:2]),
 781         .sclr(sclr)
 782         `ifdef FORMAL_VERIFICATION
 783         `else
 784         // synopsys translate_off
 785         `endif
 786         ,
 787         .aload(1'b0),
 788         .datac(1'b1),
 789         .datad(1'b1),
 790         .inverta(1'b0),
 791         .regcascin(1'b0),
 792         .sload(1'b0)
 793         `ifdef FORMAL_VERIFICATION
 794         `else
 795         // synopsys translate_on
 796         `endif
 797         // synopsys translate_off
 798         ,
 799         .cin0(),
 800         .cin1(),
 801         .cout0(),
 802         .cout1(),
 803         .devclrn(),
 804         .devpor()
 805         // synopsys translate_on
 806         );
 807         defparam
 808                 countera_2.cin_used = "true",
 809                 countera_2.lut_mask = "6c50",
 810                 countera_2.operation_mode = "arithmetic",
 811                 countera_2.sum_lutc_input = "cin",
 812                 countera_2.synch_mode = "on",
 813                 countera_2.lpm_type = "cyclone_lcell";
 814         cyclone_lcell   countera_3
 815         (
 816         .aclr(aclr),
 817         .cin(wire_countera_2cout[0:0]),
 818         .clk(clock),
 819         .combout(),
 820         .cout(wire_countera_3cout[0:0]),
 821         .dataa(power_modified_counter_values[2]),
 822         .datab(power_modified_counter_values[3]),
 823         .ena(1'b1),
 824         .regout(wire_countera_regout[3:3]),
 825         .sclr(sclr)
 826         `ifdef FORMAL_VERIFICATION
 827         `else
 828         // synopsys translate_off
 829         `endif
 830         ,
 831         .aload(1'b0),
 832         .datac(1'b1),
 833         .datad(1'b1),
 834         .inverta(1'b0),
 835         .regcascin(1'b0),
 836         .sload(1'b0)
 837         `ifdef FORMAL_VERIFICATION
 838         `else
 839         // synopsys translate_on
 840         `endif
 841         // synopsys translate_off
 842         ,
 843         .cin0(),
 844         .cin1(),
 845         .cout0(),
 846         .cout1(),
 847         .devclrn(),
 848         .devpor()
 849         // synopsys translate_on
 850         );
 851         defparam
 852                 countera_3.cin_used = "true",
 853                 countera_3.lut_mask = "6c50",
 854                 countera_3.operation_mode = "arithmetic",
 855                 countera_3.sum_lutc_input = "cin",
 856                 countera_3.synch_mode = "on",
 857                 countera_3.lpm_type = "cyclone_lcell";
 858         cyclone_lcell   countera_4
 859         (
 860         .aclr(aclr),
 861         .cin(wire_countera_3cout[0:0]),
 862         .clk(clock),
 863         .combout(),
 864         .cout(wire_countera_4cout[0:0]),
 865         .dataa(power_modified_counter_values[3]),
 866         .datab(power_modified_counter_values[4]),
 867         .ena(1'b1),
 868         .regout(wire_countera_regout[4:4]),
 869         .sclr(sclr)
 870         `ifdef FORMAL_VERIFICATION
 871         `else
 872         // synopsys translate_off
 873         `endif
 874         ,
 875         .aload(1'b0),
 876         .datac(1'b1),
 877         .datad(1'b1),
 878         .inverta(1'b0),
 879         .regcascin(1'b0),
 880         .sload(1'b0)
 881         `ifdef FORMAL_VERIFICATION
 882         `else
 883         // synopsys translate_on
 884         `endif
 885         // synopsys translate_off
 886         ,
 887         .cin0(),
 888         .cin1(),
 889         .cout0(),
 890         .cout1(),
 891         .devclrn(),
 892         .devpor()
 893         // synopsys translate_on
 894         );
 895         defparam
 896                 countera_4.cin_used = "true",
 897                 countera_4.lut_mask = "6c50",
 898                 countera_4.operation_mode = "arithmetic",
 899                 countera_4.sum_lutc_input = "cin",
 900                 countera_4.synch_mode = "on",
 901                 countera_4.lpm_type = "cyclone_lcell";
 902         cyclone_lcell   countera_5
 903         (
 904         .aclr(aclr),
 905         .cin(wire_countera_4cout[0:0]),
 906         .clk(clock),
 907         .combout(),
 908         .cout(wire_countera_5cout[0:0]),
 909         .dataa(power_modified_counter_values[4]),
 910         .datab(power_modified_counter_values[5]),
 911         .ena(1'b1),
 912         .regout(wire_countera_regout[5:5]),
 913         .sclr(sclr)
 914         `ifdef FORMAL_VERIFICATION
 915         `else
 916         // synopsys translate_off
 917         `endif
 918         ,
 919         .aload(1'b0),
 920         .datac(1'b1),
 921         .datad(1'b1),
 922         .inverta(1'b0),
 923         .regcascin(1'b0),
 924         .sload(1'b0)
 925         `ifdef FORMAL_VERIFICATION
 926         `else
 927         // synopsys translate_on
 928         `endif
 929         // synopsys translate_off
 930         ,
 931         .cin0(),
 932         .cin1(),
 933         .cout0(),
 934         .cout1(),
 935         .devclrn(),
 936         .devpor()
 937         // synopsys translate_on
 938         );
 939         defparam
 940                 countera_5.cin_used = "true",
 941                 countera_5.lut_mask = "6c50",
 942                 countera_5.operation_mode = "arithmetic",
 943                 countera_5.sum_lutc_input = "cin",
 944                 countera_5.synch_mode = "on",
 945                 countera_5.lpm_type = "cyclone_lcell";
 946         cyclone_lcell   countera_6
 947         (
 948         .aclr(aclr),
 949         .cin(wire_countera_5cout[0:0]),
 950         .clk(clock),
 951         .combout(),
 952         .cout(wire_countera_6cout[0:0]),
 953         .dataa(power_modified_counter_values[5]),
 954         .datab(power_modified_counter_values[6]),
 955         .ena(1'b1),
 956         .regout(wire_countera_regout[6:6]),
 957         .sclr(sclr)
 958         `ifdef FORMAL_VERIFICATION
 959         `else
 960         // synopsys translate_off
 961         `endif
 962         ,
 963         .aload(1'b0),
 964         .datac(1'b1),
 965         .datad(1'b1),
 966         .inverta(1'b0),
 967         .regcascin(1'b0),
 968         .sload(1'b0)
 969         `ifdef FORMAL_VERIFICATION
 970         `else
 971         // synopsys translate_on
 972         `endif
 973         // synopsys translate_off
 974         ,
 975         .cin0(),
 976         .cin1(),
 977         .cout0(),
 978         .cout1(),
 979         .devclrn(),
 980         .devpor()
 981         // synopsys translate_on
 982         );
 983         defparam
 984                 countera_6.cin_used = "true",
 985                 countera_6.lut_mask = "6c50",
 986                 countera_6.operation_mode = "arithmetic",
 987                 countera_6.sum_lutc_input = "cin",
 988                 countera_6.synch_mode = "on",
 989                 countera_6.lpm_type = "cyclone_lcell";
 990         cyclone_lcell   countera_7
 991         (
 992         .aclr(aclr),
 993         .cin(wire_countera_6cout[0:0]),
 994         .clk(clock),
 995         .combout(),
 996         .cout(wire_countera_7cout[0:0]),
 997         .dataa(power_modified_counter_values[6]),
 998         .datab(power_modified_counter_values[7]),
 999         .ena(1'b1),
1000         .regout(wire_countera_regout[7:7]),
1001         .sclr(sclr)
1002         `ifdef FORMAL_VERIFICATION
1003         `else
1004         // synopsys translate_off
1005         `endif
1006         ,
1007         .aload(1'b0),
1008         .datac(1'b1),
1009         .datad(1'b1),
1010         .inverta(1'b0),
1011         .regcascin(1'b0),
1012         .sload(1'b0)
1013         `ifdef FORMAL_VERIFICATION
1014         `else
1015         // synopsys translate_on
1016         `endif
1017         // synopsys translate_off
1018         ,
1019         .cin0(),
1020         .cin1(),
1021         .cout0(),
1022         .cout1(),
1023         .devclrn(),
1024         .devpor()
1025         // synopsys translate_on
1026         );
1027         defparam
1028                 countera_7.cin_used = "true",
1029                 countera_7.lut_mask = "6c50",
1030                 countera_7.operation_mode = "arithmetic",
1031                 countera_7.sum_lutc_input = "cin",
1032                 countera_7.synch_mode = "on",
1033                 countera_7.lpm_type = "cyclone_lcell";
1034         cyclone_lcell   countera_8
1035         (
1036         .aclr(aclr),
1037         .cin(wire_countera_7cout[0:0]),
1038         .clk(clock),
1039         .combout(),
1040         .cout(wire_countera_8cout[0:0]),
1041         .dataa(power_modified_counter_values[7]),
1042         .datab(power_modified_counter_values[8]),
1043         .ena(1'b1),
1044         .regout(wire_countera_regout[8:8]),
1045         .sclr(sclr)
1046         `ifdef FORMAL_VERIFICATION
1047         `else
1048         // synopsys translate_off
1049         `endif
1050         ,
1051         .aload(1'b0),
1052         .datac(1'b1),
1053         .datad(1'b1),
1054         .inverta(1'b0),
1055         .regcascin(1'b0),
1056         .sload(1'b0)
1057         `ifdef FORMAL_VERIFICATION
1058         `else
1059         // synopsys translate_on
1060         `endif
1061         // synopsys translate_off
1062         ,
1063         .cin0(),
1064         .cin1(),
1065         .cout0(),
1066         .cout1(),
1067         .devclrn(),
1068         .devpor()
1069         // synopsys translate_on
1070         );
1071         defparam
1072                 countera_8.cin_used = "true",
1073                 countera_8.lut_mask = "6c50",
1074                 countera_8.operation_mode = "arithmetic",
1075                 countera_8.sum_lutc_input = "cin",
1076                 countera_8.synch_mode = "on",
1077                 countera_8.lpm_type = "cyclone_lcell";
1078         cyclone_lcell   countera_9
1079         (
1080         .aclr(aclr),
1081         .cin(wire_countera_8cout[0:0]),
1082         .clk(clock),
1083         .combout(),
1084         .cout(wire_countera_9cout[0:0]),
1085         .dataa(power_modified_counter_values[8]),
1086         .datab(power_modified_counter_values[9]),
1087         .ena(1'b1),
1088         .regout(wire_countera_regout[9:9]),
1089         .sclr(sclr)
1090         `ifdef FORMAL_VERIFICATION
1091         `else
1092         // synopsys translate_off
1093         `endif
1094         ,
1095         .aload(1'b0),
1096         .datac(1'b1),
1097         .datad(1'b1),
1098         .inverta(1'b0),
1099         .regcascin(1'b0),
1100         .sload(1'b0)
1101         `ifdef FORMAL_VERIFICATION
1102         `else
1103         // synopsys translate_on
1104         `endif
1105         // synopsys translate_off
1106         ,
1107         .cin0(),
1108         .cin1(),
1109         .cout0(),
1110         .cout1(),
1111         .devclrn(),
1112         .devpor()
1113         // synopsys translate_on
1114         );
1115         defparam
1116                 countera_9.cin_used = "true",
1117                 countera_9.lut_mask = "6c50",
1118                 countera_9.operation_mode = "arithmetic",
1119                 countera_9.sum_lutc_input = "cin",
1120                 countera_9.synch_mode = "on",
1121                 countera_9.lpm_type = "cyclone_lcell";
1122         cyclone_lcell   countera_10
1123         (
1124         .aclr(aclr),
1125         .cin(wire_countera_9cout[0:0]),
1126         .clk(clock),
1127         .combout(),
1128         .cout(),
1129         .dataa(power_modified_counter_values[10]),
1130         .ena(1'b1),
1131         .regout(wire_countera_regout[10:10]),
1132         .sclr(sclr)
1133         `ifdef FORMAL_VERIFICATION
1134         `else
1135         // synopsys translate_off
1136         `endif
1137         ,
1138         .aload(1'b0),
1139         .datab(1'b1),
1140         .datac(1'b1),
1141         .datad(1'b1),
1142         .inverta(1'b0),
1143         .regcascin(1'b0),
1144         .sload(1'b0)
1145         `ifdef FORMAL_VERIFICATION
1146         `else
1147         // synopsys translate_on
1148         `endif
1149         // synopsys translate_off
1150         ,
1151         .cin0(),
1152         .cin1(),
1153         .cout0(),
1154         .cout1(),
1155         .devclrn(),
1156         .devpor()
1157         // synopsys translate_on
1158         );
1159         defparam
1160                 countera_10.cin_used = "true",
1161                 countera_10.lut_mask = "5a5a",
1162                 countera_10.operation_mode = "normal",
1163                 countera_10.sum_lutc_input = "cin",
1164                 countera_10.synch_mode = "on",
1165                 countera_10.lpm_type = "cyclone_lcell";
1166         cyclone_lcell   parity
1167         (
1168         .aclr(aclr),
1169         .cin(updown),
1170         .clk(clock),
1171         .combout(),
1172         .cout(wire_parity_cout),
1173         .dataa(cnt_en),
1174         .datab((~ wire_parity_regout)),
1175         .ena(1'b1),
1176         .regout(wire_parity_regout),
1177         .sclr(sclr)
1178         `ifdef FORMAL_VERIFICATION
1179         `else
1180         // synopsys translate_off
1181         `endif
1182         ,
1183         .aload(1'b0),
1184         .datac(1'b1),
1185         .datad(1'b1),
1186         .inverta(1'b0),
1187         .regcascin(1'b0),
1188         .sload(1'b0)
1189         `ifdef FORMAL_VERIFICATION
1190         `else
1191         // synopsys translate_on
1192         `endif
1193         // synopsys translate_off
1194         ,
1195         .cin0(),
1196         .cin1(),
1197         .cout0(),
1198         .cout1(),
1199         .devclrn(),
1200         .devpor()
1201         // synopsys translate_on
1202         );
1203         defparam
1204                 parity.cin_used = "true",
1205                 parity.lut_mask = "9982",
1206                 parity.operation_mode = "arithmetic",
1207                 parity.synch_mode = "on",
1208                 parity.lpm_type = "cyclone_lcell";
1209         assign
1210                 power_modified_counter_values = {wire_countera_regout[10:1], (~ wire_countera_regout[0])},
1211                 q = power_modified_counter_values,
1212                 sclr = 1'b0,
1213                 updown = 1'b1;
1214 endmodule //fifo_2k_a_graycounter_2r6
1215
1216
1217 //altsyncram ADDRESS_REG_B="CLOCK1" DEVICE_FAMILY="Cyclone" OPERATION_MODE="DUAL_PORT" OUTDATA_REG_B="UNREGISTERED" WIDTH_A=16 WIDTH_B=16 WIDTH_BYTEENA_A=1 WIDTHAD_A=11 WIDTHAD_B=11 address_a address_b clock0 clock1 clocken1 data_a q_b wren_a
1218 //VERSION_BEGIN 5.0 cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ  VERSION_END
1219
1220 //synthesis_resources = M4K 8
1221 //synopsys translate_off
1222 `timescale 1 ps / 1 ps
1223 //synopsys translate_on
1224 module  fifo_2k_altsyncram_6pl
1225         (
1226         address_a,
1227         address_b,
1228         clock0,
1229         clock1,
1230         clocken1,
1231         data_a,
1232         q_b,
1233         wren_a) /* synthesis synthesis_clearbox=1 */;
1234         input   [10:0]  address_a;
1235         input   [10:0]  address_b;
1236         input   clock0;
1237         input   clock1;
1238         input   clocken1;
1239         input   [15:0]  data_a;
1240         output   [15:0]  q_b;
1241         input   wren_a;
1242
1243         wire  [0:0]   wire_ram_block3a_0portbdataout;
1244         wire  [0:0]   wire_ram_block3a_1portbdataout;
1245         wire  [0:0]   wire_ram_block3a_2portbdataout;
1246         wire  [0:0]   wire_ram_block3a_3portbdataout;
1247         wire  [0:0]   wire_ram_block3a_4portbdataout;
1248         wire  [0:0]   wire_ram_block3a_5portbdataout;
1249         wire  [0:0]   wire_ram_block3a_6portbdataout;
1250         wire  [0:0]   wire_ram_block3a_7portbdataout;
1251         wire  [0:0]   wire_ram_block3a_8portbdataout;
1252         wire  [0:0]   wire_ram_block3a_9portbdataout;
1253         wire  [0:0]   wire_ram_block3a_10portbdataout;
1254         wire  [0:0]   wire_ram_block3a_11portbdataout;
1255         wire  [0:0]   wire_ram_block3a_12portbdataout;
1256         wire  [0:0]   wire_ram_block3a_13portbdataout;
1257         wire  [0:0]   wire_ram_block3a_14portbdataout;
1258         wire  [0:0]   wire_ram_block3a_15portbdataout;
1259         wire  [10:0]  address_a_wire;
1260         wire  [10:0]  address_b_wire;
1261
1262         cyclone_ram_block   ram_block3a_0
1263         (
1264         .clk0(clock0),
1265         .clk1(clock1),
1266         .ena0(wren_a),
1267         .ena1(clocken1),
1268         .portaaddr({address_a_wire[10:0]}),
1269         .portadatain({data_a[0]}),
1270         .portadataout(),
1271         .portawe(1'b1),
1272         .portbaddr({address_b_wire[10:0]}),
1273         .portbdataout(wire_ram_block3a_0portbdataout[0:0]),
1274         .portbrewe(1'b1)
1275         `ifdef FORMAL_VERIFICATION
1276         `else
1277         // synopsys translate_off
1278         `endif
1279         ,
1280         .clr0(1'b0),
1281         .clr1(1'b0),
1282         .portabyteenamasks(1'b1),
1283         .portbbyteenamasks(1'b1),
1284         .portbdatain(1'b0)
1285         `ifdef FORMAL_VERIFICATION
1286         `else
1287         // synopsys translate_on
1288         `endif
1289         // synopsys translate_off
1290         ,
1291         .devclrn(),
1292         .devpor()
1293         // synopsys translate_on
1294         );
1295         defparam
1296                 ram_block3a_0.connectivity_checking = "OFF",
1297                 ram_block3a_0.logical_ram_name = "ALTSYNCRAM",
1298                 ram_block3a_0.mixed_port_feed_through_mode = "dont_care",
1299                 ram_block3a_0.operation_mode = "dual_port",
1300                 ram_block3a_0.port_a_address_width = 11,
1301                 ram_block3a_0.port_a_data_width = 1,
1302                 ram_block3a_0.port_a_first_address = 0,
1303                 ram_block3a_0.port_a_first_bit_number = 0,
1304                 ram_block3a_0.port_a_last_address = 2047,
1305                 ram_block3a_0.port_a_logical_ram_depth = 2048,
1306                 ram_block3a_0.port_a_logical_ram_width = 16,
1307                 ram_block3a_0.port_b_address_clear = "none",
1308                 ram_block3a_0.port_b_address_clock = "clock1",
1309                 ram_block3a_0.port_b_address_width = 11,
1310                 ram_block3a_0.port_b_data_out_clear = "none",
1311                 ram_block3a_0.port_b_data_out_clock = "none",
1312                 ram_block3a_0.port_b_data_width = 1,
1313                 ram_block3a_0.port_b_first_address = 0,
1314                 ram_block3a_0.port_b_first_bit_number = 0,
1315                 ram_block3a_0.port_b_last_address = 2047,
1316                 ram_block3a_0.port_b_logical_ram_depth = 2048,
1317                 ram_block3a_0.port_b_logical_ram_width = 16,
1318                 ram_block3a_0.port_b_read_enable_write_enable_clock = "clock1",
1319                 ram_block3a_0.ram_block_type = "auto",
1320                 ram_block3a_0.lpm_type = "cyclone_ram_block";
1321         cyclone_ram_block   ram_block3a_1
1322         (
1323         .clk0(clock0),
1324         .clk1(clock1),
1325         .ena0(wren_a),
1326         .ena1(clocken1),
1327         .portaaddr({address_a_wire[10:0]}),
1328         .portadatain({data_a[1]}),
1329         .portadataout(),
1330         .portawe(1'b1),
1331         .portbaddr({address_b_wire[10:0]}),
1332         .portbdataout(wire_ram_block3a_1portbdataout[0:0]),
1333         .portbrewe(1'b1)
1334         `ifdef FORMAL_VERIFICATION
1335         `else
1336         // synopsys translate_off
1337         `endif
1338         ,
1339         .clr0(1'b0),
1340         .clr1(1'b0),
1341         .portabyteenamasks(1'b1),
1342         .portbbyteenamasks(1'b1),
1343         .portbdatain(1'b0)
1344         `ifdef FORMAL_VERIFICATION
1345         `else
1346         // synopsys translate_on
1347         `endif
1348         // synopsys translate_off
1349         ,
1350         .devclrn(),
1351         .devpor()
1352         // synopsys translate_on
1353         );
1354         defparam
1355                 ram_block3a_1.connectivity_checking = "OFF",
1356                 ram_block3a_1.logical_ram_name = "ALTSYNCRAM",
1357                 ram_block3a_1.mixed_port_feed_through_mode = "dont_care",
1358                 ram_block3a_1.operation_mode = "dual_port",
1359                 ram_block3a_1.port_a_address_width = 11,
1360                 ram_block3a_1.port_a_data_width = 1,
1361                 ram_block3a_1.port_a_first_address = 0,
1362                 ram_block3a_1.port_a_first_bit_number = 1,
1363                 ram_block3a_1.port_a_last_address = 2047,
1364                 ram_block3a_1.port_a_logical_ram_depth = 2048,
1365                 ram_block3a_1.port_a_logical_ram_width = 16,
1366                 ram_block3a_1.port_b_address_clear = "none",
1367                 ram_block3a_1.port_b_address_clock = "clock1",
1368                 ram_block3a_1.port_b_address_width = 11,
1369                 ram_block3a_1.port_b_data_out_clear = "none",
1370                 ram_block3a_1.port_b_data_out_clock = "none",
1371                 ram_block3a_1.port_b_data_width = 1,
1372                 ram_block3a_1.port_b_first_address = 0,
1373                 ram_block3a_1.port_b_first_bit_number = 1,
1374                 ram_block3a_1.port_b_last_address = 2047,
1375                 ram_block3a_1.port_b_logical_ram_depth = 2048,
1376                 ram_block3a_1.port_b_logical_ram_width = 16,
1377                 ram_block3a_1.port_b_read_enable_write_enable_clock = "clock1",
1378                 ram_block3a_1.ram_block_type = "auto",
1379                 ram_block3a_1.lpm_type = "cyclone_ram_block";
1380         cyclone_ram_block   ram_block3a_2
1381         (
1382         .clk0(clock0),
1383         .clk1(clock1),
1384         .ena0(wren_a),
1385         .ena1(clocken1),
1386         .portaaddr({address_a_wire[10:0]}),
1387         .portadatain({data_a[2]}),
1388         .portadataout(),
1389         .portawe(1'b1),
1390         .portbaddr({address_b_wire[10:0]}),
1391         .portbdataout(wire_ram_block3a_2portbdataout[0:0]),
1392         .portbrewe(1'b1)
1393         `ifdef FORMAL_VERIFICATION
1394         `else
1395         // synopsys translate_off
1396         `endif
1397         ,
1398         .clr0(1'b0),
1399         .clr1(1'b0),
1400         .portabyteenamasks(1'b1),
1401         .portbbyteenamasks(1'b1),
1402         .portbdatain(1'b0)
1403         `ifdef FORMAL_VERIFICATION
1404         `else
1405         // synopsys translate_on
1406         `endif
1407         // synopsys translate_off
1408         ,
1409         .devclrn(),
1410         .devpor()
1411         // synopsys translate_on
1412         );
1413         defparam
1414                 ram_block3a_2.connectivity_checking = "OFF",
1415                 ram_block3a_2.logical_ram_name = "ALTSYNCRAM",
1416                 ram_block3a_2.mixed_port_feed_through_mode = "dont_care",
1417                 ram_block3a_2.operation_mode = "dual_port",
1418                 ram_block3a_2.port_a_address_width = 11,
1419                 ram_block3a_2.port_a_data_width = 1,
1420                 ram_block3a_2.port_a_first_address = 0,
1421                 ram_block3a_2.port_a_first_bit_number = 2,
1422                 ram_block3a_2.port_a_last_address = 2047,
1423                 ram_block3a_2.port_a_logical_ram_depth = 2048,
1424                 ram_block3a_2.port_a_logical_ram_width = 16,
1425                 ram_block3a_2.port_b_address_clear = "none",
1426                 ram_block3a_2.port_b_address_clock = "clock1",
1427                 ram_block3a_2.port_b_address_width = 11,
1428                 ram_block3a_2.port_b_data_out_clear = "none",
1429                 ram_block3a_2.port_b_data_out_clock = "none",
1430                 ram_block3a_2.port_b_data_width = 1,
1431                 ram_block3a_2.port_b_first_address = 0,
1432                 ram_block3a_2.port_b_first_bit_number = 2,
1433                 ram_block3a_2.port_b_last_address = 2047,
1434                 ram_block3a_2.port_b_logical_ram_depth = 2048,
1435                 ram_block3a_2.port_b_logical_ram_width = 16,
1436                 ram_block3a_2.port_b_read_enable_write_enable_clock = "clock1",
1437                 ram_block3a_2.ram_block_type = "auto",
1438                 ram_block3a_2.lpm_type = "cyclone_ram_block";
1439         cyclone_ram_block   ram_block3a_3
1440         (
1441         .clk0(clock0),
1442         .clk1(clock1),
1443         .ena0(wren_a),
1444         .ena1(clocken1),
1445         .portaaddr({address_a_wire[10:0]}),
1446         .portadatain({data_a[3]}),
1447         .portadataout(),
1448         .portawe(1'b1),
1449         .portbaddr({address_b_wire[10:0]}),
1450         .portbdataout(wire_ram_block3a_3portbdataout[0:0]),
1451         .portbrewe(1'b1)
1452         `ifdef FORMAL_VERIFICATION
1453         `else
1454         // synopsys translate_off
1455         `endif
1456         ,
1457         .clr0(1'b0),
1458         .clr1(1'b0),
1459         .portabyteenamasks(1'b1),
1460         .portbbyteenamasks(1'b1),
1461         .portbdatain(1'b0)
1462         `ifdef FORMAL_VERIFICATION
1463         `else
1464         // synopsys translate_on
1465         `endif
1466         // synopsys translate_off
1467         ,
1468         .devclrn(),
1469         .devpor()
1470         // synopsys translate_on
1471         );
1472         defparam
1473                 ram_block3a_3.connectivity_checking = "OFF",
1474                 ram_block3a_3.logical_ram_name = "ALTSYNCRAM",
1475                 ram_block3a_3.mixed_port_feed_through_mode = "dont_care",
1476                 ram_block3a_3.operation_mode = "dual_port",
1477                 ram_block3a_3.port_a_address_width = 11,
1478                 ram_block3a_3.port_a_data_width = 1,
1479                 ram_block3a_3.port_a_first_address = 0,
1480                 ram_block3a_3.port_a_first_bit_number = 3,
1481                 ram_block3a_3.port_a_last_address = 2047,
1482                 ram_block3a_3.port_a_logical_ram_depth = 2048,
1483                 ram_block3a_3.port_a_logical_ram_width = 16,
1484                 ram_block3a_3.port_b_address_clear = "none",
1485                 ram_block3a_3.port_b_address_clock = "clock1",
1486                 ram_block3a_3.port_b_address_width = 11,
1487                 ram_block3a_3.port_b_data_out_clear = "none",
1488                 ram_block3a_3.port_b_data_out_clock = "none",
1489                 ram_block3a_3.port_b_data_width = 1,
1490                 ram_block3a_3.port_b_first_address = 0,
1491                 ram_block3a_3.port_b_first_bit_number = 3,
1492                 ram_block3a_3.port_b_last_address = 2047,
1493                 ram_block3a_3.port_b_logical_ram_depth = 2048,
1494                 ram_block3a_3.port_b_logical_ram_width = 16,
1495                 ram_block3a_3.port_b_read_enable_write_enable_clock = "clock1",
1496                 ram_block3a_3.ram_block_type = "auto",
1497                 ram_block3a_3.lpm_type = "cyclone_ram_block";
1498         cyclone_ram_block   ram_block3a_4
1499         (
1500         .clk0(clock0),
1501         .clk1(clock1),
1502         .ena0(wren_a),
1503         .ena1(clocken1),
1504         .portaaddr({address_a_wire[10:0]}),
1505         .portadatain({data_a[4]}),
1506         .portadataout(),
1507         .portawe(1'b1),
1508         .portbaddr({address_b_wire[10:0]}),
1509         .portbdataout(wire_ram_block3a_4portbdataout[0:0]),
1510         .portbrewe(1'b1)
1511         `ifdef FORMAL_VERIFICATION
1512         `else
1513         // synopsys translate_off
1514         `endif
1515         ,
1516         .clr0(1'b0),
1517         .clr1(1'b0),
1518         .portabyteenamasks(1'b1),
1519         .portbbyteenamasks(1'b1),
1520         .portbdatain(1'b0)
1521         `ifdef FORMAL_VERIFICATION
1522         `else
1523         // synopsys translate_on
1524         `endif
1525         // synopsys translate_off
1526         ,
1527         .devclrn(),
1528         .devpor()
1529         // synopsys translate_on
1530         );
1531         defparam
1532                 ram_block3a_4.connectivity_checking = "OFF",
1533                 ram_block3a_4.logical_ram_name = "ALTSYNCRAM",
1534                 ram_block3a_4.mixed_port_feed_through_mode = "dont_care",
1535                 ram_block3a_4.operation_mode = "dual_port",
1536                 ram_block3a_4.port_a_address_width = 11,
1537                 ram_block3a_4.port_a_data_width = 1,
1538                 ram_block3a_4.port_a_first_address = 0,
1539                 ram_block3a_4.port_a_first_bit_number = 4,
1540                 ram_block3a_4.port_a_last_address = 2047,
1541                 ram_block3a_4.port_a_logical_ram_depth = 2048,
1542                 ram_block3a_4.port_a_logical_ram_width = 16,
1543                 ram_block3a_4.port_b_address_clear = "none",
1544                 ram_block3a_4.port_b_address_clock = "clock1",
1545                 ram_block3a_4.port_b_address_width = 11,
1546                 ram_block3a_4.port_b_data_out_clear = "none",
1547                 ram_block3a_4.port_b_data_out_clock = "none",
1548                 ram_block3a_4.port_b_data_width = 1,
1549                 ram_block3a_4.port_b_first_address = 0,
1550                 ram_block3a_4.port_b_first_bit_number = 4,
1551                 ram_block3a_4.port_b_last_address = 2047,
1552                 ram_block3a_4.port_b_logical_ram_depth = 2048,
1553                 ram_block3a_4.port_b_logical_ram_width = 16,
1554                 ram_block3a_4.port_b_read_enable_write_enable_clock = "clock1",
1555                 ram_block3a_4.ram_block_type = "auto",
1556                 ram_block3a_4.lpm_type = "cyclone_ram_block";
1557         cyclone_ram_block   ram_block3a_5
1558         (
1559         .clk0(clock0),
1560         .clk1(clock1),
1561         .ena0(wren_a),
1562         .ena1(clocken1),
1563         .portaaddr({address_a_wire[10:0]}),
1564         .portadatain({data_a[5]}),
1565         .portadataout(),
1566         .portawe(1'b1),
1567         .portbaddr({address_b_wire[10:0]}),
1568         .portbdataout(wire_ram_block3a_5portbdataout[0:0]),
1569         .portbrewe(1'b1)
1570         `ifdef FORMAL_VERIFICATION
1571         `else
1572         // synopsys translate_off
1573         `endif
1574         ,
1575         .clr0(1'b0),
1576         .clr1(1'b0),
1577         .portabyteenamasks(1'b1),
1578         .portbbyteenamasks(1'b1),
1579         .portbdatain(1'b0)
1580         `ifdef FORMAL_VERIFICATION
1581         `else
1582         // synopsys translate_on
1583         `endif
1584         // synopsys translate_off
1585         ,
1586         .devclrn(),
1587         .devpor()
1588         // synopsys translate_on
1589         );
1590         defparam
1591                 ram_block3a_5.connectivity_checking = "OFF",
1592                 ram_block3a_5.logical_ram_name = "ALTSYNCRAM",
1593                 ram_block3a_5.mixed_port_feed_through_mode = "dont_care",
1594                 ram_block3a_5.operation_mode = "dual_port",
1595                 ram_block3a_5.port_a_address_width = 11,
1596                 ram_block3a_5.port_a_data_width = 1,
1597                 ram_block3a_5.port_a_first_address = 0,
1598                 ram_block3a_5.port_a_first_bit_number = 5,
1599                 ram_block3a_5.port_a_last_address = 2047,
1600                 ram_block3a_5.port_a_logical_ram_depth = 2048,
1601                 ram_block3a_5.port_a_logical_ram_width = 16,
1602                 ram_block3a_5.port_b_address_clear = "none",
1603                 ram_block3a_5.port_b_address_clock = "clock1",
1604                 ram_block3a_5.port_b_address_width = 11,
1605                 ram_block3a_5.port_b_data_out_clear = "none",
1606                 ram_block3a_5.port_b_data_out_clock = "none",
1607                 ram_block3a_5.port_b_data_width = 1,
1608                 ram_block3a_5.port_b_first_address = 0,
1609                 ram_block3a_5.port_b_first_bit_number = 5,
1610                 ram_block3a_5.port_b_last_address = 2047,
1611                 ram_block3a_5.port_b_logical_ram_depth = 2048,
1612                 ram_block3a_5.port_b_logical_ram_width = 16,
1613                 ram_block3a_5.port_b_read_enable_write_enable_clock = "clock1",
1614                 ram_block3a_5.ram_block_type = "auto",
1615                 ram_block3a_5.lpm_type = "cyclone_ram_block";
1616         cyclone_ram_block   ram_block3a_6
1617         (
1618         .clk0(clock0),
1619         .clk1(clock1),
1620         .ena0(wren_a),
1621         .ena1(clocken1),
1622         .portaaddr({address_a_wire[10:0]}),
1623         .portadatain({data_a[6]}),
1624         .portadataout(),
1625         .portawe(1'b1),
1626         .portbaddr({address_b_wire[10:0]}),
1627         .portbdataout(wire_ram_block3a_6portbdataout[0:0]),
1628         .portbrewe(1'b1)
1629         `ifdef FORMAL_VERIFICATION
1630         `else
1631         // synopsys translate_off
1632         `endif
1633         ,
1634         .clr0(1'b0),
1635         .clr1(1'b0),
1636         .portabyteenamasks(1'b1),
1637         .portbbyteenamasks(1'b1),
1638         .portbdatain(1'b0)
1639         `ifdef FORMAL_VERIFICATION
1640         `else
1641         // synopsys translate_on
1642         `endif
1643         // synopsys translate_off
1644         ,
1645         .devclrn(),
1646         .devpor()
1647         // synopsys translate_on
1648         );
1649         defparam
1650                 ram_block3a_6.connectivity_checking = "OFF",
1651                 ram_block3a_6.logical_ram_name = "ALTSYNCRAM",
1652                 ram_block3a_6.mixed_port_feed_through_mode = "dont_care",
1653                 ram_block3a_6.operation_mode = "dual_port",
1654                 ram_block3a_6.port_a_address_width = 11,
1655                 ram_block3a_6.port_a_data_width = 1,
1656                 ram_block3a_6.port_a_first_address = 0,
1657                 ram_block3a_6.port_a_first_bit_number = 6,
1658                 ram_block3a_6.port_a_last_address = 2047,
1659                 ram_block3a_6.port_a_logical_ram_depth = 2048,
1660                 ram_block3a_6.port_a_logical_ram_width = 16,
1661                 ram_block3a_6.port_b_address_clear = "none",
1662                 ram_block3a_6.port_b_address_clock = "clock1",
1663                 ram_block3a_6.port_b_address_width = 11,
1664                 ram_block3a_6.port_b_data_out_clear = "none",
1665                 ram_block3a_6.port_b_data_out_clock = "none",
1666                 ram_block3a_6.port_b_data_width = 1,
1667                 ram_block3a_6.port_b_first_address = 0,
1668                 ram_block3a_6.port_b_first_bit_number = 6,
1669                 ram_block3a_6.port_b_last_address = 2047,
1670                 ram_block3a_6.port_b_logical_ram_depth = 2048,
1671                 ram_block3a_6.port_b_logical_ram_width = 16,
1672                 ram_block3a_6.port_b_read_enable_write_enable_clock = "clock1",
1673                 ram_block3a_6.ram_block_type = "auto",
1674                 ram_block3a_6.lpm_type = "cyclone_ram_block";
1675         cyclone_ram_block   ram_block3a_7
1676         (
1677         .clk0(clock0),
1678         .clk1(clock1),
1679         .ena0(wren_a),
1680         .ena1(clocken1),
1681         .portaaddr({address_a_wire[10:0]}),
1682         .portadatain({data_a[7]}),
1683         .portadataout(),
1684         .portawe(1'b1),
1685         .portbaddr({address_b_wire[10:0]}),
1686         .portbdataout(wire_ram_block3a_7portbdataout[0:0]),
1687         .portbrewe(1'b1)
1688         `ifdef FORMAL_VERIFICATION
1689         `else
1690         // synopsys translate_off
1691         `endif
1692         ,
1693         .clr0(1'b0),
1694         .clr1(1'b0),
1695         .portabyteenamasks(1'b1),
1696         .portbbyteenamasks(1'b1),
1697         .portbdatain(1'b0)
1698         `ifdef FORMAL_VERIFICATION
1699         `else
1700         // synopsys translate_on
1701         `endif
1702         // synopsys translate_off
1703         ,
1704         .devclrn(),
1705         .devpor()
1706         // synopsys translate_on
1707         );
1708         defparam
1709                 ram_block3a_7.connectivity_checking = "OFF",
1710                 ram_block3a_7.logical_ram_name = "ALTSYNCRAM",
1711                 ram_block3a_7.mixed_port_feed_through_mode = "dont_care",
1712                 ram_block3a_7.operation_mode = "dual_port",
1713                 ram_block3a_7.port_a_address_width = 11,
1714                 ram_block3a_7.port_a_data_width = 1,
1715                 ram_block3a_7.port_a_first_address = 0,
1716                 ram_block3a_7.port_a_first_bit_number = 7,
1717                 ram_block3a_7.port_a_last_address = 2047,
1718                 ram_block3a_7.port_a_logical_ram_depth = 2048,
1719                 ram_block3a_7.port_a_logical_ram_width = 16,
1720                 ram_block3a_7.port_b_address_clear = "none",
1721                 ram_block3a_7.port_b_address_clock = "clock1",
1722                 ram_block3a_7.port_b_address_width = 11,
1723                 ram_block3a_7.port_b_data_out_clear = "none",
1724                 ram_block3a_7.port_b_data_out_clock = "none",
1725                 ram_block3a_7.port_b_data_width = 1,
1726                 ram_block3a_7.port_b_first_address = 0,
1727                 ram_block3a_7.port_b_first_bit_number = 7,
1728                 ram_block3a_7.port_b_last_address = 2047,
1729                 ram_block3a_7.port_b_logical_ram_depth = 2048,
1730                 ram_block3a_7.port_b_logical_ram_width = 16,
1731                 ram_block3a_7.port_b_read_enable_write_enable_clock = "clock1",
1732                 ram_block3a_7.ram_block_type = "auto",
1733                 ram_block3a_7.lpm_type = "cyclone_ram_block";
1734         cyclone_ram_block   ram_block3a_8
1735         (
1736         .clk0(clock0),
1737         .clk1(clock1),
1738         .ena0(wren_a),
1739         .ena1(clocken1),
1740         .portaaddr({address_a_wire[10:0]}),
1741         .portadatain({data_a[8]}),
1742         .portadataout(),
1743         .portawe(1'b1),
1744         .portbaddr({address_b_wire[10:0]}),
1745         .portbdataout(wire_ram_block3a_8portbdataout[0:0]),
1746         .portbrewe(1'b1)
1747         `ifdef FORMAL_VERIFICATION
1748         `else
1749         // synopsys translate_off
1750         `endif
1751         ,
1752         .clr0(1'b0),
1753         .clr1(1'b0),
1754         .portabyteenamasks(1'b1),
1755         .portbbyteenamasks(1'b1),
1756         .portbdatain(1'b0)
1757         `ifdef FORMAL_VERIFICATION
1758         `else
1759         // synopsys translate_on
1760         `endif
1761         // synopsys translate_off
1762         ,
1763         .devclrn(),
1764         .devpor()
1765         // synopsys translate_on
1766         );
1767         defparam
1768                 ram_block3a_8.connectivity_checking = "OFF",
1769                 ram_block3a_8.logical_ram_name = "ALTSYNCRAM",
1770                 ram_block3a_8.mixed_port_feed_through_mode = "dont_care",
1771                 ram_block3a_8.operation_mode = "dual_port",
1772                 ram_block3a_8.port_a_address_width = 11,
1773                 ram_block3a_8.port_a_data_width = 1,
1774                 ram_block3a_8.port_a_first_address = 0,
1775                 ram_block3a_8.port_a_first_bit_number = 8,
1776                 ram_block3a_8.port_a_last_address = 2047,
1777                 ram_block3a_8.port_a_logical_ram_depth = 2048,
1778                 ram_block3a_8.port_a_logical_ram_width = 16,
1779                 ram_block3a_8.port_b_address_clear = "none",
1780                 ram_block3a_8.port_b_address_clock = "clock1",
1781                 ram_block3a_8.port_b_address_width = 11,
1782                 ram_block3a_8.port_b_data_out_clear = "none",
1783                 ram_block3a_8.port_b_data_out_clock = "none",
1784                 ram_block3a_8.port_b_data_width = 1,
1785                 ram_block3a_8.port_b_first_address = 0,
1786                 ram_block3a_8.port_b_first_bit_number = 8,
1787                 ram_block3a_8.port_b_last_address = 2047,
1788                 ram_block3a_8.port_b_logical_ram_depth = 2048,
1789                 ram_block3a_8.port_b_logical_ram_width = 16,
1790                 ram_block3a_8.port_b_read_enable_write_enable_clock = "clock1",
1791                 ram_block3a_8.ram_block_type = "auto",
1792                 ram_block3a_8.lpm_type = "cyclone_ram_block";
1793         cyclone_ram_block   ram_block3a_9
1794         (
1795         .clk0(clock0),
1796         .clk1(clock1),
1797         .ena0(wren_a),
1798         .ena1(clocken1),
1799         .portaaddr({address_a_wire[10:0]}),
1800         .portadatain({data_a[9]}),
1801         .portadataout(),
1802         .portawe(1'b1),
1803         .portbaddr({address_b_wire[10:0]}),
1804         .portbdataout(wire_ram_block3a_9portbdataout[0:0]),
1805         .portbrewe(1'b1)
1806         `ifdef FORMAL_VERIFICATION
1807         `else
1808         // synopsys translate_off
1809         `endif
1810         ,
1811         .clr0(1'b0),
1812         .clr1(1'b0),
1813         .portabyteenamasks(1'b1),
1814         .portbbyteenamasks(1'b1),
1815         .portbdatain(1'b0)
1816         `ifdef FORMAL_VERIFICATION
1817         `else
1818         // synopsys translate_on
1819         `endif
1820         // synopsys translate_off
1821         ,
1822         .devclrn(),
1823         .devpor()
1824         // synopsys translate_on
1825         );
1826         defparam
1827                 ram_block3a_9.connectivity_checking = "OFF",
1828                 ram_block3a_9.logical_ram_name = "ALTSYNCRAM",
1829                 ram_block3a_9.mixed_port_feed_through_mode = "dont_care",
1830                 ram_block3a_9.operation_mode = "dual_port",
1831                 ram_block3a_9.port_a_address_width = 11,
1832                 ram_block3a_9.port_a_data_width = 1,
1833                 ram_block3a_9.port_a_first_address = 0,
1834                 ram_block3a_9.port_a_first_bit_number = 9,
1835                 ram_block3a_9.port_a_last_address = 2047,
1836                 ram_block3a_9.port_a_logical_ram_depth = 2048,
1837                 ram_block3a_9.port_a_logical_ram_width = 16,
1838                 ram_block3a_9.port_b_address_clear = "none",
1839                 ram_block3a_9.port_b_address_clock = "clock1",
1840                 ram_block3a_9.port_b_address_width = 11,
1841                 ram_block3a_9.port_b_data_out_clear = "none",
1842                 ram_block3a_9.port_b_data_out_clock = "none",
1843                 ram_block3a_9.port_b_data_width = 1,
1844                 ram_block3a_9.port_b_first_address = 0,
1845                 ram_block3a_9.port_b_first_bit_number = 9,
1846                 ram_block3a_9.port_b_last_address = 2047,
1847                 ram_block3a_9.port_b_logical_ram_depth = 2048,
1848                 ram_block3a_9.port_b_logical_ram_width = 16,
1849                 ram_block3a_9.port_b_read_enable_write_enable_clock = "clock1",
1850                 ram_block3a_9.ram_block_type = "auto",
1851                 ram_block3a_9.lpm_type = "cyclone_ram_block";
1852         cyclone_ram_block   ram_block3a_10
1853         (
1854         .clk0(clock0),
1855         .clk1(clock1),
1856         .ena0(wren_a),
1857         .ena1(clocken1),
1858         .portaaddr({address_a_wire[10:0]}),
1859         .portadatain({data_a[10]}),
1860         .portadataout(),
1861         .portawe(1'b1),
1862         .portbaddr({address_b_wire[10:0]}),
1863         .portbdataout(wire_ram_block3a_10portbdataout[0:0]),
1864         .portbrewe(1'b1)
1865         `ifdef FORMAL_VERIFICATION
1866         `else
1867         // synopsys translate_off
1868         `endif
1869         ,
1870         .clr0(1'b0),
1871         .clr1(1'b0),
1872         .portabyteenamasks(1'b1),
1873         .portbbyteenamasks(1'b1),
1874         .portbdatain(1'b0)
1875         `ifdef FORMAL_VERIFICATION
1876         `else
1877         // synopsys translate_on
1878         `endif
1879         // synopsys translate_off
1880         ,
1881         .devclrn(),
1882         .devpor()
1883         // synopsys translate_on
1884         );
1885         defparam
1886                 ram_block3a_10.connectivity_checking = "OFF",
1887                 ram_block3a_10.logical_ram_name = "ALTSYNCRAM",
1888                 ram_block3a_10.mixed_port_feed_through_mode = "dont_care",
1889                 ram_block3a_10.operation_mode = "dual_port",
1890                 ram_block3a_10.port_a_address_width = 11,
1891                 ram_block3a_10.port_a_data_width = 1,
1892                 ram_block3a_10.port_a_first_address = 0,
1893                 ram_block3a_10.port_a_first_bit_number = 10,
1894                 ram_block3a_10.port_a_last_address = 2047,
1895                 ram_block3a_10.port_a_logical_ram_depth = 2048,
1896                 ram_block3a_10.port_a_logical_ram_width = 16,
1897                 ram_block3a_10.port_b_address_clear = "none",
1898                 ram_block3a_10.port_b_address_clock = "clock1",
1899                 ram_block3a_10.port_b_address_width = 11,
1900                 ram_block3a_10.port_b_data_out_clear = "none",
1901                 ram_block3a_10.port_b_data_out_clock = "none",
1902                 ram_block3a_10.port_b_data_width = 1,
1903                 ram_block3a_10.port_b_first_address = 0,
1904                 ram_block3a_10.port_b_first_bit_number = 10,
1905                 ram_block3a_10.port_b_last_address = 2047,
1906                 ram_block3a_10.port_b_logical_ram_depth = 2048,
1907                 ram_block3a_10.port_b_logical_ram_width = 16,
1908                 ram_block3a_10.port_b_read_enable_write_enable_clock = "clock1",
1909                 ram_block3a_10.ram_block_type = "auto",
1910                 ram_block3a_10.lpm_type = "cyclone_ram_block";
1911         cyclone_ram_block   ram_block3a_11
1912         (
1913         .clk0(clock0),
1914         .clk1(clock1),
1915         .ena0(wren_a),
1916         .ena1(clocken1),
1917         .portaaddr({address_a_wire[10:0]}),
1918         .portadatain({data_a[11]}),
1919         .portadataout(),
1920         .portawe(1'b1),
1921         .portbaddr({address_b_wire[10:0]}),
1922         .portbdataout(wire_ram_block3a_11portbdataout[0:0]),
1923         .portbrewe(1'b1)
1924         `ifdef FORMAL_VERIFICATION
1925         `else
1926         // synopsys translate_off
1927         `endif
1928         ,
1929         .clr0(1'b0),
1930         .clr1(1'b0),
1931         .portabyteenamasks(1'b1),
1932         .portbbyteenamasks(1'b1),
1933         .portbdatain(1'b0)
1934         `ifdef FORMAL_VERIFICATION
1935         `else
1936         // synopsys translate_on
1937         `endif
1938         // synopsys translate_off
1939         ,
1940         .devclrn(),
1941         .devpor()
1942         // synopsys translate_on
1943         );
1944         defparam
1945                 ram_block3a_11.connectivity_checking = "OFF",
1946                 ram_block3a_11.logical_ram_name = "ALTSYNCRAM",
1947                 ram_block3a_11.mixed_port_feed_through_mode = "dont_care",
1948                 ram_block3a_11.operation_mode = "dual_port",
1949                 ram_block3a_11.port_a_address_width = 11,
1950                 ram_block3a_11.port_a_data_width = 1,
1951                 ram_block3a_11.port_a_first_address = 0,
1952                 ram_block3a_11.port_a_first_bit_number = 11,
1953                 ram_block3a_11.port_a_last_address = 2047,
1954                 ram_block3a_11.port_a_logical_ram_depth = 2048,
1955                 ram_block3a_11.port_a_logical_ram_width = 16,
1956                 ram_block3a_11.port_b_address_clear = "none",
1957                 ram_block3a_11.port_b_address_clock = "clock1",
1958                 ram_block3a_11.port_b_address_width = 11,
1959                 ram_block3a_11.port_b_data_out_clear = "none",
1960                 ram_block3a_11.port_b_data_out_clock = "none",
1961                 ram_block3a_11.port_b_data_width = 1,
1962                 ram_block3a_11.port_b_first_address = 0,
1963                 ram_block3a_11.port_b_first_bit_number = 11,
1964                 ram_block3a_11.port_b_last_address = 2047,
1965                 ram_block3a_11.port_b_logical_ram_depth = 2048,
1966                 ram_block3a_11.port_b_logical_ram_width = 16,
1967                 ram_block3a_11.port_b_read_enable_write_enable_clock = "clock1",
1968                 ram_block3a_11.ram_block_type = "auto",
1969                 ram_block3a_11.lpm_type = "cyclone_ram_block";
1970         cyclone_ram_block   ram_block3a_12
1971         (
1972         .clk0(clock0),
1973         .clk1(clock1),
1974         .ena0(wren_a),
1975         .ena1(clocken1),
1976         .portaaddr({address_a_wire[10:0]}),
1977         .portadatain({data_a[12]}),
1978         .portadataout(),
1979         .portawe(1'b1),
1980         .portbaddr({address_b_wire[10:0]}),
1981         .portbdataout(wire_ram_block3a_12portbdataout[0:0]),
1982         .portbrewe(1'b1)
1983         `ifdef FORMAL_VERIFICATION
1984         `else
1985         // synopsys translate_off
1986         `endif
1987         ,
1988         .clr0(1'b0),
1989         .clr1(1'b0),
1990         .portabyteenamasks(1'b1),
1991         .portbbyteenamasks(1'b1),
1992         .portbdatain(1'b0)
1993         `ifdef FORMAL_VERIFICATION
1994         `else
1995         // synopsys translate_on
1996         `endif
1997         // synopsys translate_off
1998         ,
1999         .devclrn(),
2000         .devpor()
2001         // synopsys translate_on
2002         );
2003         defparam
2004                 ram_block3a_12.connectivity_checking = "OFF",
2005                 ram_block3a_12.logical_ram_name = "ALTSYNCRAM",
2006                 ram_block3a_12.mixed_port_feed_through_mode = "dont_care",
2007                 ram_block3a_12.operation_mode = "dual_port",
2008                 ram_block3a_12.port_a_address_width = 11,
2009                 ram_block3a_12.port_a_data_width = 1,
2010                 ram_block3a_12.port_a_first_address = 0,
2011                 ram_block3a_12.port_a_first_bit_number = 12,
2012                 ram_block3a_12.port_a_last_address = 2047,
2013                 ram_block3a_12.port_a_logical_ram_depth = 2048,
2014                 ram_block3a_12.port_a_logical_ram_width = 16,
2015                 ram_block3a_12.port_b_address_clear = "none",
2016                 ram_block3a_12.port_b_address_clock = "clock1",
2017                 ram_block3a_12.port_b_address_width = 11,
2018                 ram_block3a_12.port_b_data_out_clear = "none",
2019                 ram_block3a_12.port_b_data_out_clock = "none",
2020                 ram_block3a_12.port_b_data_width = 1,
2021                 ram_block3a_12.port_b_first_address = 0,
2022                 ram_block3a_12.port_b_first_bit_number = 12,
2023                 ram_block3a_12.port_b_last_address = 2047,
2024                 ram_block3a_12.port_b_logical_ram_depth = 2048,
2025                 ram_block3a_12.port_b_logical_ram_width = 16,
2026                 ram_block3a_12.port_b_read_enable_write_enable_clock = "clock1",
2027                 ram_block3a_12.ram_block_type = "auto",
2028                 ram_block3a_12.lpm_type = "cyclone_ram_block";
2029         cyclone_ram_block   ram_block3a_13
2030         (
2031         .clk0(clock0),
2032         .clk1(clock1),
2033         .ena0(wren_a),
2034         .ena1(clocken1),
2035         .portaaddr({address_a_wire[10:0]}),
2036         .portadatain({data_a[13]}),
2037         .portadataout(),
2038         .portawe(1'b1),
2039         .portbaddr({address_b_wire[10:0]}),
2040         .portbdataout(wire_ram_block3a_13portbdataout[0:0]),
2041         .portbrewe(1'b1)
2042         `ifdef FORMAL_VERIFICATION
2043         `else
2044         // synopsys translate_off
2045         `endif
2046         ,
2047         .clr0(1'b0),
2048         .clr1(1'b0),
2049         .portabyteenamasks(1'b1),
2050         .portbbyteenamasks(1'b1),
2051         .portbdatain(1'b0)
2052         `ifdef FORMAL_VERIFICATION
2053         `else
2054         // synopsys translate_on
2055         `endif
2056         // synopsys translate_off
2057         ,
2058         .devclrn(),
2059         .devpor()
2060         // synopsys translate_on
2061         );
2062         defparam
2063                 ram_block3a_13.connectivity_checking = "OFF",
2064                 ram_block3a_13.logical_ram_name = "ALTSYNCRAM",
2065                 ram_block3a_13.mixed_port_feed_through_mode = "dont_care",
2066                 ram_block3a_13.operation_mode = "dual_port",
2067                 ram_block3a_13.port_a_address_width = 11,
2068                 ram_block3a_13.port_a_data_width = 1,
2069                 ram_block3a_13.port_a_first_address = 0,
2070                 ram_block3a_13.port_a_first_bit_number = 13,
2071                 ram_block3a_13.port_a_last_address = 2047,
2072                 ram_block3a_13.port_a_logical_ram_depth = 2048,
2073                 ram_block3a_13.port_a_logical_ram_width = 16,
2074                 ram_block3a_13.port_b_address_clear = "none",
2075                 ram_block3a_13.port_b_address_clock = "clock1",
2076                 ram_block3a_13.port_b_address_width = 11,
2077                 ram_block3a_13.port_b_data_out_clear = "none",
2078                 ram_block3a_13.port_b_data_out_clock = "none",
2079                 ram_block3a_13.port_b_data_width = 1,
2080                 ram_block3a_13.port_b_first_address = 0,
2081                 ram_block3a_13.port_b_first_bit_number = 13,
2082                 ram_block3a_13.port_b_last_address = 2047,
2083                 ram_block3a_13.port_b_logical_ram_depth = 2048,
2084                 ram_block3a_13.port_b_logical_ram_width = 16,
2085                 ram_block3a_13.port_b_read_enable_write_enable_clock = "clock1",
2086                 ram_block3a_13.ram_block_type = "auto",
2087                 ram_block3a_13.lpm_type = "cyclone_ram_block";
2088         cyclone_ram_block   ram_block3a_14
2089         (
2090         .clk0(clock0),
2091         .clk1(clock1),
2092         .ena0(wren_a),
2093         .ena1(clocken1),
2094         .portaaddr({address_a_wire[10:0]}),
2095         .portadatain({data_a[14]}),
2096         .portadataout(),
2097         .portawe(1'b1),
2098         .portbaddr({address_b_wire[10:0]}),
2099         .portbdataout(wire_ram_block3a_14portbdataout[0:0]),
2100         .portbrewe(1'b1)
2101         `ifdef FORMAL_VERIFICATION
2102         `else
2103         // synopsys translate_off
2104         `endif
2105         ,
2106         .clr0(1'b0),
2107         .clr1(1'b0),
2108         .portabyteenamasks(1'b1),
2109         .portbbyteenamasks(1'b1),
2110         .portbdatain(1'b0)
2111         `ifdef FORMAL_VERIFICATION
2112         `else
2113         // synopsys translate_on
2114         `endif
2115         // synopsys translate_off
2116         ,
2117         .devclrn(),
2118         .devpor()
2119         // synopsys translate_on
2120         );
2121         defparam
2122                 ram_block3a_14.connectivity_checking = "OFF",
2123                 ram_block3a_14.logical_ram_name = "ALTSYNCRAM",
2124                 ram_block3a_14.mixed_port_feed_through_mode = "dont_care",
2125                 ram_block3a_14.operation_mode = "dual_port",
2126                 ram_block3a_14.port_a_address_width = 11,
2127                 ram_block3a_14.port_a_data_width = 1,
2128                 ram_block3a_14.port_a_first_address = 0,
2129                 ram_block3a_14.port_a_first_bit_number = 14,
2130                 ram_block3a_14.port_a_last_address = 2047,
2131                 ram_block3a_14.port_a_logical_ram_depth = 2048,
2132                 ram_block3a_14.port_a_logical_ram_width = 16,
2133                 ram_block3a_14.port_b_address_clear = "none",
2134                 ram_block3a_14.port_b_address_clock = "clock1",
2135                 ram_block3a_14.port_b_address_width = 11,
2136                 ram_block3a_14.port_b_data_out_clear = "none",
2137                 ram_block3a_14.port_b_data_out_clock = "none",
2138                 ram_block3a_14.port_b_data_width = 1,
2139                 ram_block3a_14.port_b_first_address = 0,
2140                 ram_block3a_14.port_b_first_bit_number = 14,
2141                 ram_block3a_14.port_b_last_address = 2047,
2142                 ram_block3a_14.port_b_logical_ram_depth = 2048,
2143                 ram_block3a_14.port_b_logical_ram_width = 16,
2144                 ram_block3a_14.port_b_read_enable_write_enable_clock = "clock1",
2145                 ram_block3a_14.ram_block_type = "auto",
2146                 ram_block3a_14.lpm_type = "cyclone_ram_block";
2147         cyclone_ram_block   ram_block3a_15
2148         (
2149         .clk0(clock0),
2150         .clk1(clock1),
2151         .ena0(wren_a),
2152         .ena1(clocken1),
2153         .portaaddr({address_a_wire[10:0]}),
2154         .portadatain({data_a[15]}),
2155         .portadataout(),
2156         .portawe(1'b1),
2157         .portbaddr({address_b_wire[10:0]}),
2158         .portbdataout(wire_ram_block3a_15portbdataout[0:0]),
2159         .portbrewe(1'b1)
2160         `ifdef FORMAL_VERIFICATION
2161         `else
2162         // synopsys translate_off
2163         `endif
2164         ,
2165         .clr0(1'b0),
2166         .clr1(1'b0),
2167         .portabyteenamasks(1'b1),
2168         .portbbyteenamasks(1'b1),
2169         .portbdatain(1'b0)
2170         `ifdef FORMAL_VERIFICATION
2171         `else
2172         // synopsys translate_on
2173         `endif
2174         // synopsys translate_off
2175         ,
2176         .devclrn(),
2177         .devpor()
2178         // synopsys translate_on
2179         );
2180         defparam
2181                 ram_block3a_15.connectivity_checking = "OFF",
2182                 ram_block3a_15.logical_ram_name = "ALTSYNCRAM",
2183                 ram_block3a_15.mixed_port_feed_through_mode = "dont_care",
2184                 ram_block3a_15.operation_mode = "dual_port",
2185                 ram_block3a_15.port_a_address_width = 11,
2186                 ram_block3a_15.port_a_data_width = 1,
2187                 ram_block3a_15.port_a_first_address = 0,
2188                 ram_block3a_15.port_a_first_bit_number = 15,
2189                 ram_block3a_15.port_a_last_address = 2047,
2190                 ram_block3a_15.port_a_logical_ram_depth = 2048,
2191                 ram_block3a_15.port_a_logical_ram_width = 16,
2192                 ram_block3a_15.port_b_address_clear = "none",
2193                 ram_block3a_15.port_b_address_clock = "clock1",
2194                 ram_block3a_15.port_b_address_width = 11,
2195                 ram_block3a_15.port_b_data_out_clear = "none",
2196                 ram_block3a_15.port_b_data_out_clock = "none",
2197                 ram_block3a_15.port_b_data_width = 1,
2198                 ram_block3a_15.port_b_first_address = 0,
2199                 ram_block3a_15.port_b_first_bit_number = 15,
2200                 ram_block3a_15.port_b_last_address = 2047,
2201                 ram_block3a_15.port_b_logical_ram_depth = 2048,
2202                 ram_block3a_15.port_b_logical_ram_width = 16,
2203                 ram_block3a_15.port_b_read_enable_write_enable_clock = "clock1",
2204                 ram_block3a_15.ram_block_type = "auto",
2205                 ram_block3a_15.lpm_type = "cyclone_ram_block";
2206         assign
2207                 address_a_wire = address_a,
2208                 address_b_wire = address_b,
2209                 q_b = {wire_ram_block3a_15portbdataout[0], wire_ram_block3a_14portbdataout[0], wire_ram_block3a_13portbdataout[0], wire_ram_block3a_12portbdataout[0], wire_ram_block3a_11portbdataout[0], wire_ram_block3a_10portbdataout[0], wire_ram_block3a_9portbdataout[0], wire_ram_block3a_8portbdataout[0], wire_ram_block3a_7portbdataout[0], wire_ram_block3a_6portbdataout[0], wire_ram_block3a_5portbdataout[0], wire_ram_block3a_4portbdataout[0], wire_ram_block3a_3portbdataout[0], wire_ram_block3a_2portbdataout[0], wire_ram_block3a_1portbdataout[0], wire_ram_block3a_0portbdataout[0]};
2210 endmodule //fifo_2k_altsyncram_6pl
2211
2212
2213 //dffpipe DELAY=1 WIDTH=11 clock clrn d q
2214 //VERSION_BEGIN 5.0 cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ  VERSION_END
2215
2216 //synthesis_resources = lut 11
2217 //synopsys translate_off
2218 `timescale 1 ps / 1 ps
2219 //synopsys translate_on
2220 module  fifo_2k_dffpipe_ab3
2221         (
2222         clock,
2223         clrn,
2224         d,
2225         q) /* synthesis synthesis_clearbox=1 */
2226                 /* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF" */;
2227         input   clock;
2228         input   clrn;
2229         input   [10:0]  d;
2230         output   [10:0]  q;
2231
2232         wire    [10:0]  wire_dffe4a_D;
2233         reg     [10:0]  dffe4a;
2234         wire ena;
2235         wire prn;
2236         wire sclr;
2237
2238         // synopsys translate_off
2239         initial
2240                 dffe4a[0:0] = 0;
2241         // synopsys translate_on
2242         always @ ( posedge clock or  negedge prn or  negedge clrn)
2243                 if (prn == 1'b0) dffe4a[0:0] <= 1'b1;
2244                 else if (clrn == 1'b0) dffe4a[0:0] <= 1'b0;
2245                 else if  (ena == 1'b1)   dffe4a[0:0] <= wire_dffe4a_D[0:0];
2246         // synopsys translate_off
2247         initial
2248                 dffe4a[1:1] = 0;
2249         // synopsys translate_on
2250         always @ ( posedge clock or  negedge prn or  negedge clrn)
2251                 if (prn == 1'b0) dffe4a[1:1] <= 1'b1;
2252                 else if (clrn == 1'b0) dffe4a[1:1] <= 1'b0;
2253                 else if  (ena == 1'b1)   dffe4a[1:1] <= wire_dffe4a_D[1:1];
2254         // synopsys translate_off
2255         initial
2256                 dffe4a[2:2] = 0;
2257         // synopsys translate_on
2258         always @ ( posedge clock or  negedge prn or  negedge clrn)
2259                 if (prn == 1'b0) dffe4a[2:2] <= 1'b1;
2260                 else if (clrn == 1'b0) dffe4a[2:2] <= 1'b0;
2261                 else if  (ena == 1'b1)   dffe4a[2:2] <= wire_dffe4a_D[2:2];
2262         // synopsys translate_off
2263         initial
2264                 dffe4a[3:3] = 0;
2265         // synopsys translate_on
2266         always @ ( posedge clock or  negedge prn or  negedge clrn)
2267                 if (prn == 1'b0) dffe4a[3:3] <= 1'b1;
2268                 else if (clrn == 1'b0) dffe4a[3:3] <= 1'b0;
2269                 else if  (ena == 1'b1)   dffe4a[3:3] <= wire_dffe4a_D[3:3];
2270         // synopsys translate_off
2271         initial
2272                 dffe4a[4:4] = 0;
2273         // synopsys translate_on
2274         always @ ( posedge clock or  negedge prn or  negedge clrn)
2275                 if (prn == 1'b0) dffe4a[4:4] <= 1'b1;
2276                 else if (clrn == 1'b0) dffe4a[4:4] <= 1'b0;
2277                 else if  (ena == 1'b1)   dffe4a[4:4] <= wire_dffe4a_D[4:4];
2278         // synopsys translate_off
2279         initial
2280                 dffe4a[5:5] = 0;
2281         // synopsys translate_on
2282         always @ ( posedge clock or  negedge prn or  negedge clrn)
2283                 if (prn == 1'b0) dffe4a[5:5] <= 1'b1;
2284                 else if (clrn == 1'b0) dffe4a[5:5] <= 1'b0;
2285                 else if  (ena == 1'b1)   dffe4a[5:5] <= wire_dffe4a_D[5:5];
2286         // synopsys translate_off
2287         initial
2288                 dffe4a[6:6] = 0;
2289         // synopsys translate_on
2290         always @ ( posedge clock or  negedge prn or  negedge clrn)
2291                 if (prn == 1'b0) dffe4a[6:6] <= 1'b1;
2292                 else if (clrn == 1'b0) dffe4a[6:6] <= 1'b0;
2293                 else if  (ena == 1'b1)   dffe4a[6:6] <= wire_dffe4a_D[6:6];
2294         // synopsys translate_off
2295         initial
2296                 dffe4a[7:7] = 0;
2297         // synopsys translate_on
2298         always @ ( posedge clock or  negedge prn or  negedge clrn)
2299                 if (prn == 1'b0) dffe4a[7:7] <= 1'b1;
2300                 else if (clrn == 1'b0) dffe4a[7:7] <= 1'b0;
2301                 else if  (ena == 1'b1)   dffe4a[7:7] <= wire_dffe4a_D[7:7];
2302         // synopsys translate_off
2303         initial
2304                 dffe4a[8:8] = 0;
2305         // synopsys translate_on
2306         always @ ( posedge clock or  negedge prn or  negedge clrn)
2307                 if (prn == 1'b0) dffe4a[8:8] <= 1'b1;
2308                 else if (clrn == 1'b0) dffe4a[8:8] <= 1'b0;
2309                 else if  (ena == 1'b1)   dffe4a[8:8] <= wire_dffe4a_D[8:8];
2310         // synopsys translate_off
2311         initial
2312                 dffe4a[9:9] = 0;
2313         // synopsys translate_on
2314         always @ ( posedge clock or  negedge prn or  negedge clrn)
2315                 if (prn == 1'b0) dffe4a[9:9] <= 1'b1;
2316                 else if (clrn == 1'b0) dffe4a[9:9] <= 1'b0;
2317                 else if  (ena == 1'b1)   dffe4a[9:9] <= wire_dffe4a_D[9:9];
2318         // synopsys translate_off
2319         initial
2320                 dffe4a[10:10] = 0;
2321         // synopsys translate_on
2322         always @ ( posedge clock or  negedge prn or  negedge clrn)
2323                 if (prn == 1'b0) dffe4a[10:10] <= 1'b1;
2324                 else if (clrn == 1'b0) dffe4a[10:10] <= 1'b0;
2325                 else if  (ena == 1'b1)   dffe4a[10:10] <= wire_dffe4a_D[10:10];
2326         assign
2327                 wire_dffe4a_D = (d & {11{(~ sclr)}});
2328         assign
2329                 ena = 1'b1,
2330                 prn = 1'b1,
2331                 q = dffe4a,
2332                 sclr = 1'b0;
2333 endmodule //fifo_2k_dffpipe_ab3
2334
2335
2336 //dffpipe WIDTH=11 clock clrn d q
2337 //VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_altdpram 2004:11:30:11:29:56:SJ cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_dcfifo 2005:03:07:17:11:14:SJ cbx_fifo_common 2004:12:13:14:26:24:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_counter 2005:02:02:04:37:10:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_scfifo 2005:03:10:10:52:20:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ  VERSION_END
2338
2339
2340 //dffpipe WIDTH=11 clock clrn d q
2341 //VERSION_BEGIN 5.0 cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ  VERSION_END
2342
2343 //synthesis_resources = lut 11
2344 //synopsys translate_off
2345 `timescale 1 ps / 1 ps
2346 //synopsys translate_on
2347 module  fifo_2k_dffpipe_dm2
2348         (
2349         clock,
2350         clrn,
2351         d,
2352         q) /* synthesis synthesis_clearbox=1 */
2353                 /* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF" */;
2354         input   clock;
2355         input   clrn;
2356         input   [10:0]  d;
2357         output   [10:0]  q;
2358
2359         wire    [10:0]  wire_dffe6a_D;
2360         reg     [10:0]  dffe6a;
2361         wire ena;
2362         wire prn;
2363         wire sclr;
2364
2365         // synopsys translate_off
2366         initial
2367                 dffe6a[0:0] = 0;
2368         // synopsys translate_on
2369         always @ ( posedge clock or  negedge prn or  negedge clrn)
2370                 if (prn == 1'b0) dffe6a[0:0] <= 1'b1;
2371                 else if (clrn == 1'b0) dffe6a[0:0] <= 1'b0;
2372                 else if  (ena == 1'b1)   dffe6a[0:0] <= wire_dffe6a_D[0:0];
2373         // synopsys translate_off
2374         initial
2375                 dffe6a[1:1] = 0;
2376         // synopsys translate_on
2377         always @ ( posedge clock or  negedge prn or  negedge clrn)
2378                 if (prn == 1'b0) dffe6a[1:1] <= 1'b1;
2379                 else if (clrn == 1'b0) dffe6a[1:1] <= 1'b0;
2380                 else if  (ena == 1'b1)   dffe6a[1:1] <= wire_dffe6a_D[1:1];
2381         // synopsys translate_off
2382         initial
2383                 dffe6a[2:2] = 0;
2384         // synopsys translate_on
2385         always @ ( posedge clock or  negedge prn or  negedge clrn)
2386                 if (prn == 1'b0) dffe6a[2:2] <= 1'b1;
2387                 else if (clrn == 1'b0) dffe6a[2:2] <= 1'b0;
2388                 else if  (ena == 1'b1)   dffe6a[2:2] <= wire_dffe6a_D[2:2];
2389         // synopsys translate_off
2390         initial
2391                 dffe6a[3:3] = 0;
2392         // synopsys translate_on
2393         always @ ( posedge clock or  negedge prn or  negedge clrn)
2394                 if (prn == 1'b0) dffe6a[3:3] <= 1'b1;
2395                 else if (clrn == 1'b0) dffe6a[3:3] <= 1'b0;
2396                 else if  (ena == 1'b1)   dffe6a[3:3] <= wire_dffe6a_D[3:3];
2397         // synopsys translate_off
2398         initial
2399                 dffe6a[4:4] = 0;
2400         // synopsys translate_on
2401         always @ ( posedge clock or  negedge prn or  negedge clrn)
2402                 if (prn == 1'b0) dffe6a[4:4] <= 1'b1;
2403                 else if (clrn == 1'b0) dffe6a[4:4] <= 1'b0;
2404                 else if  (ena == 1'b1)   dffe6a[4:4] <= wire_dffe6a_D[4:4];
2405         // synopsys translate_off
2406         initial
2407                 dffe6a[5:5] = 0;
2408         // synopsys translate_on
2409         always @ ( posedge clock or  negedge prn or  negedge clrn)
2410                 if (prn == 1'b0) dffe6a[5:5] <= 1'b1;
2411                 else if (clrn == 1'b0) dffe6a[5:5] <= 1'b0;
2412                 else if  (ena == 1'b1)   dffe6a[5:5] <= wire_dffe6a_D[5:5];
2413         // synopsys translate_off
2414         initial
2415                 dffe6a[6:6] = 0;
2416         // synopsys translate_on
2417         always @ ( posedge clock or  negedge prn or  negedge clrn)
2418                 if (prn == 1'b0) dffe6a[6:6] <= 1'b1;
2419                 else if (clrn == 1'b0) dffe6a[6:6] <= 1'b0;
2420                 else if  (ena == 1'b1)   dffe6a[6:6] <= wire_dffe6a_D[6:6];
2421         // synopsys translate_off
2422         initial
2423                 dffe6a[7:7] = 0;
2424         // synopsys translate_on
2425         always @ ( posedge clock or  negedge prn or  negedge clrn)
2426                 if (prn == 1'b0) dffe6a[7:7] <= 1'b1;
2427                 else if (clrn == 1'b0) dffe6a[7:7] <= 1'b0;
2428                 else if  (ena == 1'b1)   dffe6a[7:7] <= wire_dffe6a_D[7:7];
2429         // synopsys translate_off
2430         initial
2431                 dffe6a[8:8] = 0;
2432         // synopsys translate_on
2433         always @ ( posedge clock or  negedge prn or  negedge clrn)
2434                 if (prn == 1'b0) dffe6a[8:8] <= 1'b1;
2435                 else if (clrn == 1'b0) dffe6a[8:8] <= 1'b0;
2436                 else if  (ena == 1'b1)   dffe6a[8:8] <= wire_dffe6a_D[8:8];
2437         // synopsys translate_off
2438         initial
2439                 dffe6a[9:9] = 0;
2440         // synopsys translate_on
2441         always @ ( posedge clock or  negedge prn or  negedge clrn)
2442                 if (prn == 1'b0) dffe6a[9:9] <= 1'b1;
2443                 else if (clrn == 1'b0) dffe6a[9:9] <= 1'b0;
2444                 else if  (ena == 1'b1)   dffe6a[9:9] <= wire_dffe6a_D[9:9];
2445         // synopsys translate_off
2446         initial
2447                 dffe6a[10:10] = 0;
2448         // synopsys translate_on
2449         always @ ( posedge clock or  negedge prn or  negedge clrn)
2450                 if (prn == 1'b0) dffe6a[10:10] <= 1'b1;
2451                 else if (clrn == 1'b0) dffe6a[10:10] <= 1'b0;
2452                 else if  (ena == 1'b1)   dffe6a[10:10] <= wire_dffe6a_D[10:10];
2453         assign
2454                 wire_dffe6a_D = (d & {11{(~ sclr)}});
2455         assign
2456                 ena = 1'b1,
2457                 prn = 1'b1,
2458                 q = dffe6a,
2459                 sclr = 1'b0;
2460 endmodule //fifo_2k_dffpipe_dm2
2461
2462 //synthesis_resources = lut 11
2463 //synopsys translate_off
2464 `timescale 1 ps / 1 ps
2465 //synopsys translate_on
2466 module  fifo_2k_alt_synch_pipe_dm2
2467         (
2468         clock,
2469         clrn,
2470         d,
2471         q) /* synthesis synthesis_clearbox=1 */
2472                 /* synthesis ALTERA_ATTRIBUTE="X_ON_VIOLATION_OPTION=OFF" */;
2473         input   clock;
2474         input   clrn;
2475         input   [10:0]  d;
2476         output   [10:0]  q;
2477
2478         wire  [10:0]   wire_dffpipe5_q;
2479
2480         fifo_2k_dffpipe_dm2   dffpipe5
2481         (
2482         .clock(clock),
2483         .clrn(clrn),
2484         .d(d),
2485         .q(wire_dffpipe5_q));
2486         assign
2487                 q = wire_dffpipe5_q;
2488 endmodule //fifo_2k_alt_synch_pipe_dm2
2489
2490
2491 //lpm_add_sub DEVICE_FAMILY="Cyclone" LPM_DIRECTION="SUB" LPM_WIDTH=11 dataa datab result
2492 //VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ  VERSION_END
2493
2494 //synthesis_resources = lut 11
2495 //synopsys translate_off
2496 `timescale 1 ps / 1 ps
2497 //synopsys translate_on
2498 module  fifo_2k_add_sub_a18
2499         (
2500         dataa,
2501         datab,
2502         result) /* synthesis synthesis_clearbox=1 */;
2503         input   [10:0]  dataa;
2504         input   [10:0]  datab;
2505         output   [10:0]  result;
2506
2507         wire  [10:0]   wire_add_sub_cella_combout;
2508         wire  [0:0]   wire_add_sub_cella_0cout;
2509         wire  [0:0]   wire_add_sub_cella_1cout;
2510         wire  [0:0]   wire_add_sub_cella_2cout;
2511         wire  [0:0]   wire_add_sub_cella_3cout;
2512         wire  [0:0]   wire_add_sub_cella_4cout;
2513         wire  [0:0]   wire_add_sub_cella_5cout;
2514         wire  [0:0]   wire_add_sub_cella_6cout;
2515         wire  [0:0]   wire_add_sub_cella_7cout;
2516         wire  [0:0]   wire_add_sub_cella_8cout;
2517         wire  [0:0]   wire_add_sub_cella_9cout;
2518         wire  [10:0]   wire_add_sub_cella_dataa;
2519         wire  [10:0]   wire_add_sub_cella_datab;
2520
2521         cyclone_lcell   add_sub_cella_0
2522         (
2523         .cin(1'b1),
2524         .combout(wire_add_sub_cella_combout[0:0]),
2525         .cout(wire_add_sub_cella_0cout[0:0]),
2526         .dataa(wire_add_sub_cella_dataa[0:0]),
2527         .datab(wire_add_sub_cella_datab[0:0]),
2528         .regout()
2529         `ifdef FORMAL_VERIFICATION
2530         `else
2531         // synopsys translate_off
2532         `endif
2533         ,
2534         .aclr(1'b0),
2535         .aload(1'b0),
2536         .clk(1'b1),
2537         .datac(1'b1),
2538         .datad(1'b1),
2539         .ena(1'b1),
2540         .inverta(1'b0),
2541         .regcascin(1'b0),
2542         .sclr(1'b0),
2543         .sload(1'b0)
2544         `ifdef FORMAL_VERIFICATION
2545         `else
2546         // synopsys translate_on
2547         `endif
2548         // synopsys translate_off
2549         ,
2550         .cin0(),
2551         .cin1(),
2552         .cout0(),
2553         .cout1(),
2554         .devclrn(),
2555         .devpor()
2556         // synopsys translate_on
2557         );
2558         defparam
2559                 add_sub_cella_0.cin_used = "true",
2560                 add_sub_cella_0.lut_mask = "69b2",
2561                 add_sub_cella_0.operation_mode = "arithmetic",
2562                 add_sub_cella_0.sum_lutc_input = "cin",
2563                 add_sub_cella_0.lpm_type = "cyclone_lcell";
2564         cyclone_lcell   add_sub_cella_1
2565         (
2566         .cin(wire_add_sub_cella_0cout[0:0]),
2567         .combout(wire_add_sub_cella_combout[1:1]),
2568         .cout(wire_add_sub_cella_1cout[0:0]),
2569         .dataa(wire_add_sub_cella_dataa[1:1]),
2570         .datab(wire_add_sub_cella_datab[1:1]),
2571         .regout()
2572         `ifdef FORMAL_VERIFICATION
2573         `else
2574         // synopsys translate_off
2575         `endif
2576         ,
2577         .aclr(1'b0),
2578         .aload(1'b0),
2579         .clk(1'b1),
2580         .datac(1'b1),
2581         .datad(1'b1),
2582         .ena(1'b1),
2583         .inverta(1'b0),
2584         .regcascin(1'b0),
2585         .sclr(1'b0),
2586         .sload(1'b0)
2587         `ifdef FORMAL_VERIFICATION
2588         `else
2589         // synopsys translate_on
2590         `endif
2591         // synopsys translate_off
2592         ,
2593         .cin0(),
2594         .cin1(),
2595         .cout0(),
2596         .cout1(),
2597         .devclrn(),
2598         .devpor()
2599         // synopsys translate_on
2600         );
2601         defparam
2602                 add_sub_cella_1.cin_used = "true",
2603                 add_sub_cella_1.lut_mask = "69b2",
2604                 add_sub_cella_1.operation_mode = "arithmetic",
2605                 add_sub_cella_1.sum_lutc_input = "cin",
2606                 add_sub_cella_1.lpm_type = "cyclone_lcell";
2607         cyclone_lcell   add_sub_cella_2
2608         (
2609         .cin(wire_add_sub_cella_1cout[0:0]),
2610         .combout(wire_add_sub_cella_combout[2:2]),
2611         .cout(wire_add_sub_cella_2cout[0:0]),
2612         .dataa(wire_add_sub_cella_dataa[2:2]),
2613         .datab(wire_add_sub_cella_datab[2:2]),
2614         .regout()
2615         `ifdef FORMAL_VERIFICATION
2616         `else
2617         // synopsys translate_off
2618         `endif
2619         ,
2620         .aclr(1'b0),
2621         .aload(1'b0),
2622         .clk(1'b1),
2623         .datac(1'b1),
2624         .datad(1'b1),
2625         .ena(1'b1),
2626         .inverta(1'b0),
2627         .regcascin(1'b0),
2628         .sclr(1'b0),
2629         .sload(1'b0)
2630         `ifdef FORMAL_VERIFICATION
2631         `else
2632         // synopsys translate_on
2633         `endif
2634         // synopsys translate_off
2635         ,
2636         .cin0(),
2637         .cin1(),
2638         .cout0(),
2639         .cout1(),
2640         .devclrn(),
2641         .devpor()
2642         // synopsys translate_on
2643         );
2644         defparam
2645                 add_sub_cella_2.cin_used = "true",
2646                 add_sub_cella_2.lut_mask = "69b2",
2647                 add_sub_cella_2.operation_mode = "arithmetic",
2648                 add_sub_cella_2.sum_lutc_input = "cin",
2649                 add_sub_cella_2.lpm_type = "cyclone_lcell";
2650         cyclone_lcell   add_sub_cella_3
2651         (
2652         .cin(wire_add_sub_cella_2cout[0:0]),
2653         .combout(wire_add_sub_cella_combout[3:3]),
2654         .cout(wire_add_sub_cella_3cout[0:0]),
2655         .dataa(wire_add_sub_cella_dataa[3:3]),
2656         .datab(wire_add_sub_cella_datab[3:3]),
2657         .regout()
2658         `ifdef FORMAL_VERIFICATION
2659         `else
2660         // synopsys translate_off
2661         `endif
2662         ,
2663         .aclr(1'b0),
2664         .aload(1'b0),
2665         .clk(1'b1),
2666         .datac(1'b1),
2667         .datad(1'b1),
2668         .ena(1'b1),
2669         .inverta(1'b0),
2670         .regcascin(1'b0),
2671         .sclr(1'b0),
2672         .sload(1'b0)
2673         `ifdef FORMAL_VERIFICATION
2674         `else
2675         // synopsys translate_on
2676         `endif
2677         // synopsys translate_off
2678         ,
2679         .cin0(),
2680         .cin1(),
2681         .cout0(),
2682         .cout1(),
2683         .devclrn(),
2684         .devpor()
2685         // synopsys translate_on
2686         );
2687         defparam
2688                 add_sub_cella_3.cin_used = "true",
2689                 add_sub_cella_3.lut_mask = "69b2",
2690                 add_sub_cella_3.operation_mode = "arithmetic",
2691                 add_sub_cella_3.sum_lutc_input = "cin",
2692                 add_sub_cella_3.lpm_type = "cyclone_lcell";
2693         cyclone_lcell   add_sub_cella_4
2694         (
2695         .cin(wire_add_sub_cella_3cout[0:0]),
2696         .combout(wire_add_sub_cella_combout[4:4]),
2697         .cout(wire_add_sub_cella_4cout[0:0]),
2698         .dataa(wire_add_sub_cella_dataa[4:4]),
2699         .datab(wire_add_sub_cella_datab[4:4]),
2700         .regout()
2701         `ifdef FORMAL_VERIFICATION
2702         `else
2703         // synopsys translate_off
2704         `endif
2705         ,
2706         .aclr(1'b0),
2707         .aload(1'b0),
2708         .clk(1'b1),
2709         .datac(1'b1),
2710         .datad(1'b1),
2711         .ena(1'b1),
2712         .inverta(1'b0),
2713         .regcascin(1'b0),
2714         .sclr(1'b0),
2715         .sload(1'b0)
2716         `ifdef FORMAL_VERIFICATION
2717         `else
2718         // synopsys translate_on
2719         `endif
2720         // synopsys translate_off
2721         ,
2722         .cin0(),
2723         .cin1(),
2724         .cout0(),
2725         .cout1(),
2726         .devclrn(),
2727         .devpor()
2728         // synopsys translate_on
2729         );
2730         defparam
2731                 add_sub_cella_4.cin_used = "true",
2732                 add_sub_cella_4.lut_mask = "69b2",
2733                 add_sub_cella_4.operation_mode = "arithmetic",
2734                 add_sub_cella_4.sum_lutc_input = "cin",
2735                 add_sub_cella_4.lpm_type = "cyclone_lcell";
2736         cyclone_lcell   add_sub_cella_5
2737         (
2738         .cin(wire_add_sub_cella_4cout[0:0]),
2739         .combout(wire_add_sub_cella_combout[5:5]),
2740         .cout(wire_add_sub_cella_5cout[0:0]),
2741         .dataa(wire_add_sub_cella_dataa[5:5]),
2742         .datab(wire_add_sub_cella_datab[5:5]),
2743         .regout()
2744         `ifdef FORMAL_VERIFICATION
2745         `else
2746         // synopsys translate_off
2747         `endif
2748         ,
2749         .aclr(1'b0),
2750         .aload(1'b0),
2751         .clk(1'b1),
2752         .datac(1'b1),
2753         .datad(1'b1),
2754         .ena(1'b1),
2755         .inverta(1'b0),
2756         .regcascin(1'b0),
2757         .sclr(1'b0),
2758         .sload(1'b0)
2759         `ifdef FORMAL_VERIFICATION
2760         `else
2761         // synopsys translate_on
2762         `endif
2763         // synopsys translate_off
2764         ,
2765         .cin0(),
2766         .cin1(),
2767         .cout0(),
2768         .cout1(),
2769         .devclrn(),
2770         .devpor()
2771         // synopsys translate_on
2772         );
2773         defparam
2774                 add_sub_cella_5.cin_used = "true",
2775                 add_sub_cella_5.lut_mask = "69b2",
2776                 add_sub_cella_5.operation_mode = "arithmetic",
2777                 add_sub_cella_5.sum_lutc_input = "cin",
2778                 add_sub_cella_5.lpm_type = "cyclone_lcell";
2779         cyclone_lcell   add_sub_cella_6
2780         (
2781         .cin(wire_add_sub_cella_5cout[0:0]),
2782         .combout(wire_add_sub_cella_combout[6:6]),
2783         .cout(wire_add_sub_cella_6cout[0:0]),
2784         .dataa(wire_add_sub_cella_dataa[6:6]),
2785         .datab(wire_add_sub_cella_datab[6:6]),
2786         .regout()
2787         `ifdef FORMAL_VERIFICATION
2788         `else
2789         // synopsys translate_off
2790         `endif
2791         ,
2792         .aclr(1'b0),
2793         .aload(1'b0),
2794         .clk(1'b1),
2795         .datac(1'b1),
2796         .datad(1'b1),
2797         .ena(1'b1),
2798         .inverta(1'b0),
2799         .regcascin(1'b0),
2800         .sclr(1'b0),
2801         .sload(1'b0)
2802         `ifdef FORMAL_VERIFICATION
2803         `else
2804         // synopsys translate_on
2805         `endif
2806         // synopsys translate_off
2807         ,
2808         .cin0(),
2809         .cin1(),
2810         .cout0(),
2811         .cout1(),
2812         .devclrn(),
2813         .devpor()
2814         // synopsys translate_on
2815         );
2816         defparam
2817                 add_sub_cella_6.cin_used = "true",
2818                 add_sub_cella_6.lut_mask = "69b2",
2819                 add_sub_cella_6.operation_mode = "arithmetic",
2820                 add_sub_cella_6.sum_lutc_input = "cin",
2821                 add_sub_cella_6.lpm_type = "cyclone_lcell";
2822         cyclone_lcell   add_sub_cella_7
2823         (
2824         .cin(wire_add_sub_cella_6cout[0:0]),
2825         .combout(wire_add_sub_cella_combout[7:7]),
2826         .cout(wire_add_sub_cella_7cout[0:0]),
2827         .dataa(wire_add_sub_cella_dataa[7:7]),
2828         .datab(wire_add_sub_cella_datab[7:7]),
2829         .regout()
2830         `ifdef FORMAL_VERIFICATION
2831         `else
2832         // synopsys translate_off
2833         `endif
2834         ,
2835         .aclr(1'b0),
2836         .aload(1'b0),
2837         .clk(1'b1),
2838         .datac(1'b1),
2839         .datad(1'b1),
2840         .ena(1'b1),
2841         .inverta(1'b0),
2842         .regcascin(1'b0),
2843         .sclr(1'b0),
2844         .sload(1'b0)
2845         `ifdef FORMAL_VERIFICATION
2846         `else
2847         // synopsys translate_on
2848         `endif
2849         // synopsys translate_off
2850         ,
2851         .cin0(),
2852         .cin1(),
2853         .cout0(),
2854         .cout1(),
2855         .devclrn(),
2856         .devpor()
2857         // synopsys translate_on
2858         );
2859         defparam
2860                 add_sub_cella_7.cin_used = "true",
2861                 add_sub_cella_7.lut_mask = "69b2",
2862                 add_sub_cella_7.operation_mode = "arithmetic",
2863                 add_sub_cella_7.sum_lutc_input = "cin",
2864                 add_sub_cella_7.lpm_type = "cyclone_lcell";
2865         cyclone_lcell   add_sub_cella_8
2866         (
2867         .cin(wire_add_sub_cella_7cout[0:0]),
2868         .combout(wire_add_sub_cella_combout[8:8]),
2869         .cout(wire_add_sub_cella_8cout[0:0]),
2870         .dataa(wire_add_sub_cella_dataa[8:8]),
2871         .datab(wire_add_sub_cella_datab[8:8]),
2872         .regout()
2873         `ifdef FORMAL_VERIFICATION
2874         `else
2875         // synopsys translate_off
2876         `endif
2877         ,
2878         .aclr(1'b0),
2879         .aload(1'b0),
2880         .clk(1'b1),
2881         .datac(1'b1),
2882         .datad(1'b1),
2883         .ena(1'b1),
2884         .inverta(1'b0),
2885         .regcascin(1'b0),
2886         .sclr(1'b0),
2887         .sload(1'b0)
2888         `ifdef FORMAL_VERIFICATION
2889         `else
2890         // synopsys translate_on
2891         `endif
2892         // synopsys translate_off
2893         ,
2894         .cin0(),
2895         .cin1(),
2896         .cout0(),
2897         .cout1(),
2898         .devclrn(),
2899         .devpor()
2900         // synopsys translate_on
2901         );
2902         defparam
2903                 add_sub_cella_8.cin_used = "true",
2904                 add_sub_cella_8.lut_mask = "69b2",
2905                 add_sub_cella_8.operation_mode = "arithmetic",
2906                 add_sub_cella_8.sum_lutc_input = "cin",
2907                 add_sub_cella_8.lpm_type = "cyclone_lcell";
2908         cyclone_lcell   add_sub_cella_9
2909         (
2910         .cin(wire_add_sub_cella_8cout[0:0]),
2911         .combout(wire_add_sub_cella_combout[9:9]),
2912         .cout(wire_add_sub_cella_9cout[0:0]),
2913         .dataa(wire_add_sub_cella_dataa[9:9]),
2914         .datab(wire_add_sub_cella_datab[9:9]),
2915         .regout()
2916         `ifdef FORMAL_VERIFICATION
2917         `else
2918         // synopsys translate_off
2919         `endif
2920         ,
2921         .aclr(1'b0),
2922         .aload(1'b0),
2923         .clk(1'b1),
2924         .datac(1'b1),
2925         .datad(1'b1),
2926         .ena(1'b1),
2927         .inverta(1'b0),
2928         .regcascin(1'b0),
2929         .sclr(1'b0),
2930         .sload(1'b0)
2931         `ifdef FORMAL_VERIFICATION
2932         `else
2933         // synopsys translate_on
2934         `endif
2935         // synopsys translate_off
2936         ,
2937         .cin0(),
2938         .cin1(),
2939         .cout0(),
2940         .cout1(),
2941         .devclrn(),
2942         .devpor()
2943         // synopsys translate_on
2944         );
2945         defparam
2946                 add_sub_cella_9.cin_used = "true",
2947                 add_sub_cella_9.lut_mask = "69b2",
2948                 add_sub_cella_9.operation_mode = "arithmetic",
2949                 add_sub_cella_9.sum_lutc_input = "cin",
2950                 add_sub_cella_9.lpm_type = "cyclone_lcell";
2951         cyclone_lcell   add_sub_cella_10
2952         (
2953         .cin(wire_add_sub_cella_9cout[0:0]),
2954         .combout(wire_add_sub_cella_combout[10:10]),
2955         .cout(),
2956         .dataa(wire_add_sub_cella_dataa[10:10]),
2957         .datab(wire_add_sub_cella_datab[10:10]),
2958         .regout()
2959         `ifdef FORMAL_VERIFICATION
2960         `else
2961         // synopsys translate_off
2962         `endif
2963         ,
2964         .aclr(1'b0),
2965         .aload(1'b0),
2966         .clk(1'b1),
2967         .datac(1'b1),
2968         .datad(1'b1),
2969         .ena(1'b1),
2970         .inverta(1'b0),
2971         .regcascin(1'b0),
2972         .sclr(1'b0),
2973         .sload(1'b0)
2974         `ifdef FORMAL_VERIFICATION
2975         `else
2976         // synopsys translate_on
2977         `endif
2978         // synopsys translate_off
2979         ,
2980         .cin0(),
2981         .cin1(),
2982         .cout0(),
2983         .cout1(),
2984         .devclrn(),
2985         .devpor()
2986         // synopsys translate_on
2987         );
2988         defparam
2989                 add_sub_cella_10.cin_used = "true",
2990                 add_sub_cella_10.lut_mask = "6969",
2991                 add_sub_cella_10.operation_mode = "normal",
2992                 add_sub_cella_10.sum_lutc_input = "cin",
2993                 add_sub_cella_10.lpm_type = "cyclone_lcell";
2994         assign
2995                 wire_add_sub_cella_dataa = dataa,
2996                 wire_add_sub_cella_datab = datab;
2997         assign
2998                 result = wire_add_sub_cella_combout;
2999 endmodule //fifo_2k_add_sub_a18
3000
3001
3002 //lpm_compare DEVICE_FAMILY="Cyclone" LPM_WIDTH=11 aeb dataa datab
3003 //VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ  VERSION_END
3004
3005
3006 //lpm_compare DEVICE_FAMILY="Cyclone" LPM_WIDTH=11 aeb dataa datab
3007 //VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ  VERSION_END
3008
3009 //synthesis_resources = lut 97 M4K 8
3010 //synopsys translate_off
3011 `timescale 1 ps / 1 ps
3012 //synopsys translate_on
3013 module  fifo_2k_dcfifo_0cq
3014         (
3015         aclr,
3016         data,
3017         q,
3018         rdclk,
3019         rdempty,
3020         rdreq,
3021         rdusedw,
3022         wrclk,
3023         wrfull,
3024         wrreq,
3025         wrusedw) /* synthesis synthesis_clearbox=1 */
3026                 /* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF;{ -from \"rdptr_g|power_modified_counter_values\" -to \"ws_dgrp|dffpipe5|dffe6a\" }CUT=ON;{ -from \"delayed_wrptr_g\" -to \"rs_dgwp|dffpipe5|dffe6a\" }CUT=ON" */;
3027         input   aclr;
3028         input   [15:0]  data;
3029         output   [15:0]  q;
3030         input   rdclk;
3031         output   rdempty;
3032         input   rdreq;
3033         output   [10:0]  rdusedw;
3034         input   wrclk;
3035         output   wrfull;
3036         input   wrreq;
3037         output   [10:0]  wrusedw;
3038
3039         wire  [10:0]   wire_rdptr_g_gray2bin_bin;
3040         wire  [10:0]   wire_rs_dgwp_gray2bin_bin;
3041         wire  [10:0]   wire_wrptr_g_gray2bin_bin;
3042         wire  [10:0]   wire_ws_dgrp_gray2bin_bin;
3043         wire  [10:0]   wire_rdptr_g_q;
3044         wire  [10:0]   wire_rdptr_g1p_q;
3045         wire  [10:0]   wire_wrptr_g1p_q;
3046         wire  [15:0]   wire_fifo_ram_q_b;
3047         reg     [10:0]  delayed_wrptr_g;
3048         reg     [10:0]  wrptr_g;
3049         wire  [10:0]   wire_rs_brp_q;
3050         wire  [10:0]   wire_rs_bwp_q;
3051         wire  [10:0]   wire_rs_dgwp_q;
3052         wire  [10:0]   wire_ws_brp_q;
3053         wire  [10:0]   wire_ws_bwp_q;
3054         wire  [10:0]   wire_ws_dgrp_q;
3055         wire  [10:0]   wire_rdusedw_sub_result;
3056         wire  [10:0]   wire_wrusedw_sub_result;
3057         reg     wire_rdempty_eq_comp_aeb_int;
3058         wire    wire_rdempty_eq_comp_aeb;
3059         wire    [10:0]  wire_rdempty_eq_comp_dataa;
3060         wire    [10:0]  wire_rdempty_eq_comp_datab;
3061         reg     wire_wrfull_eq_comp_aeb_int;
3062         wire    wire_wrfull_eq_comp_aeb;
3063         wire    [10:0]  wire_wrfull_eq_comp_dataa;
3064         wire    [10:0]  wire_wrfull_eq_comp_datab;
3065         wire  int_rdempty;
3066         wire  int_wrfull;
3067         wire  valid_rdreq;
3068         wire  valid_wrreq;
3069
3070         fifo_2k_a_gray2bin_8m4   rdptr_g_gray2bin
3071         (
3072         .bin(wire_rdptr_g_gray2bin_bin),
3073         .gray(wire_rdptr_g_q));
3074         fifo_2k_a_gray2bin_8m4   rs_dgwp_gray2bin
3075         (
3076         .bin(wire_rs_dgwp_gray2bin_bin),
3077         .gray(wire_rs_dgwp_q));
3078         fifo_2k_a_gray2bin_8m4   wrptr_g_gray2bin
3079         (
3080         .bin(wire_wrptr_g_gray2bin_bin),
3081         .gray(wrptr_g));
3082         fifo_2k_a_gray2bin_8m4   ws_dgrp_gray2bin
3083         (
3084         .bin(wire_ws_dgrp_gray2bin_bin),
3085         .gray(wire_ws_dgrp_q));
3086         fifo_2k_a_graycounter_726   rdptr_g
3087         (
3088         .aclr(aclr),
3089         .clock(rdclk),
3090         .cnt_en(valid_rdreq),
3091         .q(wire_rdptr_g_q));
3092         fifo_2k_a_graycounter_2r6   rdptr_g1p
3093         (
3094         .aclr(aclr),
3095         .clock(rdclk),
3096         .cnt_en(valid_rdreq),
3097         .q(wire_rdptr_g1p_q));
3098         fifo_2k_a_graycounter_2r6   wrptr_g1p
3099         (
3100         .aclr(aclr),
3101         .clock(wrclk),
3102         .cnt_en(valid_wrreq),
3103         .q(wire_wrptr_g1p_q));
3104         fifo_2k_altsyncram_6pl   fifo_ram
3105         (
3106         .address_a(wrptr_g),
3107         .address_b(((wire_rdptr_g_q & {11{int_rdempty}}) | (wire_rdptr_g1p_q & {11{(~ int_rdempty)}}))),
3108         .clock0(wrclk),
3109         .clock1(rdclk),
3110         .clocken1((valid_rdreq | int_rdempty)),
3111         .data_a(data),
3112         .q_b(wire_fifo_ram_q_b),
3113         .wren_a(valid_wrreq));
3114         // synopsys translate_off
3115         initial
3116                 delayed_wrptr_g = 0;
3117         // synopsys translate_on
3118         always @ ( posedge wrclk or  posedge aclr)
3119                 if (aclr == 1'b1) delayed_wrptr_g <= 11'b0;
3120                 else  delayed_wrptr_g <= wrptr_g;
3121         // synopsys translate_off
3122         initial
3123                 wrptr_g = 0;
3124         // synopsys translate_on
3125         always @ ( posedge wrclk or  posedge aclr)
3126                 if (aclr == 1'b1) wrptr_g <= 11'b0;
3127                 else if  (valid_wrreq == 1'b1)   wrptr_g <= wire_wrptr_g1p_q;
3128         fifo_2k_dffpipe_ab3   rs_brp
3129         (
3130         .clock(rdclk),
3131         .clrn((~ aclr)),
3132         .d(wire_rdptr_g_gray2bin_bin),
3133         .q(wire_rs_brp_q));
3134         fifo_2k_dffpipe_ab3   rs_bwp
3135         (
3136         .clock(rdclk),
3137         .clrn((~ aclr)),
3138         .d(wire_rs_dgwp_gray2bin_bin),
3139         .q(wire_rs_bwp_q));
3140         fifo_2k_alt_synch_pipe_dm2   rs_dgwp
3141         (
3142         .clock(rdclk),
3143         .clrn((~ aclr)),
3144         .d(delayed_wrptr_g),
3145         .q(wire_rs_dgwp_q));
3146         fifo_2k_dffpipe_ab3   ws_brp
3147         (
3148         .clock(wrclk),
3149         .clrn((~ aclr)),
3150         .d(wire_ws_dgrp_gray2bin_bin),
3151         .q(wire_ws_brp_q));
3152         fifo_2k_dffpipe_ab3   ws_bwp
3153         (
3154         .clock(wrclk),
3155         .clrn((~ aclr)),
3156         .d(wire_wrptr_g_gray2bin_bin),
3157         .q(wire_ws_bwp_q));
3158         fifo_2k_alt_synch_pipe_dm2   ws_dgrp
3159         (
3160         .clock(wrclk),
3161         .clrn((~ aclr)),
3162         .d(wire_rdptr_g_q),
3163         .q(wire_ws_dgrp_q));
3164         fifo_2k_add_sub_a18   rdusedw_sub
3165         (
3166         .dataa(wire_rs_bwp_q),
3167         .datab(wire_rs_brp_q),
3168         .result(wire_rdusedw_sub_result));
3169         fifo_2k_add_sub_a18   wrusedw_sub
3170         (
3171         .dataa(wire_ws_bwp_q),
3172         .datab(wire_ws_brp_q),
3173         .result(wire_wrusedw_sub_result));
3174         always @(wire_rdempty_eq_comp_dataa or wire_rdempty_eq_comp_datab)
3175                 if (wire_rdempty_eq_comp_dataa == wire_rdempty_eq_comp_datab)
3176                         begin
3177                                 wire_rdempty_eq_comp_aeb_int = 1'b1;
3178                         end
3179                 else
3180                         begin
3181                                 wire_rdempty_eq_comp_aeb_int = 1'b0;
3182                         end
3183         assign
3184                 wire_rdempty_eq_comp_aeb = wire_rdempty_eq_comp_aeb_int;
3185         assign
3186                 wire_rdempty_eq_comp_dataa = wire_rs_dgwp_q,
3187                 wire_rdempty_eq_comp_datab = wire_rdptr_g_q;
3188         always @(wire_wrfull_eq_comp_dataa or wire_wrfull_eq_comp_datab)
3189                 if (wire_wrfull_eq_comp_dataa == wire_wrfull_eq_comp_datab)
3190                         begin
3191                                 wire_wrfull_eq_comp_aeb_int = 1'b1;
3192                         end
3193                 else
3194                         begin
3195                                 wire_wrfull_eq_comp_aeb_int = 1'b0;
3196                         end
3197         assign
3198                 wire_wrfull_eq_comp_aeb = wire_wrfull_eq_comp_aeb_int;
3199         assign
3200                 wire_wrfull_eq_comp_dataa = wire_ws_dgrp_q,
3201                 wire_wrfull_eq_comp_datab = wire_wrptr_g1p_q;
3202         assign
3203                 int_rdempty = wire_rdempty_eq_comp_aeb,
3204                 int_wrfull = wire_wrfull_eq_comp_aeb,
3205                 q = wire_fifo_ram_q_b,
3206                 rdempty = int_rdempty,
3207                 rdusedw = wire_rdusedw_sub_result,
3208                 valid_rdreq = rdreq,
3209                 valid_wrreq = wrreq,
3210                 wrfull = int_wrfull,
3211                 wrusedw = wire_wrusedw_sub_result;
3212 endmodule //fifo_2k_dcfifo_0cq
3213 //VALID FILE
3214
3215
3216 // synopsys translate_off
3217 `timescale 1 ps / 1 ps
3218 // synopsys translate_on
3219 module fifo_2k (
3220         data,
3221         wrreq,
3222         rdreq,
3223         rdclk,
3224         wrclk,
3225         aclr,
3226         q,
3227         rdempty,
3228         rdusedw,
3229         wrfull,
3230         wrusedw)/* synthesis synthesis_clearbox = 1 */;
3231
3232         input   [15:0]  data;
3233         input     wrreq;
3234         input     rdreq;
3235         input     rdclk;
3236         input     wrclk;
3237         input     aclr;
3238         output  [15:0]  q;
3239         output    rdempty;
3240         output  [10:0]  rdusedw;
3241         output    wrfull;
3242         output  [10:0]  wrusedw;
3243
3244         wire  sub_wire0;
3245         wire [10:0] sub_wire1;
3246         wire  sub_wire2;
3247         wire [15:0] sub_wire3;
3248         wire [10:0] sub_wire4;
3249         wire  rdempty = sub_wire0;
3250         wire [10:0] wrusedw = sub_wire1[10:0];
3251         wire  wrfull = sub_wire2;
3252         wire [15:0] q = sub_wire3[15:0];
3253         wire [10:0] rdusedw = sub_wire4[10:0];
3254
3255         fifo_2k_dcfifo_0cq      fifo_2k_dcfifo_0cq_component (
3256                                 .wrclk (wrclk),
3257                                 .rdreq (rdreq),
3258                                 .aclr (aclr),
3259                                 .rdclk (rdclk),
3260                                 .wrreq (wrreq),
3261                                 .data (data),
3262                                 .rdempty (sub_wire0),
3263                                 .wrusedw (sub_wire1),
3264                                 .wrfull (sub_wire2),
3265                                 .q (sub_wire3),
3266                                 .rdusedw (sub_wire4));
3267
3268 endmodule
3269
3270 // ============================================================
3271 // CNX file retrieval info
3272 // ============================================================
3273 // Retrieval info: PRIVATE: Width NUMERIC "16"
3274 // Retrieval info: PRIVATE: Depth NUMERIC "2048"
3275 // Retrieval info: PRIVATE: Clock NUMERIC "4"
3276 // Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
3277 // Retrieval info: PRIVATE: Full NUMERIC "1"
3278 // Retrieval info: PRIVATE: Empty NUMERIC "1"
3279 // Retrieval info: PRIVATE: UsedW NUMERIC "1"
3280 // Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
3281 // Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
3282 // Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
3283 // Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
3284 // Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
3285 // Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
3286 // Retrieval info: PRIVATE: rsFull NUMERIC "0"
3287 // Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
3288 // Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
3289 // Retrieval info: PRIVATE: wsFull NUMERIC "1"
3290 // Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
3291 // Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
3292 // Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
3293 // Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
3294 // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
3295 // Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
3296 // Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
3297 // Retrieval info: PRIVATE: Optimize NUMERIC "2"
3298 // Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
3299 // Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
3300 // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
3301 // Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
3302 // Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "2048"
3303 // Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "11"
3304 // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
3305 // Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"
3306 // Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
3307 // Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
3308 // Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
3309 // Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
3310 // Retrieval info: CONSTANT: USE_EAB STRING "ON"
3311 // Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
3312 // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
3313 // Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
3314 // Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
3315 // Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
3316 // Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
3317 // Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
3318 // Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
3319 // Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
3320 // Retrieval info: USED_PORT: rdusedw 0 0 11 0 OUTPUT NODEFVAL rdusedw[10..0]
3321 // Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
3322 // Retrieval info: USED_PORT: wrusedw 0 0 11 0 OUTPUT NODEFVAL wrusedw[10..0]
3323 // Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
3324 // Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
3325 // Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
3326 // Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
3327 // Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
3328 // Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
3329 // Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
3330 // Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
3331 // Retrieval info: CONNECT: rdusedw 0 0 11 0 @rdusedw 0 0 11 0
3332 // Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
3333 // Retrieval info: CONNECT: wrusedw 0 0 11 0 @wrusedw 0 0 11 0
3334 // Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
3335 // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
3336 // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.v TRUE
3337 // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.inc FALSE
3338 // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.cmp FALSE
3339 // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k.bsf FALSE
3340 // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_inst.v FALSE
3341 // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_bb.v TRUE
3342 // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_waveforms.html TRUE
3343 // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_wave*.jpg FALSE