1 --Copyright (C) 1991-2006 Altera Corporation
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2 --Your use of Altera Corporation's design tools, logic functions
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3 --and other software and tools, and its AMPP partner logic
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4 --functions, and any output files any of the foregoing
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5 --(including device programming or simulation files), and any
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6 --associated documentation or information are expressly subject
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7 --to the terms and conditions of the Altera Program License
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8 --Subscription Agreement, Altera MegaCore Function License
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9 --Agreement, or other applicable license agreement, including,
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10 --without limitation, that your use is for the sole purpose of
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11 --programming logic devices manufactured by Altera and sold by
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12 --Altera or its authorized distributors. Please refer to the
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13 --applicable agreement for further details.
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16 component fifo_1kx16
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19 aclr : IN STD_LOGIC ;
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20 clock : IN STD_LOGIC ;
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21 data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
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22 rdreq : IN STD_LOGIC ;
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23 wrreq : IN STD_LOGIC ;
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24 almost_empty : OUT STD_LOGIC ;
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25 empty : OUT STD_LOGIC ;
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26 full : OUT STD_LOGIC ;
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27 q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
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28 usedw : OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
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projects / debian / gnuradio / blob