git.gag.com Git - debian/gnuradio/blob - usrp/fpga/inband_lib/usb_packet_fifo.v

   1 module usb_packet_fifo
   2   ( input       reset,
   3     input       clock_in,
   4     input       clock_out,
   5     input       [15:0]ram_data_in,
   6     input       write_enable,
   7     output  reg [15:0]ram_data_out,
   8     output  reg pkt_waiting,
   9     output  reg have_space,
  10     input       read_enable,
  11     input       skip_packet          ) ;
  12
  13     /* Some parameters for usage later on */
  14     parameter DATA_WIDTH = 16 ;
  15     parameter NUM_PACKETS = 4 ;
  16
  17     /* Create the RAM here */
  18     reg [DATA_WIDTH-1:0] usb_ram [256*NUM_PACKETS-1:0] ;
  19
  20     /* Create the address signals */
  21     reg [7-2+NUM_PACKETS:0] usb_ram_ain ;
  22     reg [7:0] usb_ram_offset ;
  23     reg [1:0] usb_ram_packet ;
  24
  25     wire [7-2+NUM_PACKETS:0] usb_ram_aout ;
  26     reg isfull;
  27
  28     assign usb_ram_aout = {usb_ram_packet,usb_ram_offset} ;
  29
  30     // Check if there is one full packet to process
  31     always @(usb_ram_ain, usb_ram_aout)
  32     begin
  33         if (reset)
  34             pkt_waiting <= 0;
  35         else if (usb_ram_ain == usb_ram_aout)
  36             pkt_waiting <= isfull;
  37         else if (usb_ram_ain > usb_ram_aout)
  38             pkt_waiting <= (usb_ram_ain - usb_ram_aout) >= 256;
  39         else
  40             pkt_waiting <= (usb_ram_ain + 10'b1111111111 - usb_ram_aout) >= 256;
  41     end
  42
  43     // Check if there is room
  44     always @(usb_ram_ain, usb_ram_aout)
  45     begin
  46         if (reset)
  47             have_space <= 1;
  48         else if (usb_ram_ain == usb_ram_aout)
  49             have_space <= ~isfull;
  50         else if (usb_ram_ain > usb_ram_aout)
  51             have_space <= (usb_ram_ain - usb_ram_aout) <= 256 * (NUM_PACKETS - 1);
  52         else
  53             have_space <= (usb_ram_aout - usb_ram_ain) >= 256;
  54     end
  55
  56     /* RAM Write Address process */
  57     always @(posedge clock_in)
  58     begin
  59         if( reset )
  60             usb_ram_ain <= 0 ;
  61         else
  62             if( write_enable )
  63               begin
  64                 usb_ram_ain <= usb_ram_ain + 1 ;
  65                 if (usb_ram_ain + 1 == usb_ram_aout)
  66                    isfull <= 1;
  67               end
  68     end
  69
  70     /* RAM Writing process */
  71     always @(posedge clock_in)
  72     begin
  73         if( write_enable )
  74           begin
  75             usb_ram[usb_ram_ain] <= ram_data_in ;
  76           end
  77     end
  78
  79     /* RAM Read Address process */
  80     always @(posedge clock_out)
  81     begin
  82         if( reset )
  83           begin
  84             usb_ram_packet <= 0 ;
  85             usb_ram_offset <= 0 ;
  86             isfull <= 0;
  87           end
  88         else
  89             if( skip_packet )
  90               begin
  91                 usb_ram_packet <= usb_ram_packet + 1 ;
  92                 usb_ram_offset <= 0 ;
  93               end
  94             else if(read_enable)
  95                 if( usb_ram_offset == 8'b11111111 )
  96                   begin
  97                     usb_ram_offset <= 0 ;
  98                     usb_ram_packet <= usb_ram_packet + 1 ;
  99                   end
 100                 else
 101                     usb_ram_offset <= usb_ram_offset + 1 ;
 102             if (usb_ram_ain == usb_ram_aout)
 103                isfull <= 0;
 104     end
 105
 106     /* RAM Reading Process */
 107     always @(posedge clock_out)
 108     begin
 109         ram_data_out <= usb_ram[usb_ram_aout] ;
 110     end
 111
 112 endmodule